[people/ms/u-boot.git] / board / renesas / salvator-x / salvator-x.c

/*
 * board/renesas/salvator-x/salvator-x.c
 *     This file is Salvator-X/Salvator-XS board support.
 *
 * Copyright (C) 2015-2017 Renesas Electronics Corporation
 * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 *
 * SPDX-License-Identifier: GPL-2.0+
 */

#include <common.h>
#include <malloc.h>
#include <netdev.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/sh_sdhi.h>
#include <i2c.h>
#include <mmc.h>

DECLARE_GLOBAL_DATA_PTR;

#define CPGWPCR	0xE6150904
#define CPGWPR  0xE615090C

#define CLK2MHZ(clk)	(clk / 1000 / 1000)
void s_init(void)
{
	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;

	/* Watchdog init */
	writel(0xA5A5A500, &rwdt->rwtcsra);
	writel(0xA5A5A500, &swdt->swtcsra);

	writel(0xA5A50000, CPGWPCR);
	writel(0xFFFFFFFF, CPGWPR);
}

#define GSX_MSTP112		BIT(12)	/* 3DG */
#define TMU0_MSTP125		BIT(25)	/* secure */
#define TMU1_MSTP124		BIT(24)	/* non-secure */
#define SCIF2_MSTP310		BIT(10)	/* SCIF2 */
#define ETHERAVB_MSTP812	BIT(12)
#define DVFS_MSTP926		BIT(26)
#define SD0_MSTP314		BIT(14)
#define SD1_MSTP313		BIT(13)
#define SD2_MSTP312		BIT(12)	/* either MMC0 */
#define SD3_MSTP311		BIT(11)	/* either MMC1 */

#define SD0CKCR			0xE6150074
#define SD1CKCR			0xE6150078
#define SD2CKCR			0xE6150268
#define SD3CKCR			0xE615026C

int board_early_init_f(void)
{
	/* TMU0,1 */		/* which use ? */
	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
	/* SCIF2 */
	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
	/* EHTERAVB */
	mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812);
	/* eMMC */
	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312);
	/* SDHI0, 3 */
	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314 | SD3_MSTP311);

	writel(1, SD0CKCR);
	writel(1, SD1CKCR);
	writel(1, SD2CKCR);
	writel(1, SD3CKCR);

#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
	/* DVFS for reset */
	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
#endif
	return 0;
}

/* SYSC */
/* R/- 32 Power status register 2(3DG) */
#define	SYSC_PWRSR2	0xE6180100
/* -/W 32 Power resume control register 2 (3DG) */
#define	SYSC_PWRONCR2	0xE618010C

int board_init(void)
{
	/* adress of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;

	/* Init PFC controller */
#if defined(CONFIG_R8A7795)
	r8a7795_pinmux_init();
#elif defined(CONFIG_R8A7796)
	r8a7796_pinmux_init();
#endif

#if defined(CONFIG_R8A7795)
	/* GSX: force power and clock supply */
	writel(0x0000001F, SYSC_PWRONCR2);
	while (readl(SYSC_PWRSR2) != 0x000003E0)
		mdelay(20);

	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
#endif

	/* USB1 pull-up */
	setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);

#ifdef CONFIG_RENESAS_RAVB
	/* EtherAVB Enable */
	/* GPSR2 */
	gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL);
	gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL);
	gpio_request(GPIO_GFN_AVB_LINK, NULL);
	gpio_request(GPIO_GFN_AVB_PHY_INT, NULL);
	gpio_request(GPIO_GFN_AVB_MAGIC, NULL);
	gpio_request(GPIO_GFN_AVB_MDC, NULL);

	/* IPSR0 */
	gpio_request(GPIO_IFN_AVB_MDC, NULL);
	gpio_request(GPIO_IFN_AVB_MAGIC, NULL);
	gpio_request(GPIO_IFN_AVB_PHY_INT, NULL);
	gpio_request(GPIO_IFN_AVB_LINK, NULL);
	gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL);
	gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL);
	/* IPSR1 */
	gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL);
	/* IPSR2 */
	gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL);
	/* IPSR3 */
	gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL);

#if defined(CONFIG_R8A7795)
	/* USB2_OVC */
	gpio_request(GPIO_GP_6_15, NULL);
	gpio_direction_input(GPIO_GP_6_15);

	/* USB2_PWEN */
	gpio_request(GPIO_GP_6_14, NULL);
	gpio_direction_output(GPIO_GP_6_14, 1);
	gpio_set_value(GPIO_GP_6_14, 1);
#endif
	/* AVB_PHY_RST */
	gpio_request(GPIO_GP_2_10, NULL);
	gpio_direction_output(GPIO_GP_2_10, 0);
	mdelay(20);
	gpio_set_value(GPIO_GP_2_10, 1);
	udelay(1);
#endif

#ifdef CONFIG_MMC
	/* SDHI0 */
	gpio_request(GPIO_GFN_SD0_DAT0, NULL);
	gpio_request(GPIO_GFN_SD0_DAT1, NULL);
	gpio_request(GPIO_GFN_SD0_DAT2, NULL);
	gpio_request(GPIO_GFN_SD0_DAT3, NULL);
	gpio_request(GPIO_GFN_SD0_CLK, NULL);
	gpio_request(GPIO_GFN_SD0_CMD, NULL);
	gpio_request(GPIO_GFN_SD0_CD, NULL);
	gpio_request(GPIO_GFN_SD0_WP, NULL);

	gpio_request(GPIO_GP_5_2, NULL);
	gpio_request(GPIO_GP_5_1, NULL);
	gpio_direction_output(GPIO_GP_5_2, 1);	/* power on */
	gpio_direction_output(GPIO_GP_5_1, 1);	/* 1: 3.3V, 0: 1.8V */

	/* SDHI1/SDHI2 eMMC */
	gpio_request(GPIO_GFN_SD1_DAT0, NULL);
	gpio_request(GPIO_GFN_SD1_DAT1, NULL);
	gpio_request(GPIO_GFN_SD1_DAT2, NULL);
	gpio_request(GPIO_GFN_SD1_DAT3, NULL);
	gpio_request(GPIO_GFN_SD2_DAT0, NULL);
	gpio_request(GPIO_GFN_SD2_DAT1, NULL);
	gpio_request(GPIO_GFN_SD2_DAT2, NULL);
	gpio_request(GPIO_GFN_SD2_DAT3, NULL);
	gpio_request(GPIO_GFN_SD2_CLK, NULL);
#if defined(CONFIG_R8A7795)
	gpio_request(GPIO_GFN_SD2_CMD, NULL);
#elif defined(CONFIG_R8A7796)
	gpio_request(GPIO_FN_SD2_CMD, NULL);
#else
#error Only R8A7795 and R87796 is supported
#endif
	gpio_request(GPIO_GP_5_3, NULL);
	gpio_request(GPIO_GP_5_9, NULL);
	gpio_direction_output(GPIO_GP_5_3, 0);	/* 1: 3.3V, 0: 1.8V */
	gpio_direction_output(GPIO_GP_5_9, 0);	/* 1: 3.3V, 0: 1.8V */

#if defined(CONFIG_R8A7795)
	/* SDHI3 */
	gpio_request(GPIO_GFN_SD3_DAT0, NULL);	/* GP_4_9 */
	gpio_request(GPIO_GFN_SD3_DAT1, NULL);	/* GP_4_10 */
	gpio_request(GPIO_GFN_SD3_DAT2, NULL);	/* GP_4_11 */
	gpio_request(GPIO_GFN_SD3_DAT3, NULL);	/* GP_4_12 */
	gpio_request(GPIO_GFN_SD3_CLK, NULL);	/* GP_4_7 */
	gpio_request(GPIO_GFN_SD3_CMD, NULL);	/* GP_4_8 */
#elif defined(CONFIG_R8A7796)
	gpio_request(GPIO_FN_SD3_DAT0, NULL);	/* GP_4_9 */
	gpio_request(GPIO_FN_SD3_DAT1, NULL);	/* GP_4_10 */
	gpio_request(GPIO_FN_SD3_DAT2, NULL);	/* GP_4_11 */
	gpio_request(GPIO_FN_SD3_DAT3, NULL);	/* GP_4_12 */
	gpio_request(GPIO_FN_SD3_CLK, NULL);	/* GP_4_7 */
	gpio_request(GPIO_FN_SD3_CMD, NULL);	/* GP_4_8 */
#else
#error Only R8A7795 and R87796 is supported
#endif
	/* IPSR10 */
	gpio_request(GPIO_FN_SD3_CD, NULL);
	gpio_request(GPIO_FN_SD3_WP, NULL);

	gpio_request(GPIO_GP_3_15, NULL);
	gpio_request(GPIO_GP_3_14, NULL);
	gpio_direction_output(GPIO_GP_3_15, 1);	/* power on */
	gpio_direction_output(GPIO_GP_3_14, 1);	/* 1: 3.3V, 0: 1.8V */
#endif

	return 0;
}

int dram_init(void)
{
	gd->ram_size = PHYS_SDRAM_1_SIZE;
#if (CONFIG_NR_DRAM_BANKS >= 2)
	gd->ram_size += PHYS_SDRAM_2_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 3)
	gd->ram_size += PHYS_SDRAM_3_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 4)
	gd->ram_size += PHYS_SDRAM_4_SIZE;
#endif

	return 0;
}

int dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
#if (CONFIG_NR_DRAM_BANKS >= 2)
	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 3)
	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 4)
	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
#endif
	return 0;
}

const struct rmobile_sysinfo sysinfo = {
	CONFIG_RCAR_BOARD_STRING
};

#define RST_BASE	0xE6160000
#define RST_CA57RESCNT	(RST_BASE + 0x40)
#define RST_CA53RESCNT	(RST_BASE + 0x44)
#define RST_RSTOUTCR	(RST_BASE + 0x58)
#define RST_CODE	0xA5A5000F

void reset_cpu(ulong addr)
{
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
	i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
#else
	/* only CA57 ? */
	writel(RST_CODE, RST_CA57RESCNT);
#endif
}
Commit	Line	Data
e525d34b NI	1	/*
e525d34b NI	2	* board/renesas/salvator-x/salvator-x.c
adf3057f	3	* This file is Salvator-X/Salvator-XS board support.
e525d34b	4	*
50fb0c45	5	* Copyright (C) 2015-2017 Renesas Electronics Corporation
e525d34b NI	6	* Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
	7	*
	8	* SPDX-License-Identifier: GPL-2.0+
	9	*/
	10
	11	#include <common.h>
	12	#include <malloc.h>
	13	#include <netdev.h>
	14	#include <dm.h>
	15	#include <dm/platform_data/serial_sh.h>
	16	#include <asm/processor.h>
	17	#include <asm/mach-types.h>
	18	#include <asm/io.h>
1221ce45	19	#include <linux/errno.h>
e525d34b NI	20	#include <asm/arch/sys_proto.h>
	21	#include <asm/gpio.h>
	22	#include <asm/arch/gpio.h>
	23	#include <asm/arch/rmobile.h>
	24	#include <asm/arch/rcar-mstp.h>
50fb0c45	25	#include <asm/arch/sh_sdhi.h>
e525d34b NI	26	#include <i2c.h>
	27	#include <mmc.h>
	28
	29	DECLARE_GLOBAL_DATA_PTR;
	30
	31	#define CPGWPCR 0xE6150904
	32	#define CPGWPR 0xE615090C
	33
	34	#define CLK2MHZ(clk) (clk / 1000 / 1000)
	35	void s_init(void)
	36	{
	37	struct rcar_rwdt rwdt = (struct rcar_rwdt )RWDT_BASE;
	38	struct rcar_swdt swdt = (struct rcar_swdt )SWDT_BASE;
	39
	40	/* Watchdog init */
	41	writel(0xA5A5A500, &rwdt->rwtcsra);
	42	writel(0xA5A5A500, &swdt->swtcsra);
	43
	44	writel(0xA5A50000, CPGWPCR);
	45	writel(0xFFFFFFFF, CPGWPR);
	46	}
	47
ae7a74a6 MV	48	#define GSX_MSTP112 BIT(12) /* 3DG */
	49	#define TMU0_MSTP125 BIT(25) /* secure */
	50	#define TMU1_MSTP124 BIT(24) /* non-secure */
	51	#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
90e53f8b	52	#define ETHERAVB_MSTP812 BIT(12)
fe2e8ff9	53	#define DVFS_MSTP926 BIT(26)
50fb0c45 MV	54	#define SD0_MSTP314 BIT(14)
	55	#define SD1_MSTP313 BIT(13)
	56	#define SD2_MSTP312 BIT(12) /* either MMC0 */
	57	#define SD3_MSTP311 BIT(11) /* either MMC1 */
	58
	59	#define SD0CKCR 0xE6150074
	60	#define SD1CKCR 0xE6150078
	61	#define SD2CKCR 0xE6150268
	62	#define SD3CKCR 0xE615026C
e525d34b NI	63
	64	int board_early_init_f(void)
	65	{
	66	/* TMU0,1 / / which use ? */
	67	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 \| TMU1_MSTP124);
	68	/* SCIF2 */
	69	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
90e53f8b MV	70	/* EHTERAVB */
90e53f8b MV	71	mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812);
50fb0c45 MV	72	/* eMMC */
	73	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 \| SD2_MSTP312);
	74	/* SDHI0, 3 */
	75	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314 \| SD3_MSTP311);
	76
183f5fd3 MV	77	writel(1, SD0CKCR);
	78	writel(1, SD1CKCR);
	79	writel(1, SD2CKCR);
	80	writel(1, SD3CKCR);
e525d34b	81
fe2e8ff9 MV	82	#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
	83	/* DVFS for reset */
	84	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
	85	#endif
e525d34b NI	86	return 0;
	87	}
	88
	89	/* SYSC */
	90	/* R/- 32 Power status register 2(3DG) */
	91	#define SYSC_PWRSR2 0xE6180100
	92	/* -/W 32 Power resume control register 2 (3DG) */
	93	#define SYSC_PWRONCR2 0xE618010C
	94
e525d34b NI	95	int board_init(void)
	96	{
	97	/* adress of boot parameters */
	98	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
	99
	100	/* Init PFC controller */
adf3057f	101	#if defined(CONFIG_R8A7795)
e525d34b	102	r8a7795_pinmux_init();
adf3057f MV	103	#elif defined(CONFIG_R8A7796)
	104	r8a7796_pinmux_init();
	105	#endif
e525d34b	106
adf3057f	107	#if defined(CONFIG_R8A7795)
e525d34b NI	108	/* GSX: force power and clock supply */
	109	writel(0x0000001F, SYSC_PWRONCR2);
	110	while (readl(SYSC_PWRSR2) != 0x000003E0)
	111	mdelay(20);
	112
	113	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
adf3057f	114	#endif
e525d34b	115
d1018f5f MV	116	/* USB1 pull-up */
	117	setbits_le32(PFC_PUEN6, PUEN_USB1_OVC \| PUEN_USB1_PWEN);
	118
3158b6f6	119	#ifdef CONFIG_RENESAS_RAVB
90e53f8b MV	120	/* EtherAVB Enable */
	121	/* GPSR2 */
	122	gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL);
	123	gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL);
	124	gpio_request(GPIO_GFN_AVB_LINK, NULL);
	125	gpio_request(GPIO_GFN_AVB_PHY_INT, NULL);
	126	gpio_request(GPIO_GFN_AVB_MAGIC, NULL);
	127	gpio_request(GPIO_GFN_AVB_MDC, NULL);
	128
	129	/* IPSR0 */
	130	gpio_request(GPIO_IFN_AVB_MDC, NULL);
	131	gpio_request(GPIO_IFN_AVB_MAGIC, NULL);
	132	gpio_request(GPIO_IFN_AVB_PHY_INT, NULL);
	133	gpio_request(GPIO_IFN_AVB_LINK, NULL);
	134	gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL);
	135	gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL);
	136	/* IPSR1 */
	137	gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL);
	138	/* IPSR2 */
	139	gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL);
	140	/* IPSR3 */
	141	gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL);
	142
adf3057f	143	#if defined(CONFIG_R8A7795)
d1018f5f MV	144	/* USB2_OVC */
	145	gpio_request(GPIO_GP_6_15, NULL);
	146	gpio_direction_input(GPIO_GP_6_15);
	147
	148	/* USB2_PWEN */
	149	gpio_request(GPIO_GP_6_14, NULL);
	150	gpio_direction_output(GPIO_GP_6_14, 1);
	151	gpio_set_value(GPIO_GP_6_14, 1);
adf3057f	152	#endif
90e53f8b MV	153	/* AVB_PHY_RST */
	154	gpio_request(GPIO_GP_2_10, NULL);
	155	gpio_direction_output(GPIO_GP_2_10, 0);
	156	mdelay(20);
	157	gpio_set_value(GPIO_GP_2_10, 1);
	158	udelay(1);
	159	#endif
	160
8212f563	161	#ifdef CONFIG_MMC
50fb0c45 MV	162	/* SDHI0 */
	163	gpio_request(GPIO_GFN_SD0_DAT0, NULL);
	164	gpio_request(GPIO_GFN_SD0_DAT1, NULL);
	165	gpio_request(GPIO_GFN_SD0_DAT2, NULL);
	166	gpio_request(GPIO_GFN_SD0_DAT3, NULL);
	167	gpio_request(GPIO_GFN_SD0_CLK, NULL);
	168	gpio_request(GPIO_GFN_SD0_CMD, NULL);
	169	gpio_request(GPIO_GFN_SD0_CD, NULL);
	170	gpio_request(GPIO_GFN_SD0_WP, NULL);
	171
	172	gpio_request(GPIO_GP_5_2, NULL);
	173	gpio_request(GPIO_GP_5_1, NULL);
	174	gpio_direction_output(GPIO_GP_5_2, 1); /* power on */
	175	gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */
	176
50fb0c45 MV	177	/* SDHI1/SDHI2 eMMC */
	178	gpio_request(GPIO_GFN_SD1_DAT0, NULL);
	179	gpio_request(GPIO_GFN_SD1_DAT1, NULL);
	180	gpio_request(GPIO_GFN_SD1_DAT2, NULL);
	181	gpio_request(GPIO_GFN_SD1_DAT3, NULL);
	182	gpio_request(GPIO_GFN_SD2_DAT0, NULL);
	183	gpio_request(GPIO_GFN_SD2_DAT1, NULL);
	184	gpio_request(GPIO_GFN_SD2_DAT2, NULL);
	185	gpio_request(GPIO_GFN_SD2_DAT3, NULL);
	186	gpio_request(GPIO_GFN_SD2_CLK, NULL);
adf3057f	187	#if defined(CONFIG_R8A7795)
50fb0c45	188	gpio_request(GPIO_GFN_SD2_CMD, NULL);
adf3057f MV	189	#elif defined(CONFIG_R8A7796)
	190	gpio_request(GPIO_FN_SD2_CMD, NULL);
	191	#else
	192	#error Only R8A7795 and R87796 is supported
	193	#endif
50fb0c45 MV	194	gpio_request(GPIO_GP_5_3, NULL);
	195	gpio_request(GPIO_GP_5_9, NULL);
	196	gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */
	197	gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */
	198
adf3057f	199	#if defined(CONFIG_R8A7795)
50fb0c45 MV	200	/* SDHI3 */
	201	gpio_request(GPIO_GFN_SD3_DAT0, NULL); /* GP_4_9 */
	202	gpio_request(GPIO_GFN_SD3_DAT1, NULL); /* GP_4_10 */
	203	gpio_request(GPIO_GFN_SD3_DAT2, NULL); /* GP_4_11 */
	204	gpio_request(GPIO_GFN_SD3_DAT3, NULL); /* GP_4_12 */
	205	gpio_request(GPIO_GFN_SD3_CLK, NULL); /* GP_4_7 */
	206	gpio_request(GPIO_GFN_SD3_CMD, NULL); /* GP_4_8 */
adf3057f MV	207	#elif defined(CONFIG_R8A7796)
	208	gpio_request(GPIO_FN_SD3_DAT0, NULL); /* GP_4_9 */
	209	gpio_request(GPIO_FN_SD3_DAT1, NULL); /* GP_4_10 */
	210	gpio_request(GPIO_FN_SD3_DAT2, NULL); /* GP_4_11 */
	211	gpio_request(GPIO_FN_SD3_DAT3, NULL); /* GP_4_12 */
	212	gpio_request(GPIO_FN_SD3_CLK, NULL); /* GP_4_7 */
	213	gpio_request(GPIO_FN_SD3_CMD, NULL); /* GP_4_8 */
	214	#else
	215	#error Only R8A7795 and R87796 is supported
	216	#endif
50fb0c45 MV	217	/* IPSR10 */
	218	gpio_request(GPIO_FN_SD3_CD, NULL);
	219	gpio_request(GPIO_FN_SD3_WP, NULL);
	220
	221	gpio_request(GPIO_GP_3_15, NULL);
	222	gpio_request(GPIO_GP_3_14, NULL);
	223	gpio_direction_output(GPIO_GP_3_15, 1); /* power on */
	224	gpio_direction_output(GPIO_GP_3_14, 1); /* 1: 3.3V, 0: 1.8V */
8212f563	225	#endif
50fb0c45	226
ddb39a07	227	return 0;
50fb0c45	228	}
50fb0c45	229
e525d34b NI	230	int dram_init(void)
e525d34b NI	231	{
8f284e66 MV	232	gd->ram_size = PHYS_SDRAM_1_SIZE;
	233	#if (CONFIG_NR_DRAM_BANKS >= 2)
	234	gd->ram_size += PHYS_SDRAM_2_SIZE;
	235	#endif
	236	#if (CONFIG_NR_DRAM_BANKS >= 3)
	237	gd->ram_size += PHYS_SDRAM_3_SIZE;
	238	#endif
	239	#if (CONFIG_NR_DRAM_BANKS >= 4)
	240	gd->ram_size += PHYS_SDRAM_4_SIZE;
	241	#endif
	242
	243	return 0;
	244	}
e525d34b	245
8f284e66 MV	246	int dram_init_banksize(void)
	247	{
	248	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	249	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
	250	#if (CONFIG_NR_DRAM_BANKS >= 2)
	251	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
	252	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
	253	#endif
	254	#if (CONFIG_NR_DRAM_BANKS >= 3)
	255	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
	256	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
	257	#endif
	258	#if (CONFIG_NR_DRAM_BANKS >= 4)
	259	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
	260	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
	261	#endif
e525d34b NI	262	return 0;
	263	}
	264
	265	const struct rmobile_sysinfo sysinfo = {
	266	CONFIG_RCAR_BOARD_STRING
	267	};
	268
	269	#define RST_BASE 0xE6160000
	270	#define RST_CA57RESCNT (RST_BASE + 0x40)
	271	#define RST_CA53RESCNT (RST_BASE + 0x44)
	272	#define RST_RSTOUTCR (RST_BASE + 0x58)
	273	#define RST_CODE 0xA5A5000F
	274
	275	void reset_cpu(ulong addr)
	276	{
fe2e8ff9 MV	277	#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
	278	i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
	279	#else
e525d34b NI	280	/* only CA57 ? */
e525d34b NI	281	writel(RST_CODE, RST_CA57RESCNT);
fe2e8ff9	282	#endif
e525d34b	283	}