[people/ms/u-boot.git] / board / renesas / salvator-x / salvator-x.c

/*
 * board/renesas/salvator-x/salvator-x.c
 *     This file is Salvator-X board support.
 *
 * Copyright (C) 2015-2017 Renesas Electronics Corporation
 * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 *
 * SPDX-License-Identifier: GPL-2.0+
 */

#include <common.h>
#include <malloc.h>
#include <netdev.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/sh_sdhi.h>
#include <i2c.h>
#include <mmc.h>

DECLARE_GLOBAL_DATA_PTR;

#define CPGWPCR	0xE6150904
#define CPGWPR  0xE615090C

#define CLK2MHZ(clk)	(clk / 1000 / 1000)
void s_init(void)
{
	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;

	/* Watchdog init */
	writel(0xA5A5A500, &rwdt->rwtcsra);
	writel(0xA5A5A500, &swdt->swtcsra);

	writel(0xA5A50000, CPGWPCR);
	writel(0xFFFFFFFF, CPGWPR);
}

#define GSX_MSTP112		BIT(12)	/* 3DG */
#define TMU0_MSTP125		BIT(25)	/* secure */
#define TMU1_MSTP124		BIT(24)	/* non-secure */
#define SCIF2_MSTP310		BIT(10)	/* SCIF2 */
#define SD0_MSTP314		BIT(14)
#define SD1_MSTP313		BIT(13)
#define SD2_MSTP312		BIT(12)	/* either MMC0 */
#define SD3_MSTP311		BIT(11)	/* either MMC1 */

#define SD0CKCR			0xE6150074
#define SD1CKCR			0xE6150078
#define SD2CKCR			0xE6150268
#define SD3CKCR			0xE615026C

int board_early_init_f(void)
{
	/* TMU0,1 */		/* which use ? */
	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
	/* SCIF2 */
	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
	/* eMMC */
	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312);
	/* SDHI0, 3 */
	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314 | SD3_MSTP311);

	writel(0, SD0CKCR);
	writel(0, SD1CKCR);
	writel(0, SD2CKCR);
	writel(0, SD3CKCR);

	return 0;
}

/* SYSC */
/* R/- 32 Power status register 2(3DG) */
#define	SYSC_PWRSR2	0xE6180100
/* -/W 32 Power resume control register 2 (3DG) */
#define	SYSC_PWRONCR2	0xE618010C

int board_init(void)
{
	/* adress of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;

	/* Init PFC controller */
	r8a7795_pinmux_init();

	/* GSX: force power and clock supply */
	writel(0x0000001F, SYSC_PWRONCR2);
	while (readl(SYSC_PWRSR2) != 0x000003E0)
		mdelay(20);

	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);

	return 0;
}

#ifdef CONFIG_SH_SDHI
int board_mmc_init(bd_t *bis)
{
	int ret = -ENODEV;

	/* SDHI0 */
	gpio_request(GPIO_GFN_SD0_DAT0, NULL);
	gpio_request(GPIO_GFN_SD0_DAT1, NULL);
	gpio_request(GPIO_GFN_SD0_DAT2, NULL);
	gpio_request(GPIO_GFN_SD0_DAT3, NULL);
	gpio_request(GPIO_GFN_SD0_CLK, NULL);
	gpio_request(GPIO_GFN_SD0_CMD, NULL);
	gpio_request(GPIO_GFN_SD0_CD, NULL);
	gpio_request(GPIO_GFN_SD0_WP, NULL);

	gpio_request(GPIO_GP_5_2, NULL);
	gpio_request(GPIO_GP_5_1, NULL);
	gpio_direction_output(GPIO_GP_5_2, 1);	/* power on */
	gpio_direction_output(GPIO_GP_5_1, 1);	/* 1: 3.3V, 0: 1.8V */

	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
			   SH_SDHI_QUIRK_64BIT_BUF);
	if (ret)
		return ret;

	/* SDHI1/SDHI2 eMMC */
	gpio_request(GPIO_GFN_SD1_DAT0, NULL);
	gpio_request(GPIO_GFN_SD1_DAT1, NULL);
	gpio_request(GPIO_GFN_SD1_DAT2, NULL);
	gpio_request(GPIO_GFN_SD1_DAT3, NULL);
	gpio_request(GPIO_GFN_SD2_DAT0, NULL);
	gpio_request(GPIO_GFN_SD2_DAT1, NULL);
	gpio_request(GPIO_GFN_SD2_DAT2, NULL);
	gpio_request(GPIO_GFN_SD2_DAT3, NULL);
	gpio_request(GPIO_GFN_SD2_CLK, NULL);
	gpio_request(GPIO_GFN_SD2_CMD, NULL);
	gpio_request(GPIO_GP_5_3, NULL);
	gpio_request(GPIO_GP_5_9, NULL);
	gpio_direction_output(GPIO_GP_5_3, 0);	/* 1: 3.3V, 0: 1.8V */
	gpio_direction_output(GPIO_GP_5_9, 0);	/* 1: 3.3V, 0: 1.8V */

	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 1,
			   SH_SDHI_QUIRK_64BIT_BUF);
	if (ret)
		return ret;

	/* SDHI3 */
	gpio_request(GPIO_GFN_SD3_DAT0, NULL);	/* GP_4_9 */
	gpio_request(GPIO_GFN_SD3_DAT1, NULL);	/* GP_4_10 */
	gpio_request(GPIO_GFN_SD3_DAT2, NULL);	/* GP_4_11 */
	gpio_request(GPIO_GFN_SD3_DAT3, NULL);	/* GP_4_12 */
	gpio_request(GPIO_GFN_SD3_CLK, NULL);	/* GP_4_7 */
	gpio_request(GPIO_GFN_SD3_CMD, NULL);	/* GP_4_8 */
	/* IPSR10 */
	gpio_request(GPIO_FN_SD3_CD, NULL);
	gpio_request(GPIO_FN_SD3_WP, NULL);

	gpio_request(GPIO_GP_3_15, NULL);
	gpio_request(GPIO_GP_3_14, NULL);
	gpio_direction_output(GPIO_GP_3_15, 1);	/* power on */
	gpio_direction_output(GPIO_GP_3_14, 1);	/* 1: 3.3V, 0: 1.8V */

	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI3_BASE, 2,
			   SH_SDHI_QUIRK_64BIT_BUF);
	return ret;
}
#endif

int dram_init(void)
{
	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;

	return 0;
}

const struct rmobile_sysinfo sysinfo = {
	CONFIG_RCAR_BOARD_STRING
};

#define RST_BASE	0xE6160000
#define RST_CA57RESCNT	(RST_BASE + 0x40)
#define RST_CA53RESCNT	(RST_BASE + 0x44)
#define RST_RSTOUTCR	(RST_BASE + 0x58)
#define RST_CODE	0xA5A5000F

void reset_cpu(ulong addr)
{
	/* only CA57 ? */
	writel(RST_CODE, RST_CA57RESCNT);
}

static const struct sh_serial_platdata serial_platdata = {
	.base = SCIF2_BASE,
	.type = PORT_SCIF,
	.clk = CONFIG_SH_SCIF_CLK_FREQ,
	.clk_mode = INT_CLK,
};

U_BOOT_DEVICE(salvator_x_scif2) = {
	.name = "serial_sh",
	.platdata = &serial_platdata,
};
Commit	Line	Data
e525d34b NI	1	/*
	2	* board/renesas/salvator-x/salvator-x.c
	3	* This file is Salvator-X board support.
	4	*
50fb0c45	5	* Copyright (C) 2015-2017 Renesas Electronics Corporation
e525d34b NI	6	* Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
	7	*
	8	* SPDX-License-Identifier: GPL-2.0+
	9	*/
	10
	11	#include <common.h>
	12	#include <malloc.h>
	13	#include <netdev.h>
	14	#include <dm.h>
	15	#include <dm/platform_data/serial_sh.h>
	16	#include <asm/processor.h>
	17	#include <asm/mach-types.h>
	18	#include <asm/io.h>
1221ce45	19	#include <linux/errno.h>
e525d34b NI	20	#include <asm/arch/sys_proto.h>
	21	#include <asm/gpio.h>
	22	#include <asm/arch/gpio.h>
	23	#include <asm/arch/rmobile.h>
	24	#include <asm/arch/rcar-mstp.h>
50fb0c45	25	#include <asm/arch/sh_sdhi.h>
e525d34b NI	26	#include <i2c.h>
	27	#include <mmc.h>
	28
	29	DECLARE_GLOBAL_DATA_PTR;
	30
	31	#define CPGWPCR 0xE6150904
	32	#define CPGWPR 0xE615090C
	33
	34	#define CLK2MHZ(clk) (clk / 1000 / 1000)
	35	void s_init(void)
	36	{
	37	struct rcar_rwdt rwdt = (struct rcar_rwdt )RWDT_BASE;
	38	struct rcar_swdt swdt = (struct rcar_swdt )SWDT_BASE;
	39
	40	/* Watchdog init */
	41	writel(0xA5A5A500, &rwdt->rwtcsra);
	42	writel(0xA5A5A500, &swdt->swtcsra);
	43
	44	writel(0xA5A50000, CPGWPCR);
	45	writel(0xFFFFFFFF, CPGWPR);
	46	}
	47
ae7a74a6 MV	48	#define GSX_MSTP112 BIT(12) /* 3DG */
	49	#define TMU0_MSTP125 BIT(25) /* secure */
	50	#define TMU1_MSTP124 BIT(24) /* non-secure */
	51	#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
50fb0c45 MV	52	#define SD0_MSTP314 BIT(14)
	53	#define SD1_MSTP313 BIT(13)
	54	#define SD2_MSTP312 BIT(12) /* either MMC0 */
	55	#define SD3_MSTP311 BIT(11) /* either MMC1 */
	56
	57	#define SD0CKCR 0xE6150074
	58	#define SD1CKCR 0xE6150078
	59	#define SD2CKCR 0xE6150268
	60	#define SD3CKCR 0xE615026C
e525d34b NI	61
	62	int board_early_init_f(void)
	63	{
	64	/* TMU0,1 / / which use ? */
	65	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 \| TMU1_MSTP124);
	66	/* SCIF2 */
	67	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
50fb0c45 MV	68	/* eMMC */
	69	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 \| SD2_MSTP312);
	70	/* SDHI0, 3 */
	71	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314 \| SD3_MSTP311);
	72
	73	writel(0, SD0CKCR);
	74	writel(0, SD1CKCR);
	75	writel(0, SD2CKCR);
	76	writel(0, SD3CKCR);
e525d34b NI	77
	78	return 0;
	79	}
	80
	81	/* SYSC */
	82	/* R/- 32 Power status register 2(3DG) */
	83	#define SYSC_PWRSR2 0xE6180100
	84	/* -/W 32 Power resume control register 2 (3DG) */
	85	#define SYSC_PWRONCR2 0xE618010C
	86
e525d34b NI	87	int board_init(void)
	88	{
	89	/* adress of boot parameters */
	90	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
	91
	92	/* Init PFC controller */
	93	r8a7795_pinmux_init();
	94
	95	/* GSX: force power and clock supply */
	96	writel(0x0000001F, SYSC_PWRONCR2);
	97	while (readl(SYSC_PWRSR2) != 0x000003E0)
	98	mdelay(20);
	99
	100	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
	101
	102	return 0;
	103	}
	104
50fb0c45 MV	105	#ifdef CONFIG_SH_SDHI
	106	int board_mmc_init(bd_t *bis)
	107	{
	108	int ret = -ENODEV;
	109
	110	/* SDHI0 */
	111	gpio_request(GPIO_GFN_SD0_DAT0, NULL);
	112	gpio_request(GPIO_GFN_SD0_DAT1, NULL);
	113	gpio_request(GPIO_GFN_SD0_DAT2, NULL);
	114	gpio_request(GPIO_GFN_SD0_DAT3, NULL);
	115	gpio_request(GPIO_GFN_SD0_CLK, NULL);
	116	gpio_request(GPIO_GFN_SD0_CMD, NULL);
	117	gpio_request(GPIO_GFN_SD0_CD, NULL);
	118	gpio_request(GPIO_GFN_SD0_WP, NULL);
	119
	120	gpio_request(GPIO_GP_5_2, NULL);
	121	gpio_request(GPIO_GP_5_1, NULL);
	122	gpio_direction_output(GPIO_GP_5_2, 1); /* power on */
	123	gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */
	124
	125	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
	126	SH_SDHI_QUIRK_64BIT_BUF);
	127	if (ret)
	128	return ret;
	129
	130	/* SDHI1/SDHI2 eMMC */
	131	gpio_request(GPIO_GFN_SD1_DAT0, NULL);
	132	gpio_request(GPIO_GFN_SD1_DAT1, NULL);
	133	gpio_request(GPIO_GFN_SD1_DAT2, NULL);
	134	gpio_request(GPIO_GFN_SD1_DAT3, NULL);
	135	gpio_request(GPIO_GFN_SD2_DAT0, NULL);
	136	gpio_request(GPIO_GFN_SD2_DAT1, NULL);
	137	gpio_request(GPIO_GFN_SD2_DAT2, NULL);
	138	gpio_request(GPIO_GFN_SD2_DAT3, NULL);
	139	gpio_request(GPIO_GFN_SD2_CLK, NULL);
	140	gpio_request(GPIO_GFN_SD2_CMD, NULL);
	141	gpio_request(GPIO_GP_5_3, NULL);
	142	gpio_request(GPIO_GP_5_9, NULL);
	143	gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */
	144	gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */
	145
	146	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 1,
	147	SH_SDHI_QUIRK_64BIT_BUF);
	148	if (ret)
	149	return ret;
	150
	151	/* SDHI3 */
	152	gpio_request(GPIO_GFN_SD3_DAT0, NULL); /* GP_4_9 */
	153	gpio_request(GPIO_GFN_SD3_DAT1, NULL); /* GP_4_10 */
	154	gpio_request(GPIO_GFN_SD3_DAT2, NULL); /* GP_4_11 */
	155	gpio_request(GPIO_GFN_SD3_DAT3, NULL); /* GP_4_12 */
	156	gpio_request(GPIO_GFN_SD3_CLK, NULL); /* GP_4_7 */
	157	gpio_request(GPIO_GFN_SD3_CMD, NULL); /* GP_4_8 */
	158	/* IPSR10 */
	159	gpio_request(GPIO_FN_SD3_CD, NULL);
	160	gpio_request(GPIO_FN_SD3_WP, NULL);
	161
	162	gpio_request(GPIO_GP_3_15, NULL);
	163	gpio_request(GPIO_GP_3_14, NULL);
	164	gpio_direction_output(GPIO_GP_3_15, 1); /* power on */
	165	gpio_direction_output(GPIO_GP_3_14, 1); /* 1: 3.3V, 0: 1.8V */
	166
	167	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI3_BASE, 2,
	168	SH_SDHI_QUIRK_64BIT_BUF);
169	return ret;
170	}
171	#endif
172
e525d34b NI	173	int dram_init(void)
	174	{
	175	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
	176
	177	return 0;
	178	}
	179
	180	const struct rmobile_sysinfo sysinfo = {
	181	CONFIG_RCAR_BOARD_STRING
	182	};
	183
	184	#define RST_BASE 0xE6160000
	185	#define RST_CA57RESCNT (RST_BASE + 0x40)
	186	#define RST_CA53RESCNT (RST_BASE + 0x44)
	187	#define RST_RSTOUTCR (RST_BASE + 0x58)
	188	#define RST_CODE 0xA5A5000F
	189
	190	void reset_cpu(ulong addr)
	191	{
	192	/* only CA57 ? */
	193	writel(RST_CODE, RST_CA57RESCNT);
	194	}
	195
	196	static const struct sh_serial_platdata serial_platdata = {
	197	.base = SCIF2_BASE,
	198	.type = PORT_SCIF,
8474681c MV	199	.clk = CONFIG_SH_SCIF_CLK_FREQ,
8474681c MV	200	.clk_mode = INT_CLK,
e525d34b NI	201	};
	202
	203	U_BOOT_DEVICE(salvator_x_scif2) = {
	204	.name = "serial_sh",
	205	.platdata = &serial_platdata,
	206	};