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e525d34b NI |
1 | /* |
2 | * board/renesas/salvator-x/salvator-x.c | |
adf3057f | 3 | * This file is Salvator-X/Salvator-XS board support. |
e525d34b | 4 | * |
50fb0c45 | 5 | * Copyright (C) 2015-2017 Renesas Electronics Corporation |
e525d34b NI |
6 | * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
7 | * | |
8 | * SPDX-License-Identifier: GPL-2.0+ | |
9 | */ | |
10 | ||
11 | #include <common.h> | |
12 | #include <malloc.h> | |
13 | #include <netdev.h> | |
14 | #include <dm.h> | |
15 | #include <dm/platform_data/serial_sh.h> | |
16 | #include <asm/processor.h> | |
17 | #include <asm/mach-types.h> | |
18 | #include <asm/io.h> | |
1221ce45 | 19 | #include <linux/errno.h> |
e525d34b NI |
20 | #include <asm/arch/sys_proto.h> |
21 | #include <asm/gpio.h> | |
22 | #include <asm/arch/gpio.h> | |
23 | #include <asm/arch/rmobile.h> | |
24 | #include <asm/arch/rcar-mstp.h> | |
50fb0c45 | 25 | #include <asm/arch/sh_sdhi.h> |
e525d34b NI |
26 | #include <i2c.h> |
27 | #include <mmc.h> | |
28 | ||
29 | DECLARE_GLOBAL_DATA_PTR; | |
30 | ||
31 | #define CPGWPCR 0xE6150904 | |
32 | #define CPGWPR 0xE615090C | |
33 | ||
34 | #define CLK2MHZ(clk) (clk / 1000 / 1000) | |
35 | void s_init(void) | |
36 | { | |
37 | struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; | |
38 | struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; | |
39 | ||
40 | /* Watchdog init */ | |
41 | writel(0xA5A5A500, &rwdt->rwtcsra); | |
42 | writel(0xA5A5A500, &swdt->swtcsra); | |
43 | ||
44 | writel(0xA5A50000, CPGWPCR); | |
45 | writel(0xFFFFFFFF, CPGWPR); | |
46 | } | |
47 | ||
ae7a74a6 MV |
48 | #define GSX_MSTP112 BIT(12) /* 3DG */ |
49 | #define TMU0_MSTP125 BIT(25) /* secure */ | |
50 | #define TMU1_MSTP124 BIT(24) /* non-secure */ | |
51 | #define SCIF2_MSTP310 BIT(10) /* SCIF2 */ | |
fe2e8ff9 | 52 | #define DVFS_MSTP926 BIT(26) |
afb19d65 | 53 | #define HSUSB_MSTP704 BIT(4) /* HSUSB */ |
50fb0c45 | 54 | |
e525d34b NI |
55 | int board_early_init_f(void) |
56 | { | |
57 | /* TMU0,1 */ /* which use ? */ | |
58 | mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124); | |
e525d34b | 59 | |
fe2e8ff9 MV |
60 | #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) |
61 | /* DVFS for reset */ | |
62 | mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926); | |
63 | #endif | |
e525d34b NI |
64 | return 0; |
65 | } | |
66 | ||
67 | /* SYSC */ | |
68 | /* R/- 32 Power status register 2(3DG) */ | |
69 | #define SYSC_PWRSR2 0xE6180100 | |
70 | /* -/W 32 Power resume control register 2 (3DG) */ | |
71 | #define SYSC_PWRONCR2 0xE618010C | |
72 | ||
afb19d65 MV |
73 | /* HSUSB block registers */ |
74 | #define HSUSB_REG_LPSTS 0xE6590102 | |
75 | #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) | |
76 | #define HSUSB_REG_UGCTRL2 0xE6590184 | |
77 | #define HSUSB_REG_UGCTRL2_USB0SEL 0x30 | |
78 | #define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10 | |
79 | ||
e525d34b NI |
80 | int board_init(void) |
81 | { | |
82 | /* adress of boot parameters */ | |
83 | gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; | |
84 | ||
85 | /* Init PFC controller */ | |
adf3057f | 86 | #if defined(CONFIG_R8A7795) |
e525d34b | 87 | r8a7795_pinmux_init(); |
adf3057f MV |
88 | #elif defined(CONFIG_R8A7796) |
89 | r8a7796_pinmux_init(); | |
90 | #endif | |
e525d34b | 91 | |
adf3057f | 92 | #if defined(CONFIG_R8A7795) |
e525d34b NI |
93 | /* GSX: force power and clock supply */ |
94 | writel(0x0000001F, SYSC_PWRONCR2); | |
95 | while (readl(SYSC_PWRSR2) != 0x000003E0) | |
96 | mdelay(20); | |
97 | ||
98 | mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112); | |
adf3057f | 99 | #endif |
e525d34b | 100 | |
d1018f5f MV |
101 | /* USB1 pull-up */ |
102 | setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); | |
103 | ||
afb19d65 MV |
104 | /* Configure the HSUSB block */ |
105 | mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704); | |
106 | /* Choice USB0SEL */ | |
107 | clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL, | |
108 | HSUSB_REG_UGCTRL2_USB0SEL_EHCI); | |
109 | /* low power status */ | |
110 | setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL); | |
111 | ||
3158b6f6 | 112 | #ifdef CONFIG_RENESAS_RAVB |
90e53f8b MV |
113 | /* EtherAVB Enable */ |
114 | /* GPSR2 */ | |
115 | gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL); | |
116 | gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL); | |
117 | gpio_request(GPIO_GFN_AVB_LINK, NULL); | |
118 | gpio_request(GPIO_GFN_AVB_PHY_INT, NULL); | |
119 | gpio_request(GPIO_GFN_AVB_MAGIC, NULL); | |
120 | gpio_request(GPIO_GFN_AVB_MDC, NULL); | |
121 | ||
122 | /* IPSR0 */ | |
123 | gpio_request(GPIO_IFN_AVB_MDC, NULL); | |
124 | gpio_request(GPIO_IFN_AVB_MAGIC, NULL); | |
125 | gpio_request(GPIO_IFN_AVB_PHY_INT, NULL); | |
126 | gpio_request(GPIO_IFN_AVB_LINK, NULL); | |
127 | gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL); | |
128 | gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL); | |
129 | /* IPSR1 */ | |
130 | gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL); | |
131 | /* IPSR2 */ | |
132 | gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL); | |
133 | /* IPSR3 */ | |
134 | gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL); | |
135 | ||
adf3057f | 136 | #if defined(CONFIG_R8A7795) |
d1018f5f MV |
137 | /* USB2_OVC */ |
138 | gpio_request(GPIO_GP_6_15, NULL); | |
139 | gpio_direction_input(GPIO_GP_6_15); | |
140 | ||
141 | /* USB2_PWEN */ | |
142 | gpio_request(GPIO_GP_6_14, NULL); | |
143 | gpio_direction_output(GPIO_GP_6_14, 1); | |
144 | gpio_set_value(GPIO_GP_6_14, 1); | |
adf3057f | 145 | #endif |
90e53f8b MV |
146 | /* AVB_PHY_RST */ |
147 | gpio_request(GPIO_GP_2_10, NULL); | |
148 | gpio_direction_output(GPIO_GP_2_10, 0); | |
149 | mdelay(20); | |
150 | gpio_set_value(GPIO_GP_2_10, 1); | |
151 | udelay(1); | |
152 | #endif | |
153 | ||
8212f563 | 154 | #ifdef CONFIG_MMC |
50fb0c45 MV |
155 | /* SDHI0 */ |
156 | gpio_request(GPIO_GFN_SD0_DAT0, NULL); | |
157 | gpio_request(GPIO_GFN_SD0_DAT1, NULL); | |
158 | gpio_request(GPIO_GFN_SD0_DAT2, NULL); | |
159 | gpio_request(GPIO_GFN_SD0_DAT3, NULL); | |
160 | gpio_request(GPIO_GFN_SD0_CLK, NULL); | |
161 | gpio_request(GPIO_GFN_SD0_CMD, NULL); | |
162 | gpio_request(GPIO_GFN_SD0_CD, NULL); | |
163 | gpio_request(GPIO_GFN_SD0_WP, NULL); | |
164 | ||
165 | gpio_request(GPIO_GP_5_2, NULL); | |
166 | gpio_request(GPIO_GP_5_1, NULL); | |
167 | gpio_direction_output(GPIO_GP_5_2, 1); /* power on */ | |
168 | gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */ | |
169 | ||
50fb0c45 MV |
170 | /* SDHI1/SDHI2 eMMC */ |
171 | gpio_request(GPIO_GFN_SD1_DAT0, NULL); | |
172 | gpio_request(GPIO_GFN_SD1_DAT1, NULL); | |
173 | gpio_request(GPIO_GFN_SD1_DAT2, NULL); | |
174 | gpio_request(GPIO_GFN_SD1_DAT3, NULL); | |
175 | gpio_request(GPIO_GFN_SD2_DAT0, NULL); | |
176 | gpio_request(GPIO_GFN_SD2_DAT1, NULL); | |
177 | gpio_request(GPIO_GFN_SD2_DAT2, NULL); | |
178 | gpio_request(GPIO_GFN_SD2_DAT3, NULL); | |
179 | gpio_request(GPIO_GFN_SD2_CLK, NULL); | |
adf3057f | 180 | #if defined(CONFIG_R8A7795) |
50fb0c45 | 181 | gpio_request(GPIO_GFN_SD2_CMD, NULL); |
adf3057f MV |
182 | #elif defined(CONFIG_R8A7796) |
183 | gpio_request(GPIO_FN_SD2_CMD, NULL); | |
184 | #else | |
185 | #error Only R8A7795 and R87796 is supported | |
186 | #endif | |
50fb0c45 MV |
187 | gpio_request(GPIO_GP_5_3, NULL); |
188 | gpio_request(GPIO_GP_5_9, NULL); | |
189 | gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */ | |
190 | gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */ | |
191 | ||
adf3057f | 192 | #if defined(CONFIG_R8A7795) |
50fb0c45 MV |
193 | /* SDHI3 */ |
194 | gpio_request(GPIO_GFN_SD3_DAT0, NULL); /* GP_4_9 */ | |
195 | gpio_request(GPIO_GFN_SD3_DAT1, NULL); /* GP_4_10 */ | |
196 | gpio_request(GPIO_GFN_SD3_DAT2, NULL); /* GP_4_11 */ | |
197 | gpio_request(GPIO_GFN_SD3_DAT3, NULL); /* GP_4_12 */ | |
198 | gpio_request(GPIO_GFN_SD3_CLK, NULL); /* GP_4_7 */ | |
199 | gpio_request(GPIO_GFN_SD3_CMD, NULL); /* GP_4_8 */ | |
adf3057f MV |
200 | #elif defined(CONFIG_R8A7796) |
201 | gpio_request(GPIO_FN_SD3_DAT0, NULL); /* GP_4_9 */ | |
202 | gpio_request(GPIO_FN_SD3_DAT1, NULL); /* GP_4_10 */ | |
203 | gpio_request(GPIO_FN_SD3_DAT2, NULL); /* GP_4_11 */ | |
204 | gpio_request(GPIO_FN_SD3_DAT3, NULL); /* GP_4_12 */ | |
205 | gpio_request(GPIO_FN_SD3_CLK, NULL); /* GP_4_7 */ | |
206 | gpio_request(GPIO_FN_SD3_CMD, NULL); /* GP_4_8 */ | |
207 | #else | |
208 | #error Only R8A7795 and R87796 is supported | |
209 | #endif | |
50fb0c45 MV |
210 | /* IPSR10 */ |
211 | gpio_request(GPIO_FN_SD3_CD, NULL); | |
212 | gpio_request(GPIO_FN_SD3_WP, NULL); | |
213 | ||
214 | gpio_request(GPIO_GP_3_15, NULL); | |
215 | gpio_request(GPIO_GP_3_14, NULL); | |
216 | gpio_direction_output(GPIO_GP_3_15, 1); /* power on */ | |
217 | gpio_direction_output(GPIO_GP_3_14, 1); /* 1: 3.3V, 0: 1.8V */ | |
8212f563 | 218 | #endif |
50fb0c45 | 219 | |
ddb39a07 | 220 | return 0; |
50fb0c45 | 221 | } |
50fb0c45 | 222 | |
e525d34b NI |
223 | int dram_init(void) |
224 | { | |
8f284e66 MV |
225 | gd->ram_size = PHYS_SDRAM_1_SIZE; |
226 | #if (CONFIG_NR_DRAM_BANKS >= 2) | |
227 | gd->ram_size += PHYS_SDRAM_2_SIZE; | |
228 | #endif | |
229 | #if (CONFIG_NR_DRAM_BANKS >= 3) | |
230 | gd->ram_size += PHYS_SDRAM_3_SIZE; | |
231 | #endif | |
232 | #if (CONFIG_NR_DRAM_BANKS >= 4) | |
233 | gd->ram_size += PHYS_SDRAM_4_SIZE; | |
234 | #endif | |
235 | ||
236 | return 0; | |
237 | } | |
e525d34b | 238 | |
8f284e66 MV |
239 | int dram_init_banksize(void) |
240 | { | |
241 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; | |
242 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; | |
243 | #if (CONFIG_NR_DRAM_BANKS >= 2) | |
244 | gd->bd->bi_dram[1].start = PHYS_SDRAM_2; | |
245 | gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; | |
246 | #endif | |
247 | #if (CONFIG_NR_DRAM_BANKS >= 3) | |
248 | gd->bd->bi_dram[2].start = PHYS_SDRAM_3; | |
249 | gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; | |
250 | #endif | |
251 | #if (CONFIG_NR_DRAM_BANKS >= 4) | |
252 | gd->bd->bi_dram[3].start = PHYS_SDRAM_4; | |
253 | gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; | |
254 | #endif | |
e525d34b NI |
255 | return 0; |
256 | } | |
257 | ||
258 | const struct rmobile_sysinfo sysinfo = { | |
259 | CONFIG_RCAR_BOARD_STRING | |
260 | }; | |
261 | ||
262 | #define RST_BASE 0xE6160000 | |
263 | #define RST_CA57RESCNT (RST_BASE + 0x40) | |
264 | #define RST_CA53RESCNT (RST_BASE + 0x44) | |
265 | #define RST_RSTOUTCR (RST_BASE + 0x58) | |
266 | #define RST_CODE 0xA5A5000F | |
267 | ||
268 | void reset_cpu(ulong addr) | |
269 | { | |
fe2e8ff9 MV |
270 | #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) |
271 | i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80); | |
272 | #else | |
e525d34b NI |
273 | /* only CA57 ? */ |
274 | writel(RST_CODE, RST_CA57RESCNT); | |
fe2e8ff9 | 275 | #endif |
e525d34b | 276 | } |