[thirdparty/u-boot.git] / board / renesas / silk / silk_spl.c

// SPDX-License-Identifier: GPL-2.0
/*
 * board/renesas/silk/silk_spl.c
 *
 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
 */

#include <cpu_func.h>
#include <init.h>
#include <malloc.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>

#include <spl.h>

#define TMU0_MSTP125	BIT(25)
#define SCIF2_MSTP719	BIT(19)
#define QSPI_MSTP917	BIT(17)

#define SD1CKCR		0xE6150078
#define SD_97500KHZ	0x7

struct reg_config {
	u16	off;
	u32	val;
};

static void dbsc_wait(u16 reg)
{
	static const u32 dbsc3_0_base = DBSC3_0_BASE;

	while (!(readl(dbsc3_0_base + reg) & BIT(0)))
		;
}

static void spl_init_sys(void)
{
	u32 r0 = 0;

	writel(0xa5a5a500, 0xe6020004);
	writel(0xa5a5a500, 0xe6030004);

	asm volatile(
		/* ICIALLU - Invalidate I$ to PoU */
		"mcr	15, 0, %0, cr7, cr5, 0	\n"
		/* BPIALL - Invalidate branch predictors */
		"mcr	15, 0, %0, cr7, cr5, 6	\n"
		/* Set SCTLR[IZ] */
		"mrc	15, 0, %0, cr1, cr0, 0	\n"
		"orr	%0, #0x1800		\n"
		"mcr	15, 0, %0, cr1, cr0, 0	\n"
		"isb	sy			\n"
		:"=r"(r0));
}

static void spl_init_pfc(void)
{
	static const struct reg_config pfc_with_unlock[] = {
		{ 0x0090, 0x00018040 },
		{ 0x0094, 0x00000000 },
		{ 0x0098, 0x00000000 },
		{ 0x0020, 0x94000000 },
		{ 0x0024, 0x00000006 },
		{ 0x0028, 0x40000000 },
		{ 0x002c, 0x00000155 },
		{ 0x0030, 0x00000002 },
		{ 0x0034, 0x00000000 },
		{ 0x0038, 0x00000000 },
		{ 0x003c, 0x00000000 },
		{ 0x0040, 0x60000000 },
		{ 0x0044, 0x36dab6db },
		{ 0x0048, 0x926da012 },
		{ 0x004c, 0x0008c383 },
		{ 0x0050, 0x00000000 },
		{ 0x0054, 0x00000140 },
		{ 0x0004, 0xffffffff },
		{ 0x0008, 0x00ec3fff },
		{ 0x000c, 0x5bffffff },
		{ 0x0010, 0x01bfe1ff },
		{ 0x0014, 0x5bffffff },
		{ 0x0018, 0x0f4b200f },
		{ 0x001c, 0x03ffffff },
	};

	static const struct reg_config pfc_without_unlock[] = {
		{ 0x0100, 0x00000000 },
		{ 0x0104, 0x4203fdf0 },
		{ 0x0108, 0x00000000 },
		{ 0x010c, 0x159007ff },
		{ 0x0110, 0x80000000 },
		{ 0x0114, 0x00de481f },
		{ 0x0118, 0x00000000 },
	};

	static const struct reg_config pfc_with_unlock2[] = {
		{ 0x0060, 0xffffffff },
		{ 0x0064, 0xfffff000 },
		{ 0x0068, 0x55555500 },
		{ 0x006c, 0xffffff00 },
		{ 0x0070, 0x00000000 },
	};

	static const u32 pfc_base = 0xe6060000;

	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
		writel(~pfc_with_unlock[i].val, pfc_base);
		writel(pfc_with_unlock[i].val,
		       pfc_base | pfc_with_unlock[i].off);
	}

	for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
		writel(pfc_without_unlock[i].val,
		       pfc_base | pfc_without_unlock[i].off);

	for (i = 0; i < ARRAY_SIZE(pfc_with_unlock2); i++) {
		writel(~pfc_with_unlock2[i].val, pfc_base);
		writel(pfc_with_unlock2[i].val,
		       pfc_base | pfc_with_unlock2[i].off);
	}
}

static void spl_init_gpio(void)
{
	static const u16 gpio_offs[] = {
		0x1000, 0x2000, 0x3000, 0x4000
	};

	static const struct reg_config gpio_set[] = {
		{ 0x2000, 0x24000000 },
		{ 0x4000, 0xa4000000 },
		{ 0x5000, 0x0084c000 },
	};

	static const struct reg_config gpio_clr[] = {
		{ 0x1000, 0x01000000 },
		{ 0x2000, 0x24000000 },
		{ 0x3000, 0x00000000 },
		{ 0x4000, 0xa4000000 },
		{ 0x5000, 0x00044380 },
	};

	static const u32 gpio_base = 0xe6050000;

	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
		writel(0, gpio_base | 0x20 | gpio_offs[i]);
	writel(BIT(23), gpio_base | 0x5020);

	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
		writel(0, gpio_base | 0x00 | gpio_offs[i]);
	writel(BIT(23), gpio_base | 0x5000);

	for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
		writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);

	for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
		writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
}

static void spl_init_lbsc(void)
{
	static const struct reg_config lbsc_config[] = {
		{ 0x00, 0x00000020 },
		{ 0x08, 0x00002020 },
		{ 0x30, 0x2a103320 },
		{ 0x38, 0xff70ff70 },
	};

	static const u16 lbsc_offs[] = {
		0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8
	};

	static const u32 lbsc_base = 0xfec00200;

	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
		writel(lbsc_config[i].val,
		       lbsc_base | lbsc_config[i].off);
		writel(lbsc_config[i].val,
		       lbsc_base | (lbsc_config[i].off + 4));
	}

	for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
		writel(0, lbsc_base | lbsc_offs[i]);
}

static void spl_init_dbsc(void)
{
	static const struct reg_config dbsc_config1[] = {
		{ 0x0018, 0x21000000 },
		{ 0x0018, 0x11000000 },
		{ 0x0018, 0x10000000 },
		{ 0x0280, 0x0000a55a },
		{ 0x0290, 0x00000001 },
		{ 0x02a0, 0x80000000 },
		{ 0x0290, 0x00000004 },
	};

	static const struct reg_config dbsc_config2[] = {
		{ 0x0290, 0x00000006 },
		{ 0x02a0, 0x0005c000 },
	};

	static const struct reg_config dbsc_config3r2[] = {
		{ 0x0290, 0x0000000f },
		{ 0x02a0, 0x00181224 },
	};

	static const struct reg_config dbsc_config4[] = {
		{ 0x0290, 0x00000010 },
		{ 0x02a0, 0xf004649b },
		{ 0x0290, 0x00000061 },
		{ 0x02a0, 0x0000006d },
		{ 0x0290, 0x00000001 },
		{ 0x02a0, 0x00000073 },
		{ 0x0020, 0x00000007 },
		{ 0x0024, 0x0f030a02 },
		{ 0x0030, 0x00000001 },
		{ 0x00b0, 0x00000000 },
		{ 0x0040, 0x00000009 },
		{ 0x0044, 0x00000007 },
		{ 0x0048, 0x00000000 },
		{ 0x0050, 0x00000009 },
		{ 0x0054, 0x000a0009 },
		{ 0x0058, 0x00000021 },
		{ 0x005c, 0x00000018 },
		{ 0x0060, 0x00000005 },
		{ 0x0064, 0x00000020 },
		{ 0x0068, 0x00000007 },
		{ 0x006c, 0x0000000a },
		{ 0x0070, 0x00000009 },
		{ 0x0074, 0x00000010 },
		{ 0x0078, 0x000000ae },
		{ 0x007c, 0x00140005 },
		{ 0x0080, 0x00050004 },
		{ 0x0084, 0x50213005 },
		{ 0x0088, 0x000c0000 },
		{ 0x008c, 0x00000200 },
		{ 0x0090, 0x00000040 },
		{ 0x0100, 0x00000001 },
		{ 0x00c0, 0x00020001 },
		{ 0x00c8, 0x20042004 },
		{ 0x0380, 0x00020003 },
		{ 0x0390, 0x0000001f },
	};

	static const struct reg_config dbsc_config5[] = {
		{ 0x0244, 0x00000011 },
		{ 0x0290, 0x00000003 },
		{ 0x02a0, 0x0300c4e1 },
		{ 0x0290, 0x00000023 },
		{ 0x02a0, 0x00fcb6d0 },
		{ 0x0290, 0x00000011 },
		{ 0x02a0, 0x1000040b },
		{ 0x0290, 0x00000012 },
		{ 0x02a0, 0x85589955 },
		{ 0x0290, 0x00000013 },
		{ 0x02a0, 0x1a852400 },
		{ 0x0290, 0x00000014 },
		{ 0x02a0, 0x300210b4 },
		{ 0x0290, 0x00000015 },
		{ 0x02a0, 0x00000b50 },
		{ 0x0290, 0x00000016 },
		{ 0x02a0, 0x00000006 },
		{ 0x0290, 0x00000017 },
		{ 0x02a0, 0x00000010 },
		{ 0x0290, 0x0000001a },
		{ 0x02a0, 0x910035c7 },
		{ 0x0290, 0x00000004 },
	};

	static const struct reg_config dbsc_config6[] = {
		{ 0x0290, 0x00000001 },
		{ 0x02a0, 0x00000181 },
		{ 0x0018, 0x11000000 },
		{ 0x0290, 0x00000004 },
	};

	static const struct reg_config dbsc_config7[] = {
		{ 0x0290, 0x00000001 },
		{ 0x02a0, 0x0000fe01 },
		{ 0x0304, 0x00000000 },
		{ 0x00f4, 0x01004c20 },
		{ 0x00f8, 0x012c00be },
		{ 0x00e0, 0x00000140 },
		{ 0x00e4, 0x00081450 },
		{ 0x00e8, 0x00010000 },
		{ 0x0290, 0x00000004 },
	};

	static const struct reg_config dbsc_config8[] = {
		{ 0x0014, 0x00000001 },
		{ 0x0290, 0x00000010 },
		{ 0x02a0, 0xf00464db },
		{ 0x0010, 0x00000001 },
		{ 0x0280, 0x00000000 },
	};

	static const u32 dbsc3_0_base = DBSC3_0_BASE;
	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
		writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);

	dbsc_wait(0x2a0);

	for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
		writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);

	for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) {
		writel(dbsc_config3r2[i].val,
			dbsc3_0_base | dbsc_config3r2[i].off);
	}

	for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
		writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);

	dbsc_wait(0x240);

	for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
		writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);

	dbsc_wait(0x2a0);

	for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
		writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);

	dbsc_wait(0x2a0);

	for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
		writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);

	dbsc_wait(0x2a0);

	for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
		writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);

}

static void spl_init_qspi(void)
{
	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);

	static const u32 qspi_base = 0xe6b10000;

	writeb(0x08, qspi_base + 0x00);
	writeb(0x00, qspi_base + 0x01);
	writeb(0x06, qspi_base + 0x02);
	writeb(0x01, qspi_base + 0x0a);
	writeb(0x00, qspi_base + 0x0b);
	writeb(0x00, qspi_base + 0x0c);
	writeb(0x00, qspi_base + 0x0d);
	writeb(0x00, qspi_base + 0x0e);

	writew(0xe080, qspi_base + 0x10);

	writeb(0xc0, qspi_base + 0x18);
	writeb(0x00, qspi_base + 0x18);
	writeb(0x00, qspi_base + 0x08);
	writeb(0x48, qspi_base + 0x00);
}

void board_init_f(ulong dummy)
{
	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);

	/* Set SD1 to the 97.5MHz */
	writel(SD_97500KHZ, SD1CKCR);

	spl_init_sys();
	spl_init_pfc();
	spl_init_gpio();
	spl_init_lbsc();
	spl_init_dbsc();
	spl_init_qspi();
}

void spl_board_init(void)
{
	/* UART clocks enabled and gd valid - init serial console */
	preloader_console_init();
}

void board_boot_order(u32 *spl_boot_list)
{
	const u32 jtag_magic = 0x1337c0de;
	const u32 load_magic = 0xb33fc0de;

	/*
	 * If JTAG probe sets special word at 0xe6300020, then it must
	 * put U-Boot into RAM and SPL will start it from RAM.
	 */
	if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
		printf("JTAG boot detected!\n");

		while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
			;

		spl_boot_list[0] = BOOT_DEVICE_RAM;
		spl_boot_list[1] = BOOT_DEVICE_NONE;

		return;
	}

	/* Boot from SPI NOR with YMODEM UART fallback. */
	spl_boot_list[0] = BOOT_DEVICE_SPI;
	spl_boot_list[1] = BOOT_DEVICE_UART;
	spl_boot_list[2] = BOOT_DEVICE_NONE;
}

void reset_cpu(void)
{
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0
f7aa3cd4 MV	2	/*
	3	* board/renesas/silk/silk_spl.c
	4	*
	5	* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
f7aa3cd4 MV	6	*/
f7aa3cd4 MV	7
9a3b4ceb	8	#include <cpu_func.h>
691d719d	9	#include <init.h>
f7aa3cd4 MV	10	#include <malloc.h>
	11	#include <dm/platform_data/serial_sh.h>
	12	#include <asm/processor.h>
	13	#include <asm/mach-types.h>
	14	#include <asm/io.h>
cd93d625	15	#include <linux/bitops.h>
f7aa3cd4 MV	16	#include <linux/errno.h>
	17	#include <asm/arch/sys_proto.h>
	18	#include <asm/gpio.h>
	19	#include <asm/arch/rmobile.h>
	20	#include <asm/arch/rcar-mstp.h>
	21
	22	#include <spl.h>
	23
	24	#define TMU0_MSTP125 BIT(25)
	25	#define SCIF2_MSTP719 BIT(19)
	26	#define QSPI_MSTP917 BIT(17)
	27
	28	#define SD1CKCR 0xE6150078
	29	#define SD_97500KHZ 0x7
	30
	31	struct reg_config {
	32	u16 off;
	33	u32 val;
	34	};
	35
	36	static void dbsc_wait(u16 reg)
	37	{
	38	static const u32 dbsc3_0_base = DBSC3_0_BASE;
	39
	40	while (!(readl(dbsc3_0_base + reg) & BIT(0)))
	41	;
	42	}
	43
	44	static void spl_init_sys(void)
	45	{
	46	u32 r0 = 0;
	47
	48	writel(0xa5a5a500, 0xe6020004);
	49	writel(0xa5a5a500, 0xe6030004);
	50
	51	asm volatile(
	52	/* ICIALLU - Invalidate I$ to PoU */
	53	"mcr 15, 0, %0, cr7, cr5, 0 \n"
	54	/* BPIALL - Invalidate branch predictors */
	55	"mcr 15, 0, %0, cr7, cr5, 6 \n"
	56	/* Set SCTLR[IZ] */
	57	"mrc 15, 0, %0, cr1, cr0, 0 \n"
	58	"orr %0, #0x1800 \n"
	59	"mcr 15, 0, %0, cr1, cr0, 0 \n"
	60	"isb sy \n"
	61	:"=r"(r0));
	62	}
	63
	64	static void spl_init_pfc(void)
	65	{
	66	static const struct reg_config pfc_with_unlock[] = {
	67	{ 0x0090, 0x00018040 },
	68	{ 0x0094, 0x00000000 },
	69	{ 0x0098, 0x00000000 },
	70	{ 0x0020, 0x94000000 },
	71	{ 0x0024, 0x00000006 },
	72	{ 0x0028, 0x40000000 },
	73	{ 0x002c, 0x00000155 },
	74	{ 0x0030, 0x00000002 },
	75	{ 0x0034, 0x00000000 },
	76	{ 0x0038, 0x00000000 },
	77	{ 0x003c, 0x00000000 },
	78	{ 0x0040, 0x60000000 },
	79	{ 0x0044, 0x36dab6db },
80	{ 0x0048, 0x926da012 },
81	{ 0x004c, 0x0008c383 },
82	{ 0x0050, 0x00000000 },
83	{ 0x0054, 0x00000140 },
84	{ 0x0004, 0xffffffff },
85	{ 0x0008, 0x00ec3fff },
86	{ 0x000c, 0x5bffffff },
87	{ 0x0010, 0x01bfe1ff },
88	{ 0x0014, 0x5bffffff },
89	{ 0x0018, 0x0f4b200f },
90	{ 0x001c, 0x03ffffff },
91	};
92
93	static const struct reg_config pfc_without_unlock[] = {
94	{ 0x0100, 0x00000000 },
95	{ 0x0104, 0x4203fdf0 },
96	{ 0x0108, 0x00000000 },
97	{ 0x010c, 0x159007ff },
98	{ 0x0110, 0x80000000 },
99	{ 0x0114, 0x00de481f },
100	{ 0x0118, 0x00000000 },
101	};
102
103	static const struct reg_config pfc_with_unlock2[] = {
104	{ 0x0060, 0xffffffff },
105	{ 0x0064, 0xfffff000 },
106	{ 0x0068, 0x55555500 },
107	{ 0x006c, 0xffffff00 },
108	{ 0x0070, 0x00000000 },
109	};
110
111	static const u32 pfc_base = 0xe6060000;
112
113	unsigned int i;
114
115	for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
116	writel(~pfc_with_unlock[i].val, pfc_base);
117	writel(pfc_with_unlock[i].val,
118	pfc_base \| pfc_with_unlock[i].off);
119	}
120
121	for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
122	writel(pfc_without_unlock[i].val,
123	pfc_base \| pfc_without_unlock[i].off);
124
125	for (i = 0; i < ARRAY_SIZE(pfc_with_unlock2); i++) {
126	writel(~pfc_with_unlock2[i].val, pfc_base);
127	writel(pfc_with_unlock2[i].val,
128	pfc_base \| pfc_with_unlock2[i].off);
129	}
130	}
131
132	static void spl_init_gpio(void)
133	{
134	static const u16 gpio_offs[] = {
135	0x1000, 0x2000, 0x3000, 0x4000
136	};
137
138	static const struct reg_config gpio_set[] = {
139	{ 0x2000, 0x24000000 },
140	{ 0x4000, 0xa4000000 },
141	{ 0x5000, 0x0084c000 },
142	};
143
144	static const struct reg_config gpio_clr[] = {
145	{ 0x1000, 0x01000000 },
146	{ 0x2000, 0x24000000 },
147	{ 0x3000, 0x00000000 },
148	{ 0x4000, 0xa4000000 },
149	{ 0x5000, 0x00044380 },
150	};
151
152	static const u32 gpio_base = 0xe6050000;
153
154	unsigned int i;
155
156	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
157	writel(0, gpio_base \| 0x20 \| gpio_offs[i]);
158	writel(BIT(23), gpio_base \| 0x5020);
159
160	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
161	writel(0, gpio_base \| 0x00 \| gpio_offs[i]);
162	writel(BIT(23), gpio_base \| 0x5000);
163
164	for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
165	writel(gpio_set[i].val, gpio_base \| 0x08 \| gpio_set[i].off);
166
167	for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
168	writel(gpio_clr[i].val, gpio_base \| 0x04 \| gpio_clr[i].off);
169	}
170
171	static void spl_init_lbsc(void)
172	{
173	static const struct reg_config lbsc_config[] = {
174	{ 0x00, 0x00000020 },
175	{ 0x08, 0x00002020 },
176	{ 0x30, 0x2a103320 },
177	{ 0x38, 0xff70ff70 },
178	};
179
180	static const u16 lbsc_offs[] = {
181	0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8
182	};
183
184	static const u32 lbsc_base = 0xfec00200;
185
186	unsigned int i;
187
188	for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
189	writel(lbsc_config[i].val,
190	lbsc_base \| lbsc_config[i].off);
191	writel(lbsc_config[i].val,
192	lbsc_base \| (lbsc_config[i].off + 4));
193	}
194
195	for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
196	writel(0, lbsc_base \| lbsc_offs[i]);
197	}
198
199	static void spl_init_dbsc(void)
200	{
201	static const struct reg_config dbsc_config1[] = {
202	{ 0x0018, 0x21000000 },
203	{ 0x0018, 0x11000000 },
204	{ 0x0018, 0x10000000 },
205	{ 0x0280, 0x0000a55a },
206	{ 0x0290, 0x00000001 },
207	{ 0x02a0, 0x80000000 },
208	{ 0x0290, 0x00000004 },
209	};
210
211	static const struct reg_config dbsc_config2[] = {
212	{ 0x0290, 0x00000006 },
213	{ 0x02a0, 0x0005c000 },
214	};
215
216	static const struct reg_config dbsc_config3r2[] = {
217	{ 0x0290, 0x0000000f },
218	{ 0x02a0, 0x00181224 },
219	};
220
221	static const struct reg_config dbsc_config4[] = {
222	{ 0x0290, 0x00000010 },
223	{ 0x02a0, 0xf004649b },
224	{ 0x0290, 0x00000061 },
225	{ 0x02a0, 0x0000006d },
226	{ 0x0290, 0x00000001 },
227	{ 0x02a0, 0x00000073 },
228	{ 0x0020, 0x00000007 },
229	{ 0x0024, 0x0f030a02 },
230	{ 0x0030, 0x00000001 },
231	{ 0x00b0, 0x00000000 },
232	{ 0x0040, 0x00000009 },
233	{ 0x0044, 0x00000007 },
234	{ 0x0048, 0x00000000 },
235	{ 0x0050, 0x00000009 },
236	{ 0x0054, 0x000a0009 },
237	{ 0x0058, 0x00000021 },
238	{ 0x005c, 0x00000018 },
239	{ 0x0060, 0x00000005 },
240	{ 0x0064, 0x00000020 },
241	{ 0x0068, 0x00000007 },
242	{ 0x006c, 0x0000000a },
243	{ 0x0070, 0x00000009 },
244	{ 0x0074, 0x00000010 },
245	{ 0x0078, 0x000000ae },
246	{ 0x007c, 0x00140005 },
247	{ 0x0080, 0x00050004 },
248	{ 0x0084, 0x50213005 },
249	{ 0x0088, 0x000c0000 },
250	{ 0x008c, 0x00000200 },
251	{ 0x0090, 0x00000040 },
252	{ 0x0100, 0x00000001 },
253	{ 0x00c0, 0x00020001 },
254	{ 0x00c8, 0x20042004 },
255	{ 0x0380, 0x00020003 },
256	{ 0x0390, 0x0000001f },
257	};
258
259	static const struct reg_config dbsc_config5[] = {
260	{ 0x0244, 0x00000011 },
261	{ 0x0290, 0x00000003 },
262	{ 0x02a0, 0x0300c4e1 },
263	{ 0x0290, 0x00000023 },
264	{ 0x02a0, 0x00fcb6d0 },
265	{ 0x0290, 0x00000011 },
266	{ 0x02a0, 0x1000040b },
267	{ 0x0290, 0x00000012 },
268	{ 0x02a0, 0x85589955 },
269	{ 0x0290, 0x00000013 },
270	{ 0x02a0, 0x1a852400 },
271	{ 0x0290, 0x00000014 },
272	{ 0x02a0, 0x300210b4 },
273	{ 0x0290, 0x00000015 },
274	{ 0x02a0, 0x00000b50 },
275	{ 0x0290, 0x00000016 },
276	{ 0x02a0, 0x00000006 },
277	{ 0x0290, 0x00000017 },
278	{ 0x02a0, 0x00000010 },
279	{ 0x0290, 0x0000001a },
280	{ 0x02a0, 0x910035c7 },
281	{ 0x0290, 0x00000004 },
282	};
283
284	static const struct reg_config dbsc_config6[] = {
285	{ 0x0290, 0x00000001 },
286	{ 0x02a0, 0x00000181 },
287	{ 0x0018, 0x11000000 },
288	{ 0x0290, 0x00000004 },
289	};
290
291	static const struct reg_config dbsc_config7[] = {
292	{ 0x0290, 0x00000001 },
293	{ 0x02a0, 0x0000fe01 },
294	{ 0x0304, 0x00000000 },
295	{ 0x00f4, 0x01004c20 },
296	{ 0x00f8, 0x012c00be },
297	{ 0x00e0, 0x00000140 },
298	{ 0x00e4, 0x00081450 },
299	{ 0x00e8, 0x00010000 },
300	{ 0x0290, 0x00000004 },
301	};
302
303	static const struct reg_config dbsc_config8[] = {
304	{ 0x0014, 0x00000001 },
305	{ 0x0290, 0x00000010 },
306	{ 0x02a0, 0xf00464db },
307	{ 0x0010, 0x00000001 },
308	{ 0x0280, 0x00000000 },
309	};
310
311	static const u32 dbsc3_0_base = DBSC3_0_BASE;
312	unsigned int i;
313
314	for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
315	writel(dbsc_config1[i].val, dbsc3_0_base \| dbsc_config1[i].off);
316
317	dbsc_wait(0x2a0);
318
319	for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
320	writel(dbsc_config2[i].val, dbsc3_0_base \| dbsc_config2[i].off);
321
322	for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) {
323	writel(dbsc_config3r2[i].val,
324	dbsc3_0_base \| dbsc_config3r2[i].off);
325	}
326
327	for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
328	writel(dbsc_config4[i].val, dbsc3_0_base \| dbsc_config4[i].off);
329
330	dbsc_wait(0x240);
331
332	for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
333	writel(dbsc_config5[i].val, dbsc3_0_base \| dbsc_config5[i].off);
334
335	dbsc_wait(0x2a0);
336
337	for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
338	writel(dbsc_config6[i].val, dbsc3_0_base \| dbsc_config6[i].off);
339
340	dbsc_wait(0x2a0);
341
342	for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
343	writel(dbsc_config7[i].val, dbsc3_0_base \| dbsc_config7[i].off);
344
345	dbsc_wait(0x2a0);
346
347	for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
348	writel(dbsc_config8[i].val, dbsc3_0_base \| dbsc_config8[i].off);
349
350	}
351
352	static void spl_init_qspi(void)
353	{
354	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
355
356	static const u32 qspi_base = 0xe6b10000;
357
358	writeb(0x08, qspi_base + 0x00);
359	writeb(0x00, qspi_base + 0x01);
360	writeb(0x06, qspi_base + 0x02);
361	writeb(0x01, qspi_base + 0x0a);
362	writeb(0x00, qspi_base + 0x0b);
363	writeb(0x00, qspi_base + 0x0c);
364	writeb(0x00, qspi_base + 0x0d);
365	writeb(0x00, qspi_base + 0x0e);
366
367	writew(0xe080, qspi_base + 0x10);
368
369	writeb(0xc0, qspi_base + 0x18);
370	writeb(0x00, qspi_base + 0x18);
371	writeb(0x00, qspi_base + 0x08);
372	writeb(0x48, qspi_base + 0x00);
373	}
374
375	void board_init_f(ulong dummy)
376	{
377	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
378	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
379
380	/* Set SD1 to the 97.5MHz */
381	writel(SD_97500KHZ, SD1CKCR);
382
383	spl_init_sys();
384	spl_init_pfc();
385	spl_init_gpio();
386	spl_init_lbsc();
387	spl_init_dbsc();
388	spl_init_qspi();
389	}
390
391	void spl_board_init(void)
392	{
393	/* UART clocks enabled and gd valid - init serial console */
394	preloader_console_init();
395	}
396
397	void board_boot_order(u32 *spl_boot_list)
398	{
399	const u32 jtag_magic = 0x1337c0de;
400	const u32 load_magic = 0xb33fc0de;
401
402	/*
403	* If JTAG probe sets special word at 0xe6300020, then it must
404	* put U-Boot into RAM and SPL will start it from RAM.
405	*/
406	if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
407	printf("JTAG boot detected!\n");
408
409	while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
410	;
411
412	spl_boot_list[0] = BOOT_DEVICE_RAM;
413	spl_boot_list[1] = BOOT_DEVICE_NONE;
414
415	return;
416	}
417
418	/* Boot from SPI NOR with YMODEM UART fallback. */
419	spl_boot_list[0] = BOOT_DEVICE_SPI;
420	spl_boot_list[1] = BOOT_DEVICE_UART;
421	spl_boot_list[2] = BOOT_DEVICE_NONE;
422	}
423
35b65dd8	424	void reset_cpu(void)
f7aa3cd4 MV	425	{
f7aa3cd4 MV	426	}