[thirdparty/u-boot.git] / board / renesas / stout / stout_spl.c

// SPDX-License-Identifier: GPL-2.0
/*
 * board/renesas/stout/stout_spl.c
 *
 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
 */

#include <cpu_func.h>
#include <init.h>
#include <malloc.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/renesas.h>
#include <asm/arch/rcar-mstp.h>

#include <spl.h>

#define TMU0_MSTP125	BIT(25)
#define SCIFA0_MSTP204	BIT(4)
#define QSPI_MSTP917	BIT(17)

#define SD2CKCR		0xE615026C
#define SD_97500KHZ	0x7

struct reg_config {
	u16	off;
	u32	val;
};

static void dbsc_wait(u16 reg)
{
	static const u32 dbsc3_0_base = DBSC3_0_BASE;
	static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;

	while (!(readl(dbsc3_0_base + reg) & BIT(0)))
		;

	while (!(readl(dbsc3_1_base + reg) & BIT(0)))
		;
}

static void spl_init_sys(void)
{
	u32 r0 = 0;

	writel(0xa5a5a500, 0xe6020004);
	writel(0xa5a5a500, 0xe6030004);

	asm volatile(
		/* ICIALLU - Invalidate I$ to PoU */
		"mcr	15, 0, %0, cr7, cr5, 0	\n"
		/* BPIALL - Invalidate branch predictors */
		"mcr	15, 0, %0, cr7, cr5, 6	\n"
		/* Set SCTLR[IZ] */
		"mrc	15, 0, %0, cr1, cr0, 0	\n"
		"orr	%0, #0x1800		\n"
		"mcr	15, 0, %0, cr1, cr0, 0	\n"
		"isb	sy			\n"
		:"=r"(r0));
}

static void spl_init_pfc(void)
{
	static const struct reg_config pfc_with_unlock[] = {
		{ 0x0090, 0x00140300 },
		{ 0x0094, 0x09500000 },
		{ 0x0098, 0xc0000084 },
		{ 0x0020, 0x01a33492 },
		{ 0x0024, 0x10000000 },
		{ 0x0028, 0x08449252 },
		{ 0x002c, 0x2925b322 },
		{ 0x0030, 0x0c311249 },
		{ 0x0034, 0x10124000 },
		{ 0x0038, 0x00001295 },
		{ 0x003c, 0x50890000 },
		{ 0x0040, 0x0eaa56aa },
		{ 0x0044, 0x55550000 },
		{ 0x0048, 0x00000005 },
		{ 0x004c, 0x54800000 },
		{ 0x0050, 0x3736db55 },
		{ 0x0054, 0x29148da3 },
		{ 0x0058, 0x48c446e1 },
		{ 0x005c, 0x2a3a54dc },
		{ 0x0160, 0x00000023 },
		{ 0x0004, 0xfca0ffff },
		{ 0x0008, 0x3fbffbf0 },
		{ 0x000c, 0x3ffdffff },
		{ 0x0010, 0x00ffffff },
		{ 0x0014, 0xfc3ffff3 },
		{ 0x0018, 0xe4fdfff7 },
	};

	static const struct reg_config pfc_without_unlock[] = {
		{ 0x0104, 0xffffbfff },
		{ 0x0108, 0xb1ffffe1 },
		{ 0x010c, 0xffffffff },
		{ 0x0110, 0xffffffff },
		{ 0x0114, 0xe047beab },
		{ 0x0118, 0x00000203 },
	};

	static const u32 pfc_base = 0xe6060000;

	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
		writel(~pfc_with_unlock[i].val, pfc_base);
		writel(pfc_with_unlock[i].val,
		       pfc_base | pfc_with_unlock[i].off);
	}

	for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
		writel(pfc_without_unlock[i].val,
		       pfc_base | pfc_without_unlock[i].off);
}

static void spl_init_gpio(void)
{
	static const u16 gpio_offs[] = {
		0x1000, 0x3000, 0x4000, 0x5000
	};

	static const struct reg_config gpio_set[] = {
		{ 0x4000, 0x00c00000 },
		{ 0x5000, 0x63020000 },
	};

	static const struct reg_config gpio_clr[] = {
		{ 0x1000, 0x00000000 },
		{ 0x3000, 0x00000000 },
		{ 0x4000, 0x00c00000 },
		{ 0x5000, 0xe3020000 },
	};

	static const u32 gpio_base = 0xe6050000;

	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
		writel(0, gpio_base | 0x20 | gpio_offs[i]);

	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
		writel(0, gpio_base | 0x00 | gpio_offs[i]);

	for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
		writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);

	for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
		writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
}

static void spl_init_lbsc(void)
{
	static const struct reg_config lbsc_config[] = {
		{ 0x00, 0x00000020 },
		{ 0x08, 0x00002020 },
		{ 0x30, 0x02150326 },
		{ 0x38, 0x077f077f },
	};

	static const u16 lbsc_offs[] = {
		0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
	};

	static const u32 lbsc_base = 0xfec00200;

	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
		writel(lbsc_config[i].val,
		       lbsc_base | lbsc_config[i].off);
		writel(lbsc_config[i].val,
		       lbsc_base | (lbsc_config[i].off + 4));
	}

	for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
		writel(0, lbsc_base | lbsc_offs[i]);
}

static void spl_init_dbsc(void)
{
	static const struct reg_config dbsc_config1[] = {
		{ 0x0280, 0x0000a55a },
		{ 0x0018, 0x21000000 },
		{ 0x0018, 0x11000000 },
		{ 0x0018, 0x10000000 },
		{ 0x0290, 0x00000001 },
		{ 0x02a0, 0x80000000 },
		{ 0x0290, 0x00000004 },
	};

	static const struct reg_config dbsc_config2[] = {
		{ 0x0290, 0x00000006 },
		{ 0x02a0, 0x0001c000 },
	};

	static const struct reg_config dbsc_config3r0d0[] = {
		{ 0x0290, 0x0000000f },
		{ 0x02a0, 0x00181885 },
		{ 0x0290, 0x00000070 },
		{ 0x02a0, 0x7c000887 },
		{ 0x0290, 0x00000080 },
		{ 0x02a0, 0x7c000887 },
		{ 0x0290, 0x00000090 },
		{ 0x02a0, 0x7c000887 },
		{ 0x0290, 0x000000a0 },
		{ 0x02a0, 0x7c000887 },
		{ 0x0290, 0x000000b0 },
		{ 0x02a0, 0x7c000880 },
		{ 0x0290, 0x000000c0 },
		{ 0x02a0, 0x7c000880 },
		{ 0x0290, 0x000000d0 },
		{ 0x02a0, 0x7c000880 },
		{ 0x0290, 0x000000e0 },
		{ 0x02a0, 0x7c000880 },
	};

	static const struct reg_config dbsc_config3r0d1[] = {
		{ 0x0290, 0x0000000f },
		{ 0x02a0, 0x00181885 },
		{ 0x0290, 0x00000070 },
		{ 0x02a0, 0x7c000887 },
		{ 0x0290, 0x00000080 },
		{ 0x02a0, 0x7c000887 },
		{ 0x0290, 0x00000090 },
		{ 0x02a0, 0x7c000887 },
		{ 0x0290, 0x000000a0 },
		{ 0x02a0, 0x7c000887 },
	};

	static const struct reg_config dbsc_config3r2[] = {
		{ 0x0290, 0x0000000f },
		{ 0x02a0, 0x00181224 },
	};

	static const struct reg_config dbsc_config4[] = {
		{ 0x0290, 0x00000010 },
		{ 0x02a0, 0xf004649b },
		{ 0x0290, 0x00000061 },
		{ 0x02a0, 0x0000006d },
		{ 0x0290, 0x00000001 },
		{ 0x02a0, 0x00000073 },
		{ 0x0020, 0x00000007 },
		{ 0x0024, 0x0f030a02 },
		{ 0x0030, 0x00000001 },
		{ 0x00b0, 0x00000000 },
		{ 0x0040, 0x0000000b },
		{ 0x0044, 0x00000008 },
		{ 0x0048, 0x00000000 },
		{ 0x0050, 0x0000000b },
		{ 0x0054, 0x000c000b },
		{ 0x0058, 0x00000027 },
		{ 0x005c, 0x0000001c },
		{ 0x0060, 0x00000006 },
		{ 0x0064, 0x00000020 },
		{ 0x0068, 0x00000008 },
		{ 0x006c, 0x0000000c },
		{ 0x0070, 0x00000009 },
		{ 0x0074, 0x00000012 },
		{ 0x0078, 0x000000d0 },
		{ 0x007c, 0x00140005 },
		{ 0x0080, 0x00050004 },
		{ 0x0084, 0x70233005 },
		{ 0x0088, 0x000c0000 },
		{ 0x008c, 0x00000200 },
		{ 0x0090, 0x00000040 },
		{ 0x0100, 0x00000001 },
		{ 0x00c0, 0x00020001 },
		{ 0x00c8, 0x20042004 },
		{ 0x0380, 0x00020002 },
		{ 0x0390, 0x0000001f },
	};

	static const struct reg_config dbsc_config5[] = {
		{ 0x0244, 0x00000011 },
		{ 0x0290, 0x00000003 },
		{ 0x02a0, 0x0300c4e1 },
		{ 0x0290, 0x00000023 },
		{ 0x02a0, 0x00fcdb60 },
		{ 0x0290, 0x00000011 },
		{ 0x02a0, 0x1000040b },
		{ 0x0290, 0x00000012 },
		{ 0x02a0, 0x9d9cbb66 },
		{ 0x0290, 0x00000013 },
		{ 0x02a0, 0x1a868400 },
		{ 0x0290, 0x00000014 },
		{ 0x02a0, 0x300214d8 },
		{ 0x0290, 0x00000015 },
		{ 0x02a0, 0x00000d70 },
		{ 0x0290, 0x00000016 },
		{ 0x02a0, 0x00000006 },
		{ 0x0290, 0x00000017 },
		{ 0x02a0, 0x00000018 },
		{ 0x0290, 0x0000001a },
		{ 0x02a0, 0x910035c7 },
		{ 0x0290, 0x00000004 },
	};

	static const struct reg_config dbsc_config6[] = {
		{ 0x0290, 0x00000001 },
		{ 0x02a0, 0x00000181 },
		{ 0x0018, 0x11000000 },
		{ 0x0290, 0x00000004 },
	};

	static const struct reg_config dbsc_config7[] = {
		{ 0x0290, 0x00000001 },
		{ 0x02a0, 0x0000fe01 },
		{ 0x0304, 0x00000000 },
		{ 0x00f4, 0x01004c20 },
		{ 0x00f8, 0x014000aa },
		{ 0x00e0, 0x00000140 },
		{ 0x00e4, 0x00081860 },
		{ 0x00e8, 0x00010000 },
		{ 0x0290, 0x00000004 },
	};

	static const struct reg_config dbsc_config8[] = {
		{ 0x0014, 0x00000001 },
		{ 0x0010, 0x00000001 },
		{ 0x0280, 0x00000000 },
	};

	static const u32 dbsc3_0_base = DBSC3_0_BASE;
	static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
	static const u32 prr_base = 0xff000044;
	const u16 prr_rev = readl(prr_base) & 0x7fff;
	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) {
		writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
		writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off);
	}

	dbsc_wait(0x2a0);

	for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) {
		writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
		writel(dbsc_config2[i].val, dbsc3_1_base | dbsc_config2[i].off);
	}

	if (prr_rev == 0x4500) {
		for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d0); i++) {
			writel(dbsc_config3r0d0[i].val,
				dbsc3_0_base | dbsc_config3r0d0[i].off);
		}
		for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d1); i++) {
			writel(dbsc_config3r0d1[i].val,
				dbsc3_1_base | dbsc_config3r0d1[i].off);
		}
	} else if (prr_rev != 0x4510) {
		for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) {
			writel(dbsc_config3r2[i].val,
				dbsc3_0_base | dbsc_config3r2[i].off);
			writel(dbsc_config3r2[i].val,
				dbsc3_1_base | dbsc_config3r2[i].off);
		}
	}

	for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) {
		writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
		writel(dbsc_config4[i].val, dbsc3_1_base | dbsc_config4[i].off);
	}

	dbsc_wait(0x240);

	for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) {
		writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
		writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off);
	}

	dbsc_wait(0x2a0);

	for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) {
		writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
		writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off);
	}

	dbsc_wait(0x2a0);

	for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) {
		writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
		writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off);
	}

	dbsc_wait(0x2a0);

	for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) {
		writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
		writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off);
	}

}

static void spl_init_qspi(void)
{
	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);

	static const u32 qspi_base = 0xe6b10000;

	writeb(0x08, qspi_base + 0x00);
	writeb(0x00, qspi_base + 0x01);
	writeb(0x06, qspi_base + 0x02);
	writeb(0x01, qspi_base + 0x0a);
	writeb(0x00, qspi_base + 0x0b);
	writeb(0x00, qspi_base + 0x0c);
	writeb(0x00, qspi_base + 0x0d);
	writeb(0x00, qspi_base + 0x0e);

	writew(0xe080, qspi_base + 0x10);

	writeb(0xc0, qspi_base + 0x18);
	writeb(0x00, qspi_base + 0x18);
	writeb(0x00, qspi_base + 0x08);
	writeb(0x48, qspi_base + 0x00);
}

void board_init_f(ulong dummy)
{
	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
	mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIFA0_MSTP204);

	/*
	 * SD0 clock is set to 97.5MHz by default.
	 * Set SD2 to the 97.5MHz as well.
	 */
	writel(SD_97500KHZ, SD2CKCR);

	spl_init_sys();
	spl_init_pfc();
	spl_init_gpio();
	spl_init_lbsc();
	spl_init_dbsc();
	spl_init_qspi();
}

void spl_board_init(void)
{
	/* UART clocks enabled and gd valid - init serial console */
	preloader_console_init();
}

void board_boot_order(u32 *spl_boot_list)
{
	const u32 jtag_magic = 0x1337c0de;
	const u32 load_magic = 0xb33fc0de;

	/*
	 * If JTAG probe sets special word at 0xe6300020, then it must
	 * put U-Boot into RAM and SPL will start it from RAM.
	 */
	if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
		printf("JTAG boot detected!\n");

		while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
			;

		spl_boot_list[0] = BOOT_DEVICE_RAM;
		spl_boot_list[1] = BOOT_DEVICE_NONE;

		return;
	}

	/* Boot from SPI NOR with YMODEM UART fallback. */
	spl_boot_list[0] = BOOT_DEVICE_SPI;
	spl_boot_list[1] = BOOT_DEVICE_UART;
	spl_boot_list[2] = BOOT_DEVICE_NONE;
}

void reset_cpu(void)
{
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0
ec7113fb MV	2	/*
	3	* board/renesas/stout/stout_spl.c
	4	*
	5	* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
ec7113fb MV	6	*/
ec7113fb MV	7
9a3b4ceb	8	#include <cpu_func.h>
691d719d	9	#include <init.h>
ec7113fb MV	10	#include <malloc.h>
	11	#include <dm/platform_data/serial_sh.h>
	12	#include <asm/processor.h>
	13	#include <asm/mach-types.h>
	14	#include <asm/io.h>
cd93d625	15	#include <linux/bitops.h>
ec7113fb MV	16	#include <linux/errno.h>
	17	#include <asm/arch/sys_proto.h>
	18	#include <asm/gpio.h>
65abdd19	19	#include <asm/arch/renesas.h>
ec7113fb MV	20	#include <asm/arch/rcar-mstp.h>
	21
	22	#include <spl.h>
	23
	24	#define TMU0_MSTP125 BIT(25)
	25	#define SCIFA0_MSTP204 BIT(4)
	26	#define QSPI_MSTP917 BIT(17)
	27
	28	#define SD2CKCR 0xE615026C
	29	#define SD_97500KHZ 0x7
	30
ec7113fb MV	31	struct reg_config {
	32	u16 off;
	33	u32 val;
	34	};
	35
	36	static void dbsc_wait(u16 reg)
	37	{
	38	static const u32 dbsc3_0_base = DBSC3_0_BASE;
	39	static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
	40
	41	while (!(readl(dbsc3_0_base + reg) & BIT(0)))
	42	;
	43
	44	while (!(readl(dbsc3_1_base + reg) & BIT(0)))
	45	;
	46	}
	47
0e592d07	48	static void spl_init_sys(void)
ec7113fb MV	49	{
	50	u32 r0 = 0;
	51
	52	writel(0xa5a5a500, 0xe6020004);
	53	writel(0xa5a5a500, 0xe6030004);
	54
	55	asm volatile(
	56	/* ICIALLU - Invalidate I$ to PoU */
	57	"mcr 15, 0, %0, cr7, cr5, 0 \n"
	58	/* BPIALL - Invalidate branch predictors */
	59	"mcr 15, 0, %0, cr7, cr5, 6 \n"
	60	/* Set SCTLR[IZ] */
	61	"mrc 15, 0, %0, cr1, cr0, 0 \n"
	62	"orr %0, #0x1800 \n"
	63	"mcr 15, 0, %0, cr1, cr0, 0 \n"
	64	"isb sy \n"
	65	:"=r"(r0));
	66	}
	67
0e592d07	68	static void spl_init_pfc(void)
ec7113fb MV	69	{
	70	static const struct reg_config pfc_with_unlock[] = {
	71	{ 0x0090, 0x00140300 },
	72	{ 0x0094, 0x09500000 },
	73	{ 0x0098, 0xc0000084 },
	74	{ 0x0020, 0x01a33492 },
	75	{ 0x0024, 0x10000000 },
	76	{ 0x0028, 0x08449252 },
	77	{ 0x002c, 0x2925b322 },
	78	{ 0x0030, 0x0c311249 },
	79	{ 0x0034, 0x10124000 },
	80	{ 0x0038, 0x00001295 },
	81	{ 0x003c, 0x50890000 },
	82	{ 0x0040, 0x0eaa56aa },
	83	{ 0x0044, 0x55550000 },
	84	{ 0x0048, 0x00000005 },
	85	{ 0x004c, 0x54800000 },
	86	{ 0x0050, 0x3736db55 },
	87	{ 0x0054, 0x29148da3 },
	88	{ 0x0058, 0x48c446e1 },
	89	{ 0x005c, 0x2a3a54dc },
	90	{ 0x0160, 0x00000023 },
	91	{ 0x0004, 0xfca0ffff },
	92	{ 0x0008, 0x3fbffbf0 },
	93	{ 0x000c, 0x3ffdffff },
	94	{ 0x0010, 0x00ffffff },
	95	{ 0x0014, 0xfc3ffff3 },
	96	{ 0x0018, 0xe4fdfff7 },
	97	};
	98
	99	static const struct reg_config pfc_without_unlock[] = {
	100	{ 0x0104, 0xffffbfff },
	101	{ 0x0108, 0xb1ffffe1 },
	102	{ 0x010c, 0xffffffff },
	103	{ 0x0110, 0xffffffff },
	104	{ 0x0114, 0xe047beab },
	105	{ 0x0118, 0x00000203 },
	106	};
	107
	108	static const u32 pfc_base = 0xe6060000;
	109
	110	unsigned int i;
	111
	112	for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
	113	writel(~pfc_with_unlock[i].val, pfc_base);
	114	writel(pfc_with_unlock[i].val,
	115	pfc_base \| pfc_with_unlock[i].off);
	116	}
	117
	118	for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
	119	writel(pfc_without_unlock[i].val,
	120	pfc_base \| pfc_without_unlock[i].off);
	121	}
	122
0e592d07	123	static void spl_init_gpio(void)
ec7113fb MV	124	{
	125	static const u16 gpio_offs[] = {
	126	0x1000, 0x3000, 0x4000, 0x5000
	127	};
	128
	129	static const struct reg_config gpio_set[] = {
	130	{ 0x4000, 0x00c00000 },
	131	{ 0x5000, 0x63020000 },
	132	};
	133
	134	static const struct reg_config gpio_clr[] = {
	135	{ 0x1000, 0x00000000 },
	136	{ 0x3000, 0x00000000 },
	137	{ 0x4000, 0x00c00000 },
	138	{ 0x5000, 0xe3020000 },
	139	};
	140
	141	static const u32 gpio_base = 0xe6050000;
	142
	143	unsigned int i;
	144
	145	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
	146	writel(0, gpio_base \| 0x20 \| gpio_offs[i]);
	147
	148	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
	149	writel(0, gpio_base \| 0x00 \| gpio_offs[i]);
	150
	151	for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
	152	writel(gpio_set[i].val, gpio_base \| 0x08 \| gpio_set[i].off);
	153
	154	for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
	155	writel(gpio_clr[i].val, gpio_base \| 0x04 \| gpio_clr[i].off);
	156	}
	157
0e592d07	158	static void spl_init_lbsc(void)
ec7113fb MV	159	{
	160	static const struct reg_config lbsc_config[] = {
	161	{ 0x00, 0x00000020 },
	162	{ 0x08, 0x00002020 },
	163	{ 0x30, 0x02150326 },
	164	{ 0x38, 0x077f077f },
	165	};
	166
	167	static const u16 lbsc_offs[] = {
	168	0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
	169	};
	170
	171	static const u32 lbsc_base = 0xfec00200;
	172
	173	unsigned int i;
	174
	175	for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
	176	writel(lbsc_config[i].val,
	177	lbsc_base \| lbsc_config[i].off);
	178	writel(lbsc_config[i].val,
	179	lbsc_base \| (lbsc_config[i].off + 4));
	180	}
	181
	182	for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
	183	writel(0, lbsc_base \| lbsc_offs[i]);
	184	}
	185
0e592d07	186	static void spl_init_dbsc(void)
ec7113fb MV	187	{
	188	static const struct reg_config dbsc_config1[] = {
	189	{ 0x0280, 0x0000a55a },
	190	{ 0x0018, 0x21000000 },
	191	{ 0x0018, 0x11000000 },
	192	{ 0x0018, 0x10000000 },
	193	{ 0x0290, 0x00000001 },
	194	{ 0x02a0, 0x80000000 },
	195	{ 0x0290, 0x00000004 },
	196	};
	197
	198	static const struct reg_config dbsc_config2[] = {
	199	{ 0x0290, 0x00000006 },
	200	{ 0x02a0, 0x0001c000 },
	201	};
	202
	203	static const struct reg_config dbsc_config3r0d0[] = {
	204	{ 0x0290, 0x0000000f },
	205	{ 0x02a0, 0x00181885 },
	206	{ 0x0290, 0x00000070 },
	207	{ 0x02a0, 0x7c000887 },
	208	{ 0x0290, 0x00000080 },
	209	{ 0x02a0, 0x7c000887 },
	210	{ 0x0290, 0x00000090 },
	211	{ 0x02a0, 0x7c000887 },
	212	{ 0x0290, 0x000000a0 },
	213	{ 0x02a0, 0x7c000887 },
	214	{ 0x0290, 0x000000b0 },
	215	{ 0x02a0, 0x7c000880 },
	216	{ 0x0290, 0x000000c0 },
	217	{ 0x02a0, 0x7c000880 },
	218	{ 0x0290, 0x000000d0 },
	219	{ 0x02a0, 0x7c000880 },
	220	{ 0x0290, 0x000000e0 },
	221	{ 0x02a0, 0x7c000880 },
	222	};
	223
	224	static const struct reg_config dbsc_config3r0d1[] = {
	225	{ 0x0290, 0x0000000f },
	226	{ 0x02a0, 0x00181885 },
	227	{ 0x0290, 0x00000070 },
	228	{ 0x02a0, 0x7c000887 },
	229	{ 0x0290, 0x00000080 },
	230	{ 0x02a0, 0x7c000887 },
	231	{ 0x0290, 0x00000090 },
	232	{ 0x02a0, 0x7c000887 },
	233	{ 0x0290, 0x000000a0 },
	234	{ 0x02a0, 0x7c000887 },
	235	};
	236
	237	static const struct reg_config dbsc_config3r2[] = {
	238	{ 0x0290, 0x0000000f },
	239	{ 0x02a0, 0x00181224 },
	240	};
	241
	242	static const struct reg_config dbsc_config4[] = {
	243	{ 0x0290, 0x00000010 },
	244	{ 0x02a0, 0xf004649b },
	245	{ 0x0290, 0x00000061 },
	246	{ 0x02a0, 0x0000006d },
	247	{ 0x0290, 0x00000001 },
	248	{ 0x02a0, 0x00000073 },
	249	{ 0x0020, 0x00000007 },
	250	{ 0x0024, 0x0f030a02 },
251	{ 0x0030, 0x00000001 },
252	{ 0x00b0, 0x00000000 },
253	{ 0x0040, 0x0000000b },
254	{ 0x0044, 0x00000008 },
255	{ 0x0048, 0x00000000 },
256	{ 0x0050, 0x0000000b },
257	{ 0x0054, 0x000c000b },
258	{ 0x0058, 0x00000027 },
259	{ 0x005c, 0x0000001c },
260	{ 0x0060, 0x00000006 },
261	{ 0x0064, 0x00000020 },
262	{ 0x0068, 0x00000008 },
263	{ 0x006c, 0x0000000c },
264	{ 0x0070, 0x00000009 },
265	{ 0x0074, 0x00000012 },
266	{ 0x0078, 0x000000d0 },
267	{ 0x007c, 0x00140005 },
268	{ 0x0080, 0x00050004 },
269	{ 0x0084, 0x70233005 },
270	{ 0x0088, 0x000c0000 },
271	{ 0x008c, 0x00000200 },
272	{ 0x0090, 0x00000040 },
273	{ 0x0100, 0x00000001 },
274	{ 0x00c0, 0x00020001 },
275	{ 0x00c8, 0x20042004 },
276	{ 0x0380, 0x00020002 },
277	{ 0x0390, 0x0000001f },
278	};
279
280	static const struct reg_config dbsc_config5[] = {
281	{ 0x0244, 0x00000011 },
282	{ 0x0290, 0x00000003 },
283	{ 0x02a0, 0x0300c4e1 },
284	{ 0x0290, 0x00000023 },
285	{ 0x02a0, 0x00fcdb60 },
286	{ 0x0290, 0x00000011 },
287	{ 0x02a0, 0x1000040b },
288	{ 0x0290, 0x00000012 },
289	{ 0x02a0, 0x9d9cbb66 },
290	{ 0x0290, 0x00000013 },
291	{ 0x02a0, 0x1a868400 },
292	{ 0x0290, 0x00000014 },
293	{ 0x02a0, 0x300214d8 },
294	{ 0x0290, 0x00000015 },
295	{ 0x02a0, 0x00000d70 },
296	{ 0x0290, 0x00000016 },
297	{ 0x02a0, 0x00000006 },
298	{ 0x0290, 0x00000017 },
299	{ 0x02a0, 0x00000018 },
300	{ 0x0290, 0x0000001a },
301	{ 0x02a0, 0x910035c7 },
302	{ 0x0290, 0x00000004 },
303	};
304
305	static const struct reg_config dbsc_config6[] = {
306	{ 0x0290, 0x00000001 },
307	{ 0x02a0, 0x00000181 },
308	{ 0x0018, 0x11000000 },
309	{ 0x0290, 0x00000004 },
310	};
311
312	static const struct reg_config dbsc_config7[] = {
313	{ 0x0290, 0x00000001 },
314	{ 0x02a0, 0x0000fe01 },
315	{ 0x0304, 0x00000000 },
316	{ 0x00f4, 0x01004c20 },
317	{ 0x00f8, 0x014000aa },
318	{ 0x00e0, 0x00000140 },
319	{ 0x00e4, 0x00081860 },
320	{ 0x00e8, 0x00010000 },
321	{ 0x0290, 0x00000004 },
322	};
323
324	static const struct reg_config dbsc_config8[] = {
325	{ 0x0014, 0x00000001 },
326	{ 0x0010, 0x00000001 },
327	{ 0x0280, 0x00000000 },
328	};
329
330	static const u32 dbsc3_0_base = DBSC3_0_BASE;
331	static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
332	static const u32 prr_base = 0xff000044;
333	const u16 prr_rev = readl(prr_base) & 0x7fff;
334	unsigned int i;
335
336	for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) {
337	writel(dbsc_config1[i].val, dbsc3_0_base \| dbsc_config1[i].off);
338	writel(dbsc_config1[i].val, dbsc3_1_base \| dbsc_config1[i].off);
339	}
340
341	dbsc_wait(0x2a0);
342
343	for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) {
344	writel(dbsc_config2[i].val, dbsc3_0_base \| dbsc_config2[i].off);
345	writel(dbsc_config2[i].val, dbsc3_1_base \| dbsc_config2[i].off);
346	}
347
348	if (prr_rev == 0x4500) {
349	for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d0); i++) {
350	writel(dbsc_config3r0d0[i].val,
351	dbsc3_0_base \| dbsc_config3r0d0[i].off);
352	}
353	for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d1); i++) {
354	writel(dbsc_config3r0d1[i].val,
355	dbsc3_1_base \| dbsc_config3r0d1[i].off);
356	}
357	} else if (prr_rev != 0x4510) {
358	for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) {
359	writel(dbsc_config3r2[i].val,
360	dbsc3_0_base \| dbsc_config3r2[i].off);
361	writel(dbsc_config3r2[i].val,
362	dbsc3_1_base \| dbsc_config3r2[i].off);
363	}
364	}
365
366	for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) {
367	writel(dbsc_config4[i].val, dbsc3_0_base \| dbsc_config4[i].off);
368	writel(dbsc_config4[i].val, dbsc3_1_base \| dbsc_config4[i].off);
369	}
370
371	dbsc_wait(0x240);
372
373	for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) {
374	writel(dbsc_config5[i].val, dbsc3_0_base \| dbsc_config5[i].off);
375	writel(dbsc_config5[i].val, dbsc3_1_base \| dbsc_config5[i].off);
376	}
377
378	dbsc_wait(0x2a0);
379
380	for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) {
381	writel(dbsc_config6[i].val, dbsc3_0_base \| dbsc_config6[i].off);
382	writel(dbsc_config6[i].val, dbsc3_1_base \| dbsc_config6[i].off);
383	}
384
385	dbsc_wait(0x2a0);
386
387	for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) {
388	writel(dbsc_config7[i].val, dbsc3_0_base \| dbsc_config7[i].off);
389	writel(dbsc_config7[i].val, dbsc3_1_base \| dbsc_config7[i].off);
390	}
391
392	dbsc_wait(0x2a0);
393
394	for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) {
395	writel(dbsc_config8[i].val, dbsc3_0_base \| dbsc_config8[i].off);
396	writel(dbsc_config8[i].val, dbsc3_1_base \| dbsc_config8[i].off);
397	}
398
399	}
400
0e592d07	401	static void spl_init_qspi(void)
ec7113fb MV	402	{
	403	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
	404
	405	static const u32 qspi_base = 0xe6b10000;
	406
	407	writeb(0x08, qspi_base + 0x00);
	408	writeb(0x00, qspi_base + 0x01);
	409	writeb(0x06, qspi_base + 0x02);
	410	writeb(0x01, qspi_base + 0x0a);
	411	writeb(0x00, qspi_base + 0x0b);
	412	writeb(0x00, qspi_base + 0x0c);
	413	writeb(0x00, qspi_base + 0x0d);
	414	writeb(0x00, qspi_base + 0x0e);
	415
	416	writew(0xe080, qspi_base + 0x10);
	417
	418	writeb(0xc0, qspi_base + 0x18);
	419	writeb(0x00, qspi_base + 0x18);
	420	writeb(0x00, qspi_base + 0x08);
	421	writeb(0x48, qspi_base + 0x00);
	422	}
	423
	424	void board_init_f(ulong dummy)
	425	{
	426	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
	427	mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIFA0_MSTP204);
	428
	429	/*
	430	* SD0 clock is set to 97.5MHz by default.
	431	* Set SD2 to the 97.5MHz as well.
	432	*/
	433	writel(SD_97500KHZ, SD2CKCR);
	434
0e592d07 MV	435	spl_init_sys();
	436	spl_init_pfc();
	437	spl_init_gpio();
	438	spl_init_lbsc();
	439	spl_init_dbsc();
	440	spl_init_qspi();
ec7113fb	441	}
ec7113fb MV	442
	443	void spl_board_init(void)
	444	{
	445	/* UART clocks enabled and gd valid - init serial console */
	446	preloader_console_init();
	447	}
	448
	449	void board_boot_order(u32 *spl_boot_list)
	450	{
ec7113fb MV	451	const u32 jtag_magic = 0x1337c0de;
	452	const u32 load_magic = 0xb33fc0de;
	453
	454	/*
	455	* If JTAG probe sets special word at 0xe6300020, then it must
0e592d07	456	* put U-Boot into RAM and SPL will start it from RAM.
ec7113fb	457	*/
0e592d07	458	if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
ec7113fb MV	459	printf("JTAG boot detected!\n");
ec7113fb MV	460
0e592d07	461	while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
ec7113fb MV	462	;
	463
	464	spl_boot_list[0] = BOOT_DEVICE_RAM;
	465	spl_boot_list[1] = BOOT_DEVICE_NONE;
	466
	467	return;
	468	}
ec7113fb MV	469
	470	/* Boot from SPI NOR with YMODEM UART fallback. */
	471	spl_boot_list[0] = BOOT_DEVICE_SPI;
	472	spl_boot_list[1] = BOOT_DEVICE_UART;
	473	spl_boot_list[2] = BOOT_DEVICE_NONE;
	474	}
	475
35b65dd8	476	void reset_cpu(void)
ec7113fb MV	477	{
ec7113fb MV	478	}