projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| bd39050c MV |
2 | /* |
| 3 | * board/renesas/ulcb/ulcb.c | |
| 4 | * This file is ULCB board support. | |
| 5 | * | |
| 6 | * Copyright (C) 2017 Renesas Electronics Corporation | |
| bd39050c MV |
7 | */ |
| 8 | ||
| 4d72caa5 | 9 | #include <image.h> |
| 691d719d | 10 | #include <init.h> |
| bd39050c MV |
11 | #include <malloc.h> |
| 12 | #include <netdev.h> | |
| 13 | #include <dm.h> | |
| 401d1c4f | 14 | #include <asm/global_data.h> |
| bd39050c MV |
15 | #include <dm/platform_data/serial_sh.h> |
| 16 | #include <asm/processor.h> | |
| 17 | #include <asm/mach-types.h> | |
| 18 | #include <asm/io.h> | |
| cd93d625 | 19 | #include <linux/bitops.h> |
| bd39050c MV |
20 | #include <linux/errno.h> |
| 21 | #include <asm/arch/sys_proto.h> | |
| 22 | #include <asm/gpio.h> | |
| 23 | #include <asm/arch/gpio.h> | |
| 24 | #include <asm/arch/rmobile.h> | |
| 25 | #include <asm/arch/rcar-mstp.h> | |
| bd39050c MV |
26 | #include <i2c.h> |
| 27 | #include <mmc.h> | |
| 28 | ||
| 29 | DECLARE_GLOBAL_DATA_PTR; | |
| 30 | ||
| bd39050c | 31 | #define DVFS_MSTP926 BIT(26) |
| ef603233 | 32 | #define HSUSB_MSTP704 BIT(4) /* HSUSB */ |
| bd39050c | 33 | |
| bd39050c MV |
34 | int board_early_init_f(void) |
| 35 | { | |
| 55dabcc8 | 36 | #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) |
| bd39050c | 37 | /* DVFS for reset */ |
| cf97b221 | 38 | mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926); |
| bd39050c MV |
39 | #endif |
| 40 | return 0; | |
| 41 | } | |
| 42 | ||
| ef603233 MV |
43 | /* HSUSB block registers */ |
| 44 | #define HSUSB_REG_LPSTS 0xE6590102 | |
| 45 | #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) | |
| 46 | #define HSUSB_REG_UGCTRL2 0xE6590184 | |
| 47 | #define HSUSB_REG_UGCTRL2_USB0SEL 0x30 | |
| 48 | #define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10 | |
| 49 | ||
| bd39050c MV |
50 | int board_init(void) |
| 51 | { | |
| bd39050c MV |
52 | /* USB1 pull-up */ |
| 53 | setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); | |
| 54 | ||
| ef603233 | 55 | /* Configure the HSUSB block */ |
| cf97b221 | 56 | mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704); |
| ef603233 MV |
57 | /* Choice USB0SEL */ |
| 58 | clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL, | |
| 59 | HSUSB_REG_UGCTRL2_USB0SEL_EHCI); | |
| 60 | /* low power status */ | |
| 61 | setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL); | |
| 62 | ||
| 6f380854 | 63 | return 0; |
| bd39050c | 64 | } |
| bd39050c | 65 | |
| 04513805 MV |
66 | #ifdef CONFIG_MULTI_DTB_FIT |
| 67 | int board_fit_config_name_match(const char *name) | |
| 68 | { | |
| 69 | /* PRR driver is not available yet */ | |
| 70 | u32 cpu_type = rmobile_get_cpu_type(); | |
| 71 | ||
| 72 | if ((cpu_type == RMOBILE_CPU_TYPE_R8A7795) && | |
| c7d68120 | 73 | !strcmp(name, "r8a77950-ulcb-u-boot")) |
| 04513805 MV |
74 | return 0; |
| 75 | ||
| 76 | if ((cpu_type == RMOBILE_CPU_TYPE_R8A7796) && | |
| c7d68120 | 77 | !strcmp(name, "r8a77960-ulcb-u-boot")) |
| 04513805 MV |
78 | return 0; |
| 79 | ||
| c4ea43d1 | 80 | if ((cpu_type == RMOBILE_CPU_TYPE_R8A77965) && |
| c7d68120 | 81 | !strcmp(name, "r8a77965-ulcb-u-boot")) |
| c4ea43d1 MV |
82 | return 0; |
| 83 | ||
| 04513805 MV |
84 | return -1; |
| 85 | } | |
| 86 | #endif |