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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
2d1951fe AY |
2 | /* |
3 | * (C)Copyright 2016 Rockchip Electronics Co., Ltd | |
4 | * Authors: Andy Yan <andy.yan@rock-chips.com> | |
2d1951fe AY |
5 | */ |
6 | ||
d678a59d | 7 | #include <common.h> |
691d719d | 8 | #include <init.h> |
9cec3367 | 9 | #include <syscon.h> |
401d1c4f | 10 | #include <asm/global_data.h> |
9cec3367 | 11 | #include <asm/arch-rockchip/clock.h> |
15f09a1a KY |
12 | #include <asm/arch-rockchip/grf_rv1108.h> |
13 | #include <asm/arch-rockchip/hardware.h> | |
2d1951fe AY |
14 | |
15 | DECLARE_GLOBAL_DATA_PTR; | |
16 | ||
f11f138e | 17 | int board_early_init_f(void) |
2d1951fe | 18 | { |
2d1951fe | 19 | struct rv1108_grf *grf; |
77c42611 DW |
20 | enum { |
21 | GPIO3C3_SHIFT = 6, | |
22 | GPIO3C3_MASK = 3 << GPIO3C3_SHIFT, | |
23 | ||
24 | GPIO3C2_SHIFT = 4, | |
25 | GPIO3C2_MASK = 3 << GPIO3C2_SHIFT, | |
26 | ||
27 | GPIO2D2_SHIFT = 4, | |
28 | GPIO2D2_MASK = 3 << GPIO2D2_SHIFT, | |
29 | GPIO2D2_GPIO = 0, | |
30 | GPIO2D2_UART2_SOUT_M0, | |
31 | ||
32 | GPIO2D1_SHIFT = 2, | |
33 | GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, | |
34 | GPIO2D1_GPIO = 0, | |
35 | GPIO2D1_UART2_SIN_M0, | |
36 | }; | |
2d1951fe | 37 | |
9cec3367 | 38 | grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); |
2d1951fe AY |
39 | |
40 | /*evb board use UART2 m0 for debug*/ | |
41 | rk_clrsetreg(&grf->gpio2d_iomux, | |
42 | GPIO2D2_MASK | GPIO2D1_MASK, | |
43 | GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT | | |
44 | GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT); | |
45 | rk_clrreg(&grf->gpio3c_iomux, GPIO3C3_MASK | GPIO3C2_MASK); | |
46 | ||
47 | return 0; | |
48 | } | |
49 | ||
2d1951fe AY |
50 | int dram_init(void) |
51 | { | |
52 | gd->ram_size = 0x8000000; | |
53 | ||
54 | return 0; | |
55 | } |