[people/ms/u-boot.git] / board / ronetix / pm9261 / pm9261.c

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian.pop@leadtechdesign.com>
 * Lead Tech Design <www.leadtechdesign.com>
 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
 * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/sizes.h>
#include <asm/io.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_matrix.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>

#include <lcd.h>
#include <atmel_lcdc.h>
#include <dataflash.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
#include <net.h>
#endif
#include <netdev.h>

DECLARE_GLOBAL_DATA_PTR;

/* ------------------------------------------------------------------------- */
/*
 * Miscelaneous platform dependent initialisations
 */

#ifdef CONFIG_CMD_NAND
static void pm9261_nand_hw_init(void)
{
	unsigned long csa;
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;

	/* Enable CS3 */
	csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
	writel(csa, &matrix->csa);

	/* Configure SMC CS3 for NAND/SmartMedia */
	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
		&smc->cs[3].setup);

	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
		&smc->cs[3].pulse);

	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
		&smc->cs[3].cycle);

	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
		AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
		AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
		AT91_SMC_MODE_DBW_8 |
#endif
		AT91_SMC_MODE_TDF_CYCLE(2),
		&smc->cs[3].mode);

	writel(1 << ATMEL_ID_PIOA |
		1 << ATMEL_ID_PIOC,
		&pmc->pcer);

	/* Configure RDY/BSY */
	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);

	/* Enable NandFlash */
	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);

	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* NANDOE */
	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* NANDWE */
}
#endif


#ifdef CONFIG_DRIVER_DM9000
static void pm9261_dm9000_hw_init(void)
{
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;

	/* Configure SMC CS2 for DM9000 */
	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
		&smc->cs[2].setup);

	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
		&smc->cs[2].pulse);

	writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
		&smc->cs[2].cycle);

	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
		AT91_SMC_MODE_EXNW_DISABLE |
		AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
		AT91_SMC_MODE_TDF_CYCLE(1),
		&smc->cs[2].mode);

	/* Configure Interrupt pin as input, no pull-up */
	writel(1 << ATMEL_ID_PIOA, &pmc->pcer);
	at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
}
#endif

#ifdef CONFIG_LCD
vidinfo_t panel_info = {
	vl_col:		240,
	vl_row:		320,
	vl_clk:		4965000,
	vl_sync:	ATMEL_LCDC_INVLINE_INVERTED |
			ATMEL_LCDC_INVFRAME_INVERTED,
	vl_bpix:	3,
	vl_tft:		1,
	vl_hsync_len:	5,
	vl_left_margin:	1,
	vl_right_margin:33,
	vl_vsync_len:	1,
	vl_upper_margin:1,
	vl_lower_margin:0,
	mmio:		ATMEL_BASE_LCDC,
};

void lcd_enable(void)
{
	at91_set_pio_value(AT91_PIO_PORTA, 22, 0);  /* power up */
}

void lcd_disable(void)
{
	at91_set_pio_value(AT91_PIO_PORTA, 22, 1);  /* power down */
}

static void pm9261_lcd_hw_init(void)
{
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;

	at91_set_a_periph(AT91_PIO_PORTB, 1, 0);	/* LCDHSYNC */
	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* LCDDOTCK */
	at91_set_a_periph(AT91_PIO_PORTB, 3, 0);	/* LCDDEN */
	at91_set_a_periph(AT91_PIO_PORTB, 4, 0);	/* LCDCC */
	at91_set_a_periph(AT91_PIO_PORTB, 7, 0);	/* LCDD2 */
	at91_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* LCDD3 */
	at91_set_a_periph(AT91_PIO_PORTB, 9, 0);	/* LCDD4 */
	at91_set_a_periph(AT91_PIO_PORTB, 10, 0);	/* LCDD5 */
	at91_set_a_periph(AT91_PIO_PORTB, 11, 0);	/* LCDD6 */
	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* LCDD7 */
	at91_set_a_periph(AT91_PIO_PORTB, 15, 0);	/* LCDD10 */
	at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* LCDD11 */
	at91_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* LCDD12 */
	at91_set_a_periph(AT91_PIO_PORTB, 18, 0);	/* LCDD13 */
	at91_set_a_periph(AT91_PIO_PORTB, 19, 0);	/* LCDD14 */
	at91_set_a_periph(AT91_PIO_PORTB, 20, 0);	/* LCDD15 */
	at91_set_b_periph(AT91_PIO_PORTB, 23, 0);	/* LCDD18 */
	at91_set_b_periph(AT91_PIO_PORTB, 24, 0);	/* LCDD19 */
	at91_set_b_periph(AT91_PIO_PORTB, 25, 0);	/* LCDD20 */
	at91_set_b_periph(AT91_PIO_PORTB, 26, 0);	/* LCDD21 */
	at91_set_b_periph(AT91_PIO_PORTB, 27, 0);	/* LCDD22 */
	at91_set_b_periph(AT91_PIO_PORTB, 28, 0);	/* LCDD23 */

	writel(1 << 17, &pmc->scer); /* LCD controller Clock, AT91SAM9261 only */

	gd->fb_base = ATMEL_BASE_SRAM;
}

#ifdef CONFIG_LCD_INFO
#include <nand.h>
#include <version.h>

extern flash_info_t flash_info[];

void lcd_show_board_info(void)
{
	ulong dram_size, nand_size, flash_size, dataflash_size;
	int i;
	char temp[32];

	lcd_printf ("%s\n", U_BOOT_VERSION);
	lcd_printf ("(C) 2009 Ronetix GmbH\n");
	lcd_printf ("support@ronetix.at\n");
	lcd_printf ("%s CPU at %s MHz",
		CONFIG_SYS_AT91_CPU_NAME,
		strmhz(temp, get_cpu_clk_rate()));

	dram_size = 0;
	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
		dram_size += gd->bd->bi_dram[i].size;

	nand_size = 0;
	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
		nand_size += nand_info[i].size;

	flash_size = 0;
	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
		flash_size += flash_info[i].size;

	dataflash_size = 0;
	for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
		dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
				dataflash_info[i].Device.pages_size;

	lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
			"%ld MB DataFlash\n",
		dram_size >> 20,
		nand_size >> 20,
		flash_size >> 20,
		dataflash_size >> 20);
}
#endif /* CONFIG_LCD_INFO */

#endif /* CONFIG_LCD */

int board_init(void)
{
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;

	/* Enable Ctrlc */
	console_init_f();

	writel(1 << ATMEL_ID_PIOA |
		1 << ATMEL_ID_PIOC,
		&pmc->pcer);

	/* adress of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

	at91_seriald_hw_init();
#ifdef CONFIG_CMD_NAND
	pm9261_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
	at91_spi0_hw_init(1 << 0);
#endif
#ifdef CONFIG_DRIVER_DM9000
	pm9261_dm9000_hw_init();
#endif
#ifdef CONFIG_LCD
	pm9261_lcd_hw_init();
#endif
	return 0;
}

#ifdef CONFIG_DRIVER_DM9000
int board_eth_init(bd_t *bis)
{
	return dm9000_initialize(bis);
}
#endif

int dram_init(void)
{
	/* dram_init must store complete ramsize in gd->ram_size */
	gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
				PHYS_SDRAM_SIZE);
	return 0;
}

void dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM;
	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
}

#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#ifdef CONFIG_DRIVER_DM9000
	/*
	 * Initialize ethernet HW addr prior to starting Linux,
	 * needed for nfsroot
	 */
	eth_init(gd->bd);
#endif
}
#endif

#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard (void)
{
	char buf[32];

	printf ("Board : Ronetix PM9261\n");
	printf ("Crystal frequency: %8s MHz\n",
					strmhz(buf, get_main_clk_rate()));
	printf ("CPU clock        : %8s MHz\n",
					strmhz(buf, get_cpu_clk_rate()));
	printf ("Master clock     : %8s MHz\n",
					strmhz(buf, get_mck_clk_rate()));

	return 0;
}
#endif
Commit	Line	Data
32949232 II	1	/*
	2	* (C) Copyright 2007-2008
	3	* Stelian Pop <stelian.pop@leadtechdesign.com>
	4	* Lead Tech Design <www.leadtechdesign.com>
	5	* Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
	6	* Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#include <common.h>
	28	#include <asm/sizes.h>
f47316a8	29	#include <asm/io.h>
32949232 II	30	#include <asm/arch/at91sam9_smc.h>
	31	#include <asm/arch/at91_common.h>
	32	#include <asm/arch/at91_pmc.h>
	33	#include <asm/arch/at91_rstc.h>
e3150c77	34	#include <asm/arch/at91_matrix.h>
32949232	35	#include <asm/arch/clk.h>
f47316a8 AD	36	#include <asm/arch/gpio.h>
f47316a8 AD	37
32949232 II	38	#include <lcd.h>
	39	#include <atmel_lcdc.h>
	40	#include <dataflash.h>
	41	#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
	42	#include <net.h>
	43	#endif
	44	#include <netdev.h>
	45
	46	DECLARE_GLOBAL_DATA_PTR;
	47
	48	/* ------------------------------------------------------------------------- */
	49	/*
	50	* Miscelaneous platform dependent initialisations
	51	*/
	52
	53	#ifdef CONFIG_CMD_NAND
	54	static void pm9261_nand_hw_init(void)
	55	{
	56	unsigned long csa;
f47316a8 AD	57	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC;
	58	struct at91_matrix matrix = (struct at91_matrix )ATMEL_BASE_MATRIX;
	59	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
32949232 II	60
32949232 II	61	/* Enable CS3 */
e3150c77 AD	62	csa = readl(&matrix->csa) \| AT91_MATRIX_CSA_EBI_CS3A;
e3150c77 AD	63	writel(csa, &matrix->csa);
32949232 II	64
32949232 II	65	/* Configure SMC CS3 for NAND/SmartMedia */
e3150c77 AD	66	writel(AT91_SMC_SETUP_NWE(1) \| AT91_SMC_SETUP_NCS_WR(0) \|
	67	AT91_SMC_SETUP_NRD(1) \| AT91_SMC_SETUP_NCS_RD(0),
	68	&smc->cs[3].setup);
	69
	70	writel(AT91_SMC_PULSE_NWE(3) \| AT91_SMC_PULSE_NCS_WR(3) \|
	71	AT91_SMC_PULSE_NRD(3) \| AT91_SMC_PULSE_NCS_RD(3),
	72	&smc->cs[3].pulse);
	73
	74	writel(AT91_SMC_CYCLE_NWE(5) \| AT91_SMC_CYCLE_NRD(5),
	75	&smc->cs[3].cycle);
	76
	77	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	78	AT91_SMC_MODE_EXNW_DISABLE \|
32949232	79	#ifdef CONFIG_SYS_NAND_DBW_16
e3150c77	80	AT91_SMC_MODE_DBW_16 \|
32949232	81	#else /* CONFIG_SYS_NAND_DBW_8 */
e3150c77	82	AT91_SMC_MODE_DBW_8 \|
32949232	83	#endif
e3150c77 AD	84	AT91_SMC_MODE_TDF_CYCLE(2),
	85	&smc->cs[3].mode);
	86
f47316a8 AD	87	writel(1 << ATMEL_ID_PIOA \|
f47316a8 AD	88	1 << ATMEL_ID_PIOC,
e3150c77	89	&pmc->pcer);
32949232 II	90
32949232 II	91	/* Configure RDY/BSY */
e3150c77	92	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
32949232 II	93
32949232 II	94	/* Enable NandFlash */
e3150c77	95	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
32949232	96
e3150c77 AD	97	at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */
e3150c77 AD	98	at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */
32949232 II	99	}
	100	#endif
	101
	102
	103	#ifdef CONFIG_DRIVER_DM9000
	104	static void pm9261_dm9000_hw_init(void)
	105	{
f47316a8 AD	106	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC;
f47316a8 AD	107	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
e3150c77	108
32949232	109	/* Configure SMC CS2 for DM9000 */
e3150c77 AD	110	writel(AT91_SMC_SETUP_NWE(2) \| AT91_SMC_SETUP_NCS_WR(0) \|
	111	AT91_SMC_SETUP_NRD(2) \| AT91_SMC_SETUP_NCS_RD(0),
	112	&smc->cs[2].setup);
	113
	114	writel(AT91_SMC_PULSE_NWE(4) \| AT91_SMC_PULSE_NCS_WR(8) \|
	115	AT91_SMC_PULSE_NRD(4) \| AT91_SMC_PULSE_NCS_RD(8),
	116	&smc->cs[2].pulse);
	117
	118	writel(AT91_SMC_CYCLE_NWE(16) \| AT91_SMC_CYCLE_NRD(16),
	119	&smc->cs[2].cycle);
	120
	121	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	122	AT91_SMC_MODE_EXNW_DISABLE \|
	123	AT91_SMC_MODE_BAT \| AT91_SMC_MODE_DBW_16 \|
	124	AT91_SMC_MODE_TDF_CYCLE(1),
	125	&smc->cs[2].mode);
32949232 II	126
32949232 II	127	/* Configure Interrupt pin as input, no pull-up */
f47316a8	128	writel(1 << ATMEL_ID_PIOA, &pmc->pcer);
e3150c77	129	at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
32949232 II	130	}
	131	#endif
	132
	133	#ifdef CONFIG_LCD
	134	vidinfo_t panel_info = {
	135	vl_col: 240,
	136	vl_row: 320,
	137	vl_clk: 4965000,
	138	vl_sync: ATMEL_LCDC_INVLINE_INVERTED \|
	139	ATMEL_LCDC_INVFRAME_INVERTED,
	140	vl_bpix: 3,
	141	vl_tft: 1,
	142	vl_hsync_len: 5,
	143	vl_left_margin: 1,
	144	vl_right_margin:33,
	145	vl_vsync_len: 1,
	146	vl_upper_margin:1,
	147	vl_lower_margin:0,
f47316a8	148	mmio: ATMEL_BASE_LCDC,
32949232 II	149	};
	150
	151	void lcd_enable(void)
	152	{
e3150c77	153	at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power up */
32949232 II	154	}
	155
	156	void lcd_disable(void)
	157	{
e3150c77	158	at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power down */
32949232 II	159	}
	160
	161	static void pm9261_lcd_hw_init(void)
	162	{
f47316a8	163	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
e3150c77 AD	164
	165	at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* LCDHSYNC */
	166	at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* LCDDOTCK */
	167	at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* LCDDEN */
	168	at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* LCDCC */
	169	at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* LCDD2 */
	170	at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* LCDD3 */
	171	at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* LCDD4 */
	172	at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* LCDD5 */
	173	at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* LCDD6 */
	174	at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* LCDD7 */
	175	at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* LCDD10 */
	176	at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* LCDD11 */
	177	at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* LCDD12 */
	178	at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* LCDD13 */
	179	at91_set_a_periph(AT91_PIO_PORTB, 19, 0); /* LCDD14 */
	180	at91_set_a_periph(AT91_PIO_PORTB, 20, 0); /* LCDD15 */
	181	at91_set_b_periph(AT91_PIO_PORTB, 23, 0); /* LCDD18 */
	182	at91_set_b_periph(AT91_PIO_PORTB, 24, 0); /* LCDD19 */
	183	at91_set_b_periph(AT91_PIO_PORTB, 25, 0); /* LCDD20 */
	184	at91_set_b_periph(AT91_PIO_PORTB, 26, 0); /* LCDD21 */
	185	at91_set_b_periph(AT91_PIO_PORTB, 27, 0); /* LCDD22 */
	186	at91_set_b_periph(AT91_PIO_PORTB, 28, 0); /* LCDD23 */
	187
	188	writel(1 << 17, &pmc->scer); /* LCD controller Clock, AT91SAM9261 only */
32949232	189
f47316a8	190	gd->fb_base = ATMEL_BASE_SRAM;
32949232 II	191	}
	192
	193	#ifdef CONFIG_LCD_INFO
	194	#include <nand.h>
	195	#include <version.h>
	196
	197	extern flash_info_t flash_info[];
	198
	199	void lcd_show_board_info(void)
	200	{
	201	ulong dram_size, nand_size, flash_size, dataflash_size;
	202	int i;
	203	char temp[32];
	204
	205	lcd_printf ("%s\n", U_BOOT_VERSION);
	206	lcd_printf ("(C) 2009 Ronetix GmbH\n");
	207	lcd_printf ("support@ronetix.at\n");
	208	lcd_printf ("%s CPU at %s MHz",
7c966a8b	209	CONFIG_SYS_AT91_CPU_NAME,
32949232 II	210	strmhz(temp, get_cpu_clk_rate()));
	211
	212	dram_size = 0;
	213	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
	214	dram_size += gd->bd->bi_dram[i].size;
	215
	216	nand_size = 0;
	217	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
	218	nand_size += nand_info[i].size;
	219
	220	flash_size = 0;
	221	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
	222	flash_size += flash_info[i].size;
	223
	224	dataflash_size = 0;
	225	for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
	226	dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
	227	dataflash_info[i].Device.pages_size;
	228
	229	lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
	230	"%ld MB DataFlash\n",
	231	dram_size >> 20,
	232	nand_size >> 20,
	233	flash_size >> 20,
	234	dataflash_size >> 20);
	235	}
	236	#endif /* CONFIG_LCD_INFO */
	237
	238	#endif /* CONFIG_LCD */
	239
	240	int board_init(void)
	241	{
f47316a8	242	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
e3150c77	243
32949232 II	244	/* Enable Ctrlc */
	245	console_init_f();
	246
f47316a8 AD	247	writel(1 << ATMEL_ID_PIOA \|
f47316a8 AD	248	1 << ATMEL_ID_PIOC,
e3150c77	249	&pmc->pcer);
32949232	250
32949232 II	251	/* adress of boot parameters */
	252	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	253
f47316a8	254	at91_seriald_hw_init();
32949232 II	255	#ifdef CONFIG_CMD_NAND
	256	pm9261_nand_hw_init();
	257	#endif
	258	#ifdef CONFIG_HAS_DATAFLASH
	259	at91_spi0_hw_init(1 << 0);
	260	#endif
	261	#ifdef CONFIG_DRIVER_DM9000
	262	pm9261_dm9000_hw_init();
	263	#endif
	264	#ifdef CONFIG_LCD
	265	pm9261_lcd_hw_init();
	266	#endif
	267	return 0;
	268	}
	269
e830b66b II	270	#ifdef CONFIG_DRIVER_DM9000
	271	int board_eth_init(bd_t *bis)
	272	{
	273	return dm9000_initialize(bis);
	274	}
	275	#endif
	276
32949232	277	int dram_init(void)
4f81bf43 AD	278	{
4f81bf43 AD	279	/* dram_init must store complete ramsize in gd->ram_size */
a55d23cc	280	gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
4f81bf43 AD	281	PHYS_SDRAM_SIZE);
	282	return 0;
	283	}
	284
	285	void dram_init_banksize(void)
32949232 II	286	{
	287	gd->bd->bi_dram[0].start = PHYS_SDRAM;
	288	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
32949232 II	289	}
	290
	291	#ifdef CONFIG_RESET_PHY_R
	292	void reset_phy(void)
	293	{
	294	#ifdef CONFIG_DRIVER_DM9000
	295	/*
	296	* Initialize ethernet HW addr prior to starting Linux,
	297	* needed for nfsroot
	298	*/
	299	eth_init(gd->bd);
	300	#endif
	301	}
	302	#endif
	303
	304	#ifdef CONFIG_DISPLAY_BOARDINFO
	305	int checkboard (void)
	306	{
	307	char buf[32];
	308
	309	printf ("Board : Ronetix PM9261\n");
	310	printf ("Crystal frequency: %8s MHz\n",
	311	strmhz(buf, get_main_clk_rate()));
	312	printf ("CPU clock : %8s MHz\n",
	313	strmhz(buf, get_cpu_clk_rate()));
	314	printf ("Master clock : %8s MHz\n",
	315	strmhz(buf, get_mck_clk_rate()));
	316
	317	return 0;
	318	}
	319	#endif