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[people/ms/u-boot.git] / board / ronetix / pm9263 / pm9263.c
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f0a2c7b4
II		 1/*
2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
5 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
6 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <asm/sizes.h>
29#include <asm/arch/at91sam9263.h>
f0a2c7b4
II		 30#include <asm/arch/at91sam9_smc.h>
31#include <asm/arch/at91_common.h>
32#include <asm/arch/at91_pmc.h>
33#include <asm/arch/at91_rstc.h>
20d98c2c
AD		 34#include <asm/arch/at91_matrix.h>
35#include <asm/arch/at91_pio.h>
f0a2c7b4 36#include <asm/arch/clk.h>
f0a2c7b4
II		 37#include <asm/arch/io.h>
38#include <asm/arch/hardware.h>
39#include <lcd.h>
40#include <atmel_lcdc.h>
41#include <dataflash.h>
42#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
43#include <net.h>
44#endif
45#include <netdev.h>
46
47DECLARE_GLOBAL_DATA_PTR;
48
49/* ------------------------------------------------------------------------- */
50/*
51 * Miscelaneous platform dependent initialisations
52 */
53
54#ifdef CONFIG_CMD_NAND
55static void pm9263_nand_hw_init(void)
56{
57 unsigned long csa;
20d98c2c
AD		 58 at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE;
59 at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
f0a2c7b4
II		 60
61 /* Enable CS3 */
20d98c2c
AD		 62 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
63 writel(csa, &matrix->csa[0]);
f0a2c7b4
II		 64
65 /* Configure SMC CS3 for NAND/SmartMedia */
20d98c2c
AD		 66 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
67 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
68 &smc->cs[3].setup);
69
70 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
71 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
72 &smc->cs[3].pulse);
73
74 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
75 &smc->cs[3].cycle);
76
77 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
78 AT91_SMC_MODE_EXNW_DISABLE |
f0a2c7b4 79#ifdef CONFIG_SYS_NAND_DBW_16
20d98c2c 80 AT91_SMC_MODE_DBW_16 |
f0a2c7b4 81#else /* CONFIG_SYS_NAND_DBW_8 */
20d98c2c 82 AT91_SMC_MODE_DBW_8 |
f0a2c7b4 83#endif
20d98c2c
AD		 84 AT91_SMC_MODE_TDF_CYCLE(2),
85 &smc->cs[3].mode);
f0a2c7b4
II		 86
87 /* Configure RDY/BSY */
20d98c2c 88 at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
f0a2c7b4
II		 89
90 /* Enable NandFlash */
20d98c2c 91 at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
f0a2c7b4
II		 92}
93#endif
94
95#ifdef CONFIG_MACB
96static void pm9263_macb_hw_init(void)
97{
20d98c2c 98 at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
20d98c2c 99
f0a2c7b4
II		 100 /*
101 * PB27 enables the 50MHz oscillator for Ethernet PHY
102 * 1 - enable
103 * 0 - disable
104 */
20d98c2c
AD		 105 at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
106 at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */
f0a2c7b4
II		 107
108 /* Enable clock */
20d98c2c 109 writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
f0a2c7b4
II		 110
111 /*
112 * Disable pull-up on:
113 * RXDV (PC25) => PHY normal mode (not Test mode)
114 * ERX0 (PE25) => PHY ADDR0
115 * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
116 *
117 * PHY has internal pull-down
118 */
f0a2c7b4 119
20d98c2c
AD		 120 at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0);
121 at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0);
122 at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0);
f0a2c7b4
II		 123
124 /* Re-enable pull-up */
20d98c2c
AD		 125 at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1);
126 at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1);
127 at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1);
f0a2c7b4
II		 128
129 at91_macb_hw_init();
130}
131#endif
132
133#ifdef CONFIG_LCD
134vidinfo_t panel_info = {
135 vl_col: 240,
136 vl_row: 320,
137 vl_clk: 4965000,
138 vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
139 ATMEL_LCDC_INVFRAME_INVERTED,
140 vl_bpix: 3,
141 vl_tft: 1,
142 vl_hsync_len: 5,
143 vl_left_margin: 1,
144 vl_right_margin:33,
145 vl_vsync_len: 1,
146 vl_upper_margin:1,
147 vl_lower_margin:0,
148 mmio: AT91SAM9263_LCDC_BASE,
149};
150
151void lcd_enable(void)
152{
20d98c2c 153 at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */
f0a2c7b4
II		 154}
155
156void lcd_disable(void)
157{
20d98c2c 158 at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
f0a2c7b4
II		 159}
160
161#ifdef CONFIG_LCD_IN_PSRAM
162
20d98c2c 163#define PSRAM_CRE_PIN AT91_PIO_PORTB, 29
f0a2c7b4
II		 164#define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
165
166/* Initialize the PSRAM memory */
167static int pm9263_lcd_hw_psram_init(void)
168{
169 volatile uint16_t x;
7a11c7f9 170 unsigned long csa;
20d98c2c
AD		 171 at91_smc_t *smc = (at91_smc_t *) AT91_SMC1_BASE;
172 at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
7a11c7f9
JCPV		 173
174 /* Enable CS3 3.3v, no pull-ups */
20d98c2c
AD		 175 csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC |
176 AT91_MATRIX_CSA_VDDIOMSEL_3_3V;
177
178 writel(csa, &matrix->csa[1]);
7a11c7f9
JCPV		 179
180 /* Configure SMC1 CS0 for PSRAM - 16-bit */
20d98c2c
AD		 181 writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
182 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
183 &smc->cs[0].setup);
184
185 writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
186 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7),
187 &smc->cs[0].pulse);
188
189 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
190 &smc->cs[0].cycle);
191
192 writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32,
193 &smc->cs[0].mode);
f0a2c7b4
II		 194
195 /* setup PB29 as output */
20d98c2c 196 at91_set_pio_output(PSRAM_CRE_PIN, 1);
f0a2c7b4 197
20d98c2c 198 at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */
f0a2c7b4
II		 199
200 /* PSRAM: write BCR */
201 x = readw(PSRAM_CTRL_REG);
202 x = readw(PSRAM_CTRL_REG);
203 writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
204 writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */
205
206 /* write RCR of the PSRAM */
207 x = readw(PSRAM_CTRL_REG);
208 x = readw(PSRAM_CTRL_REG);
209 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
210 /* set RCR; 0x10-async mode,0x90-page mode */
211 writew(0x90, PSRAM_CTRL_REG);
212
213 /*
214 * test to see if the PSRAM is MT45W2M16A or MT45W2M16B
215 * MT45W2M16B - CRE must be 0
216 * MT45W2M16A - CRE must be 1
217 */
218 writew(0x1234, PHYS_PSRAM);
219 writew(0x5678, PHYS_PSRAM + 2);
220
221 /* test if the chip is MT45W2M16B */
222 if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
223 /* try with CRE=1 (MT45W2M16A) */
20d98c2c 224 at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
f0a2c7b4
II		 225
226 /* write RCR of the PSRAM */
227 x = readw(PSRAM_CTRL_REG);
228 x = readw(PSRAM_CTRL_REG);
229 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
230 /* set RCR;0x10-async mode,0x90-page mode */
231 writew(0x90, PSRAM_CTRL_REG);
232
233
234 writew(0x1234, PHYS_PSRAM);
235 writew(0x5678, PHYS_PSRAM+2);
236 if ((readw(PHYS_PSRAM) != 0x1234)
20d98c2c 237 || (readw(PHYS_PSRAM + 2) != 0x5678))
f0a2c7b4
II		 238 return 1;
239
240 }
241
242 /* Bus matrix */
20d98c2c
AD		 243 writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a);
244 writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]);
f0a2c7b4
II		 245
246 return 0;
247}
248#endif
249
250static void pm9263_lcd_hw_init(void)
251{
20d98c2c
AD		 252 at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
253
254 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
255 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
256 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
257 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
258 at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
259 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
260 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
261 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
262 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
263 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
264 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
265 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
266 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
267 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
268 at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
269 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
270 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
271 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
272 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
273 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
274 at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
275 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
276 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
277
278 writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer);
f0a2c7b4
II		 279
280 /* Power Control */
20d98c2c
AD		 281 at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
282 at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
f0a2c7b4
II		 283
284#ifdef CONFIG_LCD_IN_PSRAM
285 /* initialize te PSRAM */
286 int stat = pm9263_lcd_hw_psram_init();
287
288 gd->fb_base = (stat == 0) ? PHYS_PSRAM : AT91SAM9263_SRAM0_BASE;
289#else
290 gd->fb_base = AT91SAM9263_SRAM0_BASE;
291#endif
292
293}
294
295#ifdef CONFIG_LCD_INFO
296#include <nand.h>
297#include <version.h>
298
299extern flash_info_t flash_info[];
300
301void lcd_show_board_info(void)
302{
303 ulong dram_size, nand_size, flash_size, dataflash_size;
304 int i;
305 char temp[32];
306
307 lcd_printf ("%s\n", U_BOOT_VERSION);
308 lcd_printf ("(C) 2009 Ronetix GmbH\n");
309 lcd_printf ("support@ronetix.at\n");
310 lcd_printf ("%s CPU at %s MHz",
7c966a8b 311 CONFIG_SYS_AT91_CPU_NAME,
f0a2c7b4
II		 312 strmhz(temp, get_cpu_clk_rate()));
313
314 dram_size = 0;
315 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
316 dram_size += gd->bd->bi_dram[i].size;
317
318 nand_size = 0;
319 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
320 nand_size += nand_info[i].size;
321
322 flash_size = 0;
323 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
324 flash_size += flash_info[i].size;
325
326 dataflash_size = 0;
327 for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
328 dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
329 dataflash_info[i].Device.pages_size;
330
331 lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
332 "4 MB PSRAM, %ld MB DataFlash\n",
333 dram_size >> 20,
334 nand_size >> 20,
335 flash_size >> 20,
336 dataflash_size >> 20);
337}
338#endif /* CONFIG_LCD_INFO */
339
340#endif /* CONFIG_LCD */
341
342int board_init(void)
343{
20d98c2c
AD		 344 at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
345
f0a2c7b4
II		 346 /* Enable Ctrlc */
347 console_init_f();
348
20d98c2c
AD		 349 writel((1 << AT91SAM9263_ID_PIOA) |
350 (1 << AT91SAM9263_ID_PIOCDE) |
351 (1 << AT91SAM9263_ID_PIOB),
352 &pmc->pcer);
f0a2c7b4
II		 353
354 /* arch number of AT91SAM9263EK-Board */
355 gd->bd->bi_arch_number = MACH_TYPE_PM9263;
356
357 /* adress of boot parameters */
358 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
359
360 at91_serial_hw_init();
361#ifdef CONFIG_CMD_NAND
362 pm9263_nand_hw_init();
363#endif
364#ifdef CONFIG_HAS_DATAFLASH
365 at91_spi0_hw_init(1 << 0);
366#endif
367#ifdef CONFIG_MACB
368 pm9263_macb_hw_init();
369#endif
370#ifdef CONFIG_USB_OHCI_NEW
371 at91_uhp_hw_init();
372#endif
373#ifdef CONFIG_LCD
374 pm9263_lcd_hw_init();
375#endif
376 return 0;
377}
378
379int dram_init(void)
380{
381 gd->bd->bi_dram[0].start = PHYS_SDRAM;
382 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
383 return 0;
384}
385
386#ifdef CONFIG_RESET_PHY_R
387void reset_phy(void)
388{
f0a2c7b4
II		 389}
390#endif
391
392int board_eth_init(bd_t *bis)
393{
394 int rc = 0;
395#ifdef CONFIG_MACB
20d98c2c 396 rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x01);
f0a2c7b4
II		 397#endif
398 return rc;
399}
400
401#ifdef CONFIG_DISPLAY_BOARDINFO
402int checkboard (void)
403{
404 char *ss;
f0a2c7b4
II		 405
406 printf ("Board : Ronetix PM9263\n");
f0a2c7b4
II		 407
408 switch (gd->fb_base) {
409 case PHYS_PSRAM:
410 ss = "(PSRAM)";
411 break;
412
413 case AT91SAM9263_SRAM0_BASE:
414 ss = "(Internal SRAM)";
415 break;
416
417 default:
418 ss = "";
419 break;
420 }
421 printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );
422
423 printf ("\n");
424 return 0;
425}
426#endif
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