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1/*
2 * (C) Copyright 2010
3 * Ilko Iliev <iliev@ronetix.at>
4 * Asen Dimov <dimov@ronetix.at>
5 * Ronetix GmbH <www.ronetix.at>
6 *
7 * (C) Copyright 2007-2008
c9e798d3 8 * Stelian Pop <stelian@popies.net>
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9 * Lead Tech Design <www.leadtechdesign.com>
10 *
1a459660 11 * SPDX-License-Identifier: GPL-2.0+
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12 */
13
14#include <common.h>
15#include <asm/sizes.h>
eb6e608b 16#include <asm/io.h>
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17#include <asm/arch/at91sam9_smc.h>
18#include <asm/arch/at91_common.h>
19#include <asm/arch/at91_pmc.h>
20#include <asm/arch/at91_rstc.h>
21#include <asm/arch/at91_matrix.h>
eb6e608b 22#include <asm/arch/gpio.h>
b5d289fc 23#include <asm/arch/clk.h>
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24#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
25#include <net.h>
26#endif
27#include <netdev.h>
28
29DECLARE_GLOBAL_DATA_PTR;
30
31/*
32 * Miscelaneous platform dependent initialisations
33 */
34
35#ifdef CONFIG_CMD_NAND
36static void pm9g45_nand_hw_init(void)
37{
38 unsigned long csa;
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39 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
40 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
41 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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42
43 /* Enable CS3 */
44 csa = readl(&matrix->ccr[6]) | AT91_MATRIX_CSA_EBI_CS3A;
45 writel(csa, &matrix->ccr[6]);
46
47 /* Configure SMC CS3 for NAND/SmartMedia */
48 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
49 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
50 &smc->cs[3].setup);
51
52 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
53 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
54 &smc->cs[3].pulse);
55
56 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
57 &smc->cs[3].cycle);
58
59 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
60 AT91_SMC_MODE_EXNW_DISABLE |
61 AT91_SMC_MODE_DBW_8 |
62 AT91_SMC_MODE_TDF_CYCLE(3),
63 &smc->cs[3].mode);
64
eb6e608b 65 writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
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66
67#ifdef CONFIG_SYS_NAND_READY_PIN
68 /* Configure RDY/BSY */
69 at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
70#endif
71
72 /* Enable NandFlash */
73 at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
74}
75#endif
76
77#ifdef CONFIG_MACB
78static void pm9g45_macb_hw_init(void)
79{
eb6e608b 80 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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81
82 /*
83 * PD2 enables the 50MHz oscillator for Ethernet PHY
84 * 1 - enable
85 * 0 - disable
86 */
87 at91_set_pio_output(AT91_PIO_PORTD, 2, 1);
88 at91_set_pio_value(AT91_PIO_PORTD, 2, 1); /* 1- enable, 0 - disable */
89
90 /* Enable clock */
eb6e608b 91 writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
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92
93 /*
94 * Disable pull-up on:
95 * RXDV (PA15) => PHY normal mode (not Test mode)
96 * ERX0 (PA12) => PHY ADDR0
97 * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
98 *
99 * PHY has internal pull-down
100 */
101 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
102 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0);
103 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0);
104
105 /* Re-enable pull-up */
106 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
107 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
108 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
109
110 at91_macb_hw_init();
111}
112#endif
113
c4df2149 114int board_early_init_f(void)
b5d289fc 115{
eb6e608b 116 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
b5d289fc 117
c4df2149 118 /* Enable clocks for all PIOs */
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119 writel((1 << ATMEL_ID_PIOA) |
120 (1 << ATMEL_ID_PIOB) |
121 (1 << ATMEL_ID_PIOC) |
122 (1 << ATMEL_ID_PIODE), &pmc->pcer);
b5d289fc 123
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124 at91_seriald_hw_init();
125
126 return 0;
127}
128
129int board_init(void)
130{
131 /* arch number of AT91SAM9M10G45EK-Board */
132 gd->bd->bi_arch_number = MACH_TYPE_PM9G45;
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133 /* adress of boot parameters */
134 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
135
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136#ifdef CONFIG_CMD_NAND
137 pm9g45_nand_hw_init();
138#endif
139
140#ifdef CONFIG_MACB
141 pm9g45_macb_hw_init();
142#endif
143 return 0;
144}
145
146int dram_init(void)
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147{
148 /* dram_init must store complete ramsize in gd->ram_size */
a55d23cc 149 gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
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150 PHYS_SDRAM_SIZE);
151 return 0;
152}
153
154void dram_init_banksize(void)
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155{
156 gd->bd->bi_dram[0].start = PHYS_SDRAM;
157 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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158}
159
160#ifdef CONFIG_RESET_PHY_R
161void reset_phy(void)
162{
163#ifdef CONFIG_MACB
164 /*
165 * Initialize ethernet HW addr prior to starting Linux,
166 * needed for nfsroot
167 */
168 eth_init(gd->bd);
169#endif
170}
171#endif
172
173int board_eth_init(bd_t *bis)
174{
175 int rc = 0;
176#ifdef CONFIG_MACB
eb6e608b 177 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
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178#endif
179 return rc;
180}