[thirdparty/u-boot.git] / board / ronetix / pm9g45 / pm9g45.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2010
 * Ilko Iliev <iliev@ronetix.at>
 * Asen Dimov <dimov@ronetix.at>
 * Ronetix GmbH <www.ronetix.at>
 *
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 */

#include <common.h>
#include <init.h>
#include <asm/global_data.h>
#include <linux/sizes.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_matrix.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
#include <netdev.h>
#include <asm/mach-types.h>

DECLARE_GLOBAL_DATA_PTR;

/*
 * Miscelaneous platform dependent initialisations
 */

#ifdef CONFIG_CMD_NAND
static void pm9g45_nand_hw_init(void)
{
	unsigned long csa;
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;

	/* Enable CS3 */
	csa = readl(&matrix->ccr[6]) | AT91_MATRIX_CSA_EBI_CS3A;
	writel(csa, &matrix->ccr[6]);

	/* Configure SMC CS3 for NAND/SmartMedia */
	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
		&smc->cs[3].setup);

	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
		&smc->cs[3].pulse);

	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
		&smc->cs[3].cycle);

	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
		AT91_SMC_MODE_EXNW_DISABLE |
		AT91_SMC_MODE_DBW_8 |
		AT91_SMC_MODE_TDF_CYCLE(3),
		&smc->cs[3].mode);

	at91_periph_clk_enable(ATMEL_ID_PIOC);

#ifdef CFG_SYS_NAND_READY_PIN
	/* Configure RDY/BSY */
	gpio_request(CFG_SYS_NAND_READY_PIN, "NAND RDY/BSY");
	gpio_direction_input(CFG_SYS_NAND_READY_PIN);
#endif

	/* Enable NandFlash */
	gpio_request(CFG_SYS_NAND_ENABLE_PIN, "NAND enable");
	gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#endif

#ifdef CONFIG_MACB
static void pm9g45_macb_hw_init(void)
{
	/*
	 * PD2 enables the 50MHz oscillator for Ethernet PHY
	 * 1 - enable
	 * 0 - disable
	 */
	at91_set_pio_output(AT91_PIO_PORTD, 2, 1);
	at91_set_pio_value(AT91_PIO_PORTD, 2, 1); /* 1- enable, 0 - disable */

	at91_periph_clk_enable(ATMEL_ID_EMAC);

	/*
	 * Disable pull-up on:
	 *	RXDV (PA15) => PHY normal mode (not Test mode)
	 *	ERX0 (PA12) => PHY ADDR0
	 *	ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
	 *
	 * PHY has internal pull-down
	 */
	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
	at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0);
	at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0);

	/* Re-enable pull-up */
	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
	at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
	at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);

	at91_macb_hw_init();
}
#endif

int board_early_init_f(void)
{
	at91_periph_clk_enable(ATMEL_ID_PIOA);
	at91_periph_clk_enable(ATMEL_ID_PIOB);
	at91_periph_clk_enable(ATMEL_ID_PIOC);
	at91_periph_clk_enable(ATMEL_ID_PIODE);

	at91_seriald_hw_init();

	return 0;
}

int board_init(void)
{
	/* arch number of AT91SAM9M10G45EK-Board */
	gd->bd->bi_arch_number = MACH_TYPE_PM9G45;
	/* adress of boot parameters */
	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;

#ifdef CONFIG_CMD_NAND
	pm9g45_nand_hw_init();
#endif

#ifdef CONFIG_MACB
	pm9g45_macb_hw_init();
#endif
	return 0;
}

int dram_init(void)
{
	/* dram_init must store complete ramsize in gd->ram_size */
	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
				    CFG_SYS_SDRAM_SIZE);
	return 0;
}

int dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
	gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE;

	return 0;
}

#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#ifdef CONFIG_MACB
	/*
	 * Initialize ethernet HW addr prior to starting Linux,
	 * needed for nfsroot
	 */
	eth_init();
#endif
}
#endif

int board_eth_init(struct bd_info *bis)
{
	int rc = 0;
#ifdef CONFIG_MACB
	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
#endif
	return rc;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
b5d289fc AD	2	/*
	3	* (C) Copyright 2010
	4	* Ilko Iliev <iliev@ronetix.at>
	5	* Asen Dimov <dimov@ronetix.at>
	6	* Ronetix GmbH <www.ronetix.at>
	7	*
	8	* (C) Copyright 2007-2008
c9e798d3	9	* Stelian Pop <stelian@popies.net>
b5d289fc	10	* Lead Tech Design <www.leadtechdesign.com>
b5d289fc AD	11	*/
b5d289fc AD	12
d678a59d	13	#include <common.h>
9b4a205f	14	#include <init.h>
401d1c4f	15	#include <asm/global_data.h>
1ace4022	16	#include <linux/sizes.h>
eb6e608b	17	#include <asm/io.h>
ac45bb16	18	#include <asm/gpio.h>
b5d289fc AD	19	#include <asm/arch/at91sam9_smc.h>
b5d289fc AD	20	#include <asm/arch/at91_common.h>
b5d289fc AD	21	#include <asm/arch/at91_rstc.h>
b5d289fc AD	22	#include <asm/arch/at91_matrix.h>
eb6e608b	23	#include <asm/arch/gpio.h>
b5d289fc	24	#include <asm/arch/clk.h>
b5d289fc AD	25	#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
	26	#include <net.h>
	27	#endif
	28	#include <netdev.h>
c62db35d	29	#include <asm/mach-types.h>
b5d289fc AD	30
	31	DECLARE_GLOBAL_DATA_PTR;
	32
	33	/*
	34	* Miscelaneous platform dependent initialisations
	35	*/
	36
	37	#ifdef CONFIG_CMD_NAND
	38	static void pm9g45_nand_hw_init(void)
	39	{
	40	unsigned long csa;
eb6e608b AD	41	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC;
eb6e608b AD	42	struct at91_matrix matrix = (struct at91_matrix )ATMEL_BASE_MATRIX;
b5d289fc AD	43
	44	/* Enable CS3 */
	45	csa = readl(&matrix->ccr[6]) \| AT91_MATRIX_CSA_EBI_CS3A;
	46	writel(csa, &matrix->ccr[6]);
	47
	48	/* Configure SMC CS3 for NAND/SmartMedia */
	49	writel(AT91_SMC_SETUP_NWE(1) \| AT91_SMC_SETUP_NCS_WR(0) \|
	50	AT91_SMC_SETUP_NRD(1) \| AT91_SMC_SETUP_NCS_RD(0),
	51	&smc->cs[3].setup);
	52
	53	writel(AT91_SMC_PULSE_NWE(4) \| AT91_SMC_PULSE_NCS_WR(3) \|
	54	AT91_SMC_PULSE_NRD(3) \| AT91_SMC_PULSE_NCS_RD(2),
	55	&smc->cs[3].pulse);
	56
	57	writel(AT91_SMC_CYCLE_NWE(7) \| AT91_SMC_CYCLE_NRD(4),
	58	&smc->cs[3].cycle);
	59
	60	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	61	AT91_SMC_MODE_EXNW_DISABLE \|
	62	AT91_SMC_MODE_DBW_8 \|
	63	AT91_SMC_MODE_TDF_CYCLE(3),
	64	&smc->cs[3].mode);
	65
70341e2e	66	at91_periph_clk_enable(ATMEL_ID_PIOC);
b5d289fc	67
4e590945	68	#ifdef CFG_SYS_NAND_READY_PIN
b5d289fc	69	/* Configure RDY/BSY */
c89982f0	70	gpio_request(CFG_SYS_NAND_READY_PIN, "NAND RDY/BSY");
4e590945	71	gpio_direction_input(CFG_SYS_NAND_READY_PIN);
b5d289fc AD	72	#endif
	73
	74	/* Enable NandFlash */
c89982f0	75	gpio_request(CFG_SYS_NAND_ENABLE_PIN, "NAND enable");
4e590945	76	gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
b5d289fc AD	77	}
	78	#endif
	79
	80	#ifdef CONFIG_MACB
	81	static void pm9g45_macb_hw_init(void)
	82	{
b5d289fc AD	83	/*
	84	* PD2 enables the 50MHz oscillator for Ethernet PHY
	85	* 1 - enable
	86	* 0 - disable
	87	*/
	88	at91_set_pio_output(AT91_PIO_PORTD, 2, 1);
	89	at91_set_pio_value(AT91_PIO_PORTD, 2, 1); /* 1- enable, 0 - disable */
	90
70341e2e	91	at91_periph_clk_enable(ATMEL_ID_EMAC);
b5d289fc AD	92
	93	/*
	94	* Disable pull-up on:
	95	* RXDV (PA15) => PHY normal mode (not Test mode)
	96	* ERX0 (PA12) => PHY ADDR0
	97	* ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
	98	*
	99	* PHY has internal pull-down
	100	*/
	101	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
	102	at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0);
	103	at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0);
	104
	105	/* Re-enable pull-up */
	106	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
	107	at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
	108	at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
	109
	110	at91_macb_hw_init();
	111	}
	112	#endif
	113
c4df2149	114	int board_early_init_f(void)
b5d289fc	115	{
70341e2e WY	116	at91_periph_clk_enable(ATMEL_ID_PIOA);
	117	at91_periph_clk_enable(ATMEL_ID_PIOB);
	118	at91_periph_clk_enable(ATMEL_ID_PIOC);
	119	at91_periph_clk_enable(ATMEL_ID_PIODE);
b5d289fc	120
c4df2149 AD	121	at91_seriald_hw_init();
	122
	123	return 0;
	124	}
	125
	126	int board_init(void)
	127	{
	128	/* arch number of AT91SAM9M10G45EK-Board */
	129	gd->bd->bi_arch_number = MACH_TYPE_PM9G45;
b5d289fc	130	/* adress of boot parameters */
aa6e94de	131	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
b5d289fc	132
b5d289fc AD	133	#ifdef CONFIG_CMD_NAND
	134	pm9g45_nand_hw_init();
	135	#endif
	136
	137	#ifdef CONFIG_MACB
	138	pm9g45_macb_hw_init();
	139	#endif
	140	return 0;
	141	}
	142
	143	int dram_init(void)
510f794c AD	144	{
510f794c AD	145	/* dram_init must store complete ramsize in gd->ram_size */
aa6e94de TR	146	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
aa6e94de TR	147	CFG_SYS_SDRAM_SIZE);
510f794c AD	148	return 0;
	149	}
	150
76b00aca	151	int dram_init_banksize(void)
b5d289fc	152	{
aa6e94de TR	153	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
aa6e94de TR	154	gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE;
76b00aca SG	155
76b00aca SG	156	return 0;
b5d289fc AD	157	}
	158
	159	#ifdef CONFIG_RESET_PHY_R
	160	void reset_phy(void)
	161	{
	162	#ifdef CONFIG_MACB
	163	/*
	164	* Initialize ethernet HW addr prior to starting Linux,
	165	* needed for nfsroot
	166	*/
d2eaec60	167	eth_init();
b5d289fc AD	168	#endif
	169	}
	170	#endif
	171
b75d8dc5	172	int board_eth_init(struct bd_info *bis)
b5d289fc AD	173	{
	174	int rc = 0;
	175	#ifdef CONFIG_MACB
eb6e608b	176	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
b5d289fc AD	177	#endif
	178	return rc;
	179	}