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1 | /* |
2 | * (C) Copyright 2000 | |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <common.h> | |
26 | #include <ioports.h> | |
27 | #include <mpc8260.h> | |
28 | #include <i2c.h> | |
29 | ||
30 | /* define to initialise the SDRAM on the local bus */ | |
31 | #undef INIT_LOCAL_BUS_SDRAM | |
32 | ||
33 | /* I2C Bus adresses for PPC & Protocol board */ | |
34 | #define PPC8260_I2C_ADR 0x30 /*(0)011.0000 */ | |
35 | #define LM84_PPC_I2C_ADR 0x2A /*(0)010.1010 */ | |
36 | #define LM84_SHARC_I2C_ADR 0x29 /*(0)010.1001 */ | |
37 | #define VIRTEX_I2C_ADR 0x25 /*(0)010.0101 */ | |
38 | #define X24645_PPC_I2C_ADR 0x00 /*(0)00X.XXXX -> be careful ! No other i2c-chip should have an adress beginning with (0)00 !!! */ | |
39 | #define RS5C372_PPC_I2C_ADR 0x32 /*(0)011.0010 -> this adress is programmed by the manufacturer and cannot be changed !!! */ | |
40 | ||
41 | /* | |
42 | * I/O Port configuration table | |
43 | * | |
44 | * if conf is 1, then that port pin will be configured at boot time | |
45 | * according to the five values podr/pdir/ppar/psor/pdat for that entry | |
46 | */ | |
47 | ||
48 | const iop_conf_t iop_conf_tab[4][32] = { | |
49 | ||
50 | /* Port A configuration */ | |
51 | { /* conf ppar psor pdir podr pdat */ | |
52 | /* PA31 */ { 0, 0, 0, 0, 0, 0 }, | |
53 | /* PA30 */ { 0, 0, 0, 0, 0, 0 }, | |
54 | /* PA29 */ { 0, 0, 0, 0, 0, 0 }, | |
55 | /* PA28 */ { 0, 0, 0, 0, 0, 0 }, | |
56 | /* PA27 */ { 0, 0, 0, 0, 0, 0 }, | |
57 | /* PA26 */ { 0, 0, 0, 0, 0, 0 }, | |
58 | /* PA25 */ { 0, 0, 0, 0, 0, 0 }, | |
59 | /* PA24 */ { 0, 0, 0, 0, 0, 0 }, | |
60 | /* PA23 */ { 0, 0, 0, 0, 0, 0 }, | |
61 | /* PA22 */ { 0, 0, 0, 0, 0, 0 }, | |
62 | /* PA21 */ { 0, 0, 0, 0, 0, 0 }, | |
63 | /* PA20 */ { 0, 0, 0, 0, 0, 0 }, | |
64 | /* PA19 */ { 0, 0, 0, 0, 0, 0 }, | |
65 | /* PA18 */ { 0, 0, 0, 0, 0, 0 }, | |
66 | /* PA17 */ { 0, 0, 0, 0, 0, 0 }, | |
67 | /* PA16 */ { 0, 0, 0, 0, 0, 0 }, | |
68 | /* PA15 */ { 0, 0, 0, 0, 0, 0 }, | |
69 | /* PA14 */ { 0, 0, 0, 0, 0, 0 }, | |
70 | /* PA13 */ { 0, 0, 0, 0, 0, 0 }, | |
71 | /* PA12 */ { 0, 0, 0, 0, 0, 0 }, | |
72 | /* PA11 */ { 0, 0, 0, 0, 0, 0 }, | |
73 | /* PA10 */ { 0, 0, 0, 0, 0, 0 }, | |
74 | /* PA9 */ { 0, 0, 0, 0, 0, 0 }, | |
75 | /* PA8 */ { 0, 0, 0, 0, 0, 0 }, | |
76 | /* PA7 */ { 0, 0, 0, 0, 0, 0 }, | |
77 | /* PA6 */ { 0, 0, 0, 0, 0, 0 }, | |
78 | /* PA5 */ { 0, 0, 0, 0, 0, 0 }, | |
79 | /* PA4 */ { 0, 0, 0, 0, 0, 0 }, | |
80 | /* PA3 */ { 0, 0, 0, 0, 0, 0 }, | |
81 | /* PA2 */ { 0, 0, 0, 0, 0, 0 }, | |
82 | /* PA1 */ { 0, 0, 0, 0, 0, 0 }, | |
83 | /* PA0 */ { 0, 0, 0, 0, 0, 0 } | |
84 | }, | |
85 | ||
86 | ||
87 | { /* conf ppar psor pdir podr pdat */ | |
88 | /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ | |
89 | /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ | |
90 | /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ | |
91 | /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ | |
92 | /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ | |
93 | /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ | |
94 | /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ | |
95 | /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ | |
96 | /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ | |
97 | /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ | |
98 | /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ | |
99 | /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ | |
100 | /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ | |
101 | /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ | |
102 | /* PB17 */ { 0, 0, 0, 0, 0, 0 }, | |
103 | /* PB16 */ { 0, 0, 0, 0, 0, 0 }, | |
104 | /* PB15 */ { 0, 0, 0, 0, 0, 0 }, | |
105 | /* PB14 */ { 0, 0, 0, 0, 0, 0 }, | |
106 | /* PB13 */ { 0, 0, 0, 0, 0, 0 }, | |
107 | /* PB12 */ { 0, 0, 0, 0, 0, 0 }, | |
108 | /* PB11 */ { 0, 0, 0, 0, 0, 0 }, | |
109 | /* PB10 */ { 0, 0, 0, 0, 0, 0 }, | |
110 | /* PB9 */ { 0, 0, 0, 0, 0, 0 }, | |
111 | /* PB8 */ { 0, 0, 0, 0, 0, 0 }, | |
112 | /* PB7 */ { 0, 0, 0, 0, 0, 0 }, | |
113 | /* PB6 */ { 0, 0, 0, 0, 0, 0 }, | |
114 | /* PB5 */ { 0, 0, 0, 0, 0, 0 }, | |
115 | /* PB4 */ { 0, 0, 0, 0, 0, 0 }, | |
116 | /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
117 | /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
118 | /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
119 | /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ | |
120 | }, | |
121 | ||
122 | ||
123 | { /* conf ppar psor pdir podr pdat */ | |
124 | /* PC31 */ { 0, 0, 0, 0, 0, 0 }, | |
125 | /* PC30 */ { 0, 0, 0, 0, 0, 0 }, | |
126 | /* PC29 */ { 0, 0, 0, 0, 0, 0 }, | |
127 | /* PC28 */ { 0, 0, 0, 0, 0, 0 }, | |
128 | /* PC27 */ { 0, 0, 0, 0, 0, 0 }, | |
129 | /* PC26 */ { 0, 0, 0, 0, 0, 0 }, | |
130 | /* PC25 */ { 0, 0, 0, 0, 0, 0 }, | |
131 | /* PC24 */ { 0, 0, 0, 0, 0, 0 }, | |
132 | /* PC23 */ { 0, 0, 0, 0, 0, 0 }, | |
133 | /* PC22 */ { 0, 0, 0, 0, 0, 0 }, | |
134 | /* PC21 */ { 0, 0, 0, 0, 0, 0 }, | |
135 | /* PC20 */ { 0, 0, 0, 0, 0, 0 }, | |
136 | /* PC19 */ { 1, 1, 0, 0, 0, 0 }, | |
137 | /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* ETHRXCLK: CLK14 */ | |
138 | /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* ETHTXCLK: CLK15 */ | |
139 | /* PC16 */ { 0, 0, 0, 0, 0, 0 }, | |
140 | /* PC15 */ { 0, 0, 0, 0, 0, 0 }, | |
141 | /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART CD/ */ | |
142 | /* PC13 */ { 0, 0, 0, 0, 0, 0 }, | |
143 | /* PC12 */ { 0, 0, 0, 0, 0, 0 }, | |
144 | /* PC11 */ { 0, 0, 0, 0, 0, 0 }, | |
145 | /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* ETHMDC: GP */ | |
146 | /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* ETHMDIO: GP */ | |
147 | /* PC8 */ { 0, 0, 0, 0, 0, 0 }, | |
148 | /* PC7 */ { 0, 0, 0, 0, 0, 0 }, | |
149 | /* PC6 */ { 0, 0, 0, 0, 0, 0 }, | |
150 | /* PC5 */ { 0, 0, 0, 0, 0, 0 }, | |
151 | /* PC4 */ { 0, 0, 0, 0, 0, 0 }, | |
152 | /* PC3 */ { 0, 0, 0, 0, 0, 0 }, | |
153 | /* PC2 */ { 0, 0, 0, 0, 0, 0 }, | |
154 | /* PC1 */ { 0, 0, 0, 0, 0, 0 }, | |
155 | /* PC0 */ { 0, 0, 0, 0, 0, 0 } | |
156 | }, | |
157 | ||
158 | ||
159 | { /* conf ppar psor pdir podr pdat */ | |
160 | /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */ | |
161 | /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */ | |
162 | /* PD29 */ { 0, 0, 0, 0, 0, 0 }, | |
163 | /* PD28 */ { 0, 0, 0, 0, 0, 0 }, | |
164 | /* PD27 */ { 0, 0, 0, 0, 0, 0 }, | |
165 | /* PD26 */ { 0, 0, 0, 0, 0, 0 }, | |
166 | /* PD25 */ { 0, 0, 0, 0, 0, 0 }, | |
167 | /* PD24 */ { 0, 0, 0, 0, 0, 0 }, | |
168 | /* PD23 */ { 0, 0, 0, 0, 0, 0 }, | |
169 | /* PD22 */ { 0, 0, 0, 0, 0, 0 }, | |
170 | /* PD21 */ { 0, 0, 0, 0, 0, 0 }, | |
171 | /* PD20 */ { 0, 0, 0, 0, 0, 0 }, | |
172 | /* PD19 */ { 0, 0, 0, 0, 0, 0 }, | |
173 | /* PD18 */ { 0, 0, 0, 0, 0, 0 }, | |
174 | /* PD17 */ { 0, 0, 0, 0, 0, 0 }, | |
175 | /* PD16 */ { 0, 0, 0, 0, 0, 0 }, | |
176 | /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ | |
177 | /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ | |
178 | /* PD13 */ { 0, 0, 0, 0, 0, 0 }, | |
179 | /* PD12 */ { 0, 0, 0, 0, 0, 0 }, | |
180 | /* PD11 */ { 0, 0, 0, 0, 0, 0 }, | |
181 | /* PD10 */ { 0, 0, 0, 0, 0, 0 }, | |
182 | /* PD9 */ { 0, 0, 0, 0, 0, 0 }, | |
183 | /* PD8 */ { 0, 0, 0, 0, 0, 0 }, | |
184 | /* PD7 */ { 0, 0, 0, 0, 0, 0 }, | |
185 | /* PD6 */ { 0, 0, 0, 0, 0, 0 }, | |
186 | /* PD5 */ { 0, 0, 0, 0, 0, 0 }, | |
187 | /* PD4 */ { 0, 0, 0, 0, 0, 0 }, | |
188 | /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
189 | /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
190 | /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
191 | /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ | |
192 | } | |
193 | }; | |
194 | ||
195 | /* ------------------------------------------------------------------------- */ | |
196 | ||
197 | struct tm { | |
198 | unsigned int tm_sec; | |
199 | unsigned int tm_min; | |
200 | unsigned int tm_hour; | |
201 | unsigned int tm_wday; | |
202 | unsigned int tm_mday; | |
203 | unsigned int tm_mon; | |
204 | unsigned int tm_year; | |
205 | }; | |
206 | ||
207 | void read_RS5C372_time (struct tm *timedate) | |
208 | { | |
209 | unsigned char buffer[8]; | |
210 | ||
211 | #define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10) | |
212 | ||
fd329e6f | 213 | if (! i2c_read (RS5C372_PPC_I2C_ADR, 0, 1, buffer, sizeof (buffer))) { |
fe8c2806 WD |
214 | timedate->tm_sec = BCD_TO_BIN (buffer[0]); |
215 | timedate->tm_min = BCD_TO_BIN (buffer[1]); | |
216 | timedate->tm_hour = BCD_TO_BIN (buffer[2]); | |
217 | timedate->tm_wday = BCD_TO_BIN (buffer[3]); | |
218 | timedate->tm_mday = BCD_TO_BIN (buffer[4]); | |
219 | timedate->tm_mon = BCD_TO_BIN (buffer[5]); | |
220 | timedate->tm_year = BCD_TO_BIN (buffer[6]) + 2000; | |
221 | } else { | |
222 | /*printf("i2c error %02x\n", rc); */ | |
223 | memset (timedate, 0, sizeof (struct tm)); | |
224 | } | |
225 | } | |
226 | ||
227 | /* ------------------------------------------------------------------------- */ | |
228 | ||
229 | int read_LM84_temp (int address) | |
230 | { | |
231 | unsigned char buffer[8]; | |
232 | /*int rc;*/ | |
233 | ||
fd329e6f | 234 | if (! i2c_read (address, 0, 1, buffer, 1)) { |
fe8c2806 WD |
235 | return (int) buffer[0]; |
236 | } else { | |
237 | /*printf("i2c error %02x\n", rc); */ | |
238 | return -42; | |
239 | } | |
240 | } | |
241 | ||
242 | /* ------------------------------------------------------------------------- */ | |
243 | ||
244 | /* | |
245 | * Check Board Identity: | |
246 | */ | |
247 | ||
248 | int checkboard (void) | |
249 | { | |
250 | struct tm timedate; | |
251 | unsigned int ppctemp, prottemp; | |
252 | ||
253 | puts ("Board: Rohde & Schwarz 8260 Protocol Board\n"); | |
254 | ||
255 | /* initialise i2c */ | |
6d0f6bcf | 256 | i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
fe8c2806 WD |
257 | |
258 | read_RS5C372_time (&timedate); | |
259 | printf (" Time: %02d:%02d:%02d\n", | |
260 | timedate.tm_hour, timedate.tm_min, timedate.tm_sec); | |
261 | printf (" Date: %02d-%02d-%04d\n", | |
262 | timedate.tm_mday, timedate.tm_mon, timedate.tm_year); | |
263 | ppctemp = read_LM84_temp (LM84_PPC_I2C_ADR); | |
264 | prottemp = read_LM84_temp (LM84_SHARC_I2C_ADR); | |
265 | printf (" Temp: PPC %d C, Protocol Board %d C\n", | |
266 | ppctemp, prottemp); | |
267 | ||
268 | return 0; | |
269 | } | |
270 | ||
271 | /* ------------------------------------------------------------------------- */ | |
272 | ||
273 | /* | |
274 | * Miscelaneous platform dependent initialisations while still | |
275 | * running in flash | |
276 | */ | |
277 | ||
278 | int misc_init_f (void) | |
279 | { | |
280 | return 0; | |
281 | } | |
282 | ||
283 | /* ------------------------------------------------------------------------- */ | |
284 | ||
9973e3c6 | 285 | phys_size_t initdram (int board_type) |
fe8c2806 | 286 | { |
6d0f6bcf | 287 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
fe8c2806 WD |
288 | volatile memctl8260_t *memctl = &immap->im_memctl; |
289 | ||
290 | #ifdef INIT_LOCAL_BUS_SDRAM | |
291 | volatile uchar *ramaddr8; | |
292 | #endif | |
293 | volatile ulong *ramaddr32; | |
294 | ulong sdmr; | |
295 | int i; | |
296 | ||
297 | /* | |
298 | * Only initialize SDRAM when running from FLASH. | |
299 | * When running from RAM, don't touch it. | |
300 | */ | |
301 | if ((ulong) initdram & 0xff000000) { | |
302 | immap->im_siu_conf.sc_ppc_acr = 0x02; | |
303 | immap->im_siu_conf.sc_ppc_alrh = 0x01267893; | |
304 | immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF; | |
305 | immap->im_siu_conf.sc_lcl_acr = 0x02; | |
306 | immap->im_siu_conf.sc_lcl_alrh = 0x01234567; | |
307 | immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF; | |
308 | /* | |
309 | * Program local/60x bus Transfer Error Status and Control Regs: | |
310 | * Disable parity errors | |
311 | */ | |
312 | immap->im_siu_conf.sc_tescr1 = 0x00040000; | |
313 | immap->im_siu_conf.sc_ltescr1 = 0x00040000; | |
314 | ||
315 | /* | |
316 | * Perform Power-Up Initialisation of SDRAM (see 8260 UM, 10.4.2) | |
317 | * | |
318 | * The appropriate BRx/ORx registers have already | |
319 | * been set when we get here (see cpu_init_f). The | |
6d0f6bcf | 320 | * SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. |
fe8c2806 WD |
321 | */ |
322 | memctl->memc_mptpr = 0x2000; | |
323 | memctl->memc_mar = 0x0200; | |
324 | #ifdef INIT_LOCAL_BUS_SDRAM | |
325 | /* initialise local bus ram | |
326 | * | |
327 | * (using the PSRMR_ definitions is NOT an error here | |
328 | * - the LSDMR has the same fields as the PSDMR!) | |
329 | */ | |
330 | memctl->memc_lsrt = 0x0b; | |
331 | memctl->memc_lurt = 0x00; | |
332 | ramaddr = (uchar *) PHYS_SDRAM_LOCAL; | |
6d0f6bcf | 333 | sdmr = CONFIG_SYS_LSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI); |
fe8c2806 WD |
334 | memctl->memc_lsdmr = sdmr | PSDMR_OP_PREA; |
335 | *ramaddr = 0xff; | |
336 | for (i = 0; i < 8; i++) { | |
337 | memctl->memc_lsdmr = sdmr | PSDMR_OP_CBRR; | |
338 | *ramaddr = 0xff; | |
339 | } | |
340 | memctl->memc_lsdmr = sdmr | PSDMR_OP_MRW; | |
341 | *ramaddr = 0xff; | |
6d0f6bcf | 342 | memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_NORM; |
fe8c2806 WD |
343 | #endif |
344 | /* initialise 60x bus ram */ | |
345 | memctl->memc_psrt = 0x0b; | |
346 | memctl->memc_purt = 0x08; | |
347 | ramaddr32 = (ulong *) PHYS_SDRAM_60X; | |
6d0f6bcf | 348 | sdmr = CONFIG_SYS_PSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI); |
fe8c2806 WD |
349 | memctl->memc_psdmr = sdmr | PSDMR_OP_PREA; |
350 | ramaddr32[0] = 0x00ff00ff; | |
351 | ramaddr32[1] = 0x00ff00ff; | |
352 | memctl->memc_psdmr = sdmr | PSDMR_OP_CBRR; | |
353 | for (i = 0; i < 8; i++) { | |
354 | ramaddr32[0] = 0x00ff00ff; | |
355 | ramaddr32[1] = 0x00ff00ff; | |
356 | } | |
357 | memctl->memc_psdmr = sdmr | PSDMR_OP_MRW; | |
358 | ramaddr32[0] = 0x00ff00ff; | |
359 | ramaddr32[1] = 0x00ff00ff; | |
360 | memctl->memc_psdmr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; | |
361 | } | |
362 | ||
363 | /* return the size of the 60x bus ram */ | |
364 | return PHYS_SDRAM_60X_SIZE; | |
365 | } | |
366 | ||
367 | /* ------------------------------------------------------------------------- */ | |
368 | ||
369 | /* | |
370 | * Miscelaneous platform dependent initialisations after monitor | |
371 | * has been relocated into ram | |
372 | */ | |
373 | ||
374 | int misc_init_r (void) | |
375 | { | |
376 | printf ("misc_init_r\n"); | |
377 | return (0); | |
378 | } |