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rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / board / sacsng / clkinit.c
CommitLineData
c609719b
WD		 1/*
2 * (C) Copyright 2002
3 * Custom IDEAS, Inc. <www.cideas.com>
4 * Jon Diekema <diekema@cideas.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <ioports.h>
27#include <mpc8260.h>
28#include <asm/cpm_8260.h>
29#include <configs/sacsng.h>
30
31#include "clkinit.h"
32
d87080b7
WD		 33DECLARE_GLOBAL_DATA_PTR;
34
c609719b
WD		 35int Daq64xSampling = 0;
36
37
38void Daq_BRG_Reset(uint brg)
39{
6d0f6bcf 40 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
c609719b
WD		 41 volatile uint *brg_ptr;
42
43 brg_ptr = (uint *)&immr->im_brgc1;
44
45 if (brg >= 5) {
8bde7f77
WD		 46 brg_ptr = (uint *)&immr->im_brgc5;
47 brg -= 4;
c609719b
WD		 48 }
49 brg_ptr += brg;
50 *brg_ptr |= CPM_BRG_RST;
51 *brg_ptr &= ~CPM_BRG_RST;
52}
53
54void Daq_BRG_Disable(uint brg)
55{
6d0f6bcf 56 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
c609719b
WD		 57 volatile uint *brg_ptr;
58
59 brg_ptr = (uint *)&immr->im_brgc1;
60
61 if (brg >= 5) {
8bde7f77
WD		 62 brg_ptr = (uint *)&immr->im_brgc5;
63 brg -= 4;
c609719b
WD		 64 }
65 brg_ptr += brg;
66 *brg_ptr &= ~CPM_BRG_EN;
67}
68
69void Daq_BRG_Enable(uint brg)
70{
6d0f6bcf 71 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
c609719b
WD		 72 volatile uint *brg_ptr;
73
74 brg_ptr = (uint *)&immr->im_brgc1;
75 if (brg >= 5) {
8bde7f77
WD		 76 brg_ptr = (uint *)&immr->im_brgc5;
77 brg -= 4;
c609719b
WD		 78 }
79 brg_ptr += brg;
80 *brg_ptr |= CPM_BRG_EN;
81}
82
83uint Daq_BRG_Get_Div16(uint brg)
84{
6d0f6bcf 85 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
c609719b
WD		 86 uint *brg_ptr;
87
88 brg_ptr = (uint *)&immr->im_brgc1;
89 if (brg >= 5) {
8bde7f77
WD		 90 brg_ptr = (uint *)&immr->im_brgc5;
91 brg -= 4;
c609719b
WD		 92 }
93 brg_ptr += brg;
94
95 if (*brg_ptr & CPM_BRG_DIV16) {
8bde7f77
WD		 96 /* DIV16 active */
97 return (TRUE);
c609719b
WD		 98 }
99 else {
8bde7f77
WD		 100 /* DIV16 inactive */
101 return (FALSE);
c609719b
WD		 102 }
103}
104
105void Daq_BRG_Set_Div16(uint brg, uint div16)
106{
6d0f6bcf 107 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
c609719b
WD		 108 uint *brg_ptr;
109
110 brg_ptr = (uint *)&immr->im_brgc1;
111 if (brg >= 5) {
8bde7f77
WD		 112 brg_ptr = (uint *)&immr->im_brgc5;
113 brg -= 4;
c609719b
WD		 114 }
115 brg_ptr += brg;
116
117 if (div16) {
8bde7f77
WD		 118 /* DIV16 active */
119 *brg_ptr |= CPM_BRG_DIV16;
c609719b
WD		 120 }
121 else {
8bde7f77
WD		 122 /* DIV16 inactive */
123 *brg_ptr &= ~CPM_BRG_DIV16;
c609719b
WD		 124 }
125}
126
127uint Daq_BRG_Get_Count(uint brg)
128{
6d0f6bcf 129 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
c609719b
WD		 130 uint *brg_ptr;
131 uint brg_cnt;
132
133 brg_ptr = (uint *)&immr->im_brgc1;
134 if (brg >= 5) {
8bde7f77
WD		 135 brg_ptr = (uint *)&immr->im_brgc5;
136 brg -= 4;
c609719b
WD		 137 }
138 brg_ptr += brg;
139
140 /* Get the clock divider
141 *
142 * Note: A clock divider of 0 means divide by 1,
143 * therefore we need to add 1 to the count.
144 */
145 brg_cnt = (*brg_ptr & CPM_BRG_CD_MASK) >> CPM_BRG_DIV16_SHIFT;
146 brg_cnt++;
147 if (*brg_ptr & CPM_BRG_DIV16) {
8bde7f77 148 brg_cnt *= 16;
c609719b
WD		 149 }
150
151 return (brg_cnt);
152}
153
154void Daq_BRG_Set_Count(uint brg, uint brg_cnt)
155{
6d0f6bcf 156 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
c609719b
WD		 157 uint *brg_ptr;
158
159 brg_ptr = (uint *)&immr->im_brgc1;
160 if (brg >= 5) {
8bde7f77
WD		 161 brg_ptr = (uint *)&immr->im_brgc5;
162 brg -= 4;
c609719b
WD		 163 }
164 brg_ptr += brg;
165
166 /*
167 * Note: A clock divider of 0 means divide by 1,
168 * therefore we need to subtract 1 from the count.
169 */
170 if (brg_cnt > 4096) {
8bde7f77
WD		 171 /* Prescale = Divide by 16 */
172 *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) |
c609719b
WD		 173 (((brg_cnt / 16) - 1) << CPM_BRG_DIV16_SHIFT);
174 *brg_ptr |= CPM_BRG_DIV16;
175 }
176 else {
8bde7f77
WD		 177 /* Prescale = Divide by 1 */
178 *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) |
c609719b
WD		 179 ((brg_cnt - 1) << CPM_BRG_DIV16_SHIFT);
180 *brg_ptr &= ~CPM_BRG_DIV16;
181 }
182}
183
184uint Daq_BRG_Get_ExtClk(uint brg)
185{
6d0f6bcf 186 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
c609719b
WD		 187 uint *brg_ptr;
188
189 brg_ptr = (uint *)&immr->im_brgc1;
190 if (brg >= 5) {
8bde7f77
WD		 191 brg_ptr = (uint *)&immr->im_brgc5;
192 brg -= 4;
c609719b
WD		 193 }
194 brg_ptr += brg;
195
196 return ((*brg_ptr & CPM_BRG_EXTC_MASK) >> CPM_BRG_EXTC_SHIFT);
197}
198
199char* Daq_BRG_Get_ExtClk_Description(uint brg)
200{
201 uint extc;
202
203 extc = Daq_BRG_Get_ExtClk(brg);
204
205 switch (brg + 1) {
8bde7f77
WD		 206 case 1:
207 case 2:
208 case 5:
209 case 6: {
210 switch (extc) {
211 case 0: {
212 return ("BRG_INT");
213 }
214 case 1: {
215 return ("CLK3");
216 }
217 case 2: {
218 return ("CLK5");
219 }
220 }
221 return ("??1245??");
222 }
223 case 3:
224 case 4:
225 case 7:
226 case 8: {
227 switch (extc) {
228 case 0: {
229 return ("BRG_INT");
230 }
231 case 1: {
232 return ("CLK9");
233 }
234 case 2: {
235 return ("CLK15");
236 }
237 }
238 return ("??3478??");
239 }
c609719b
WD		 240 }
241 return ("??9876??");
242}
243
244void Daq_BRG_Set_ExtClk(uint brg, uint extc)
245{
6d0f6bcf 246 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
c609719b
WD		 247 uint *brg_ptr;
248
249 brg_ptr = (uint *)&immr->im_brgc1;
250 if (brg >= 5) {
8bde7f77
WD		 251 brg_ptr = (uint *)&immr->im_brgc5;
252 brg -= 4;
c609719b
WD		 253 }
254 brg_ptr += brg;
255
256 *brg_ptr = (*brg_ptr & ~CPM_BRG_EXTC_MASK) |
8bde7f77 257 ((extc << CPM_BRG_EXTC_SHIFT) & CPM_BRG_EXTC_MASK);
c609719b
WD		 258}
259
260uint Daq_BRG_Rate(uint brg)
261{
6d0f6bcf 262 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
c609719b
WD		 263 uint *brg_ptr;
264 uint brg_cnt;
265 uint brg_freq = 0;
266
267 brg_ptr = (uint *)&immr->im_brgc1;
268 brg_ptr += brg;
269 if (brg >= 5) {
8bde7f77
WD		 270 brg_ptr = (uint *)&immr->im_brgc5;
271 brg_ptr += (brg - 4);
c609719b
WD		 272 }
273
274 brg_cnt = Daq_BRG_Get_Count(brg);
275
276 switch (Daq_BRG_Get_ExtClk(brg)) {
8bde7f77
WD		 277 case CPM_BRG_EXTC_CLK3:
278 case CPM_BRG_EXTC_CLK5: {
c609719b
WD		 279 brg_freq = brg_cnt;
280 break;
281 }
282 default: {
283 brg_freq = (uint)BRG_INT_CLK / brg_cnt;
284 }
285 }
286 return (brg_freq);
287}
288
289uint Daq_Get_SampleRate(void)
c609719b
WD		 290{
291 /*
292 * Read the BRG's to return the actual sample rate.
293 */
294 return (Daq_BRG_Rate(MCLK_BRG) / (MCLK_DIVISOR * SCLK_DIVISOR));
295}
296
c609719b 297void Daq_Init_Clocks(int sample_rate, int sample_64x)
c609719b 298{
6d0f6bcf 299 volatile ioport_t *iopa = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */);
eb9401e3 300 uint mclk_divisor; /* MCLK divisor */
8bde7f77 301 int flag; /* Interrupt state */
c609719b
WD		 302
303 /* Save off the clocking data */
304 Daq64xSampling = sample_64x;
305
306 /*
307 * Limit the sample rate to some sensible values.
308 */
eb9401e3 309 if (sample_rate > MAX_64x_SAMPLE_RATE) {
8bde7f77 310 sample_rate = MAX_64x_SAMPLE_RATE;
c609719b
WD		 311 }
312 if (sample_rate < MIN_SAMPLE_RATE) {
8bde7f77 313 sample_rate = MIN_SAMPLE_RATE;
c609719b
WD		 314 }
315
316 /*
317 * Initialize the MCLK/SCLK/LRCLK baud rate generators.
318 */
319
320 /* Setup MCLK */
321 Daq_BRG_Set_ExtClk(MCLK_BRG, CPM_BRG_EXTC_BRGCLK);
322
323 /* Setup SCLK */
324# ifdef RUN_SCLK_ON_BRG_INT
8bde7f77 325 Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_BRGCLK);
c609719b 326# else
8bde7f77 327 Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_CLK9);
c609719b
WD		 328# endif
329
330 /* Setup LRCLK */
331# ifdef RUN_LRCLK_ON_BRG_INT
8bde7f77 332 Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_BRGCLK);
c609719b 333# else
8bde7f77 334 Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_CLK5);
c609719b
WD		 335# endif
336
eb9401e3
WD		 337 /*
338 * Dynamically adjust MCLK based on the new sample rate.
339 */
340
341 /* Compute the divisors */
342 mclk_divisor = BRG_INT_CLK / (sample_rate * MCLK_DIVISOR * SCLK_DIVISOR);
343
344 /*
345 * Disable interrupt and save the current state
346 */
347 flag = disable_interrupts();
348
349 /* Setup MCLK */
350 Daq_BRG_Set_Count(MCLK_BRG, mclk_divisor);
351
352 /* Setup SCLK */
353# ifdef RUN_SCLK_ON_BRG_INT
354 Daq_BRG_Set_Count(SCLK_BRG, mclk_divisor * MCLK_DIVISOR);
355# else
356 Daq_BRG_Set_Count(SCLK_BRG, MCLK_DIVISOR);
357# endif
358
359# ifdef RUN_LRCLK_ON_BRG_INT
8bde7f77 360 Daq_BRG_Set_Count(LRCLK_BRG,
eb9401e3
WD		 361 mclk_divisor * MCLK_DIVISOR * SCLK_DIVISOR);
362# else
363 Daq_BRG_Set_Count(LRCLK_BRG, SCLK_DIVISOR);
364# endif
365
366 /*
367 * Restore the Interrupt state
368 */
369 if (flag) {
8bde7f77 370 enable_interrupts();
eb9401e3 371 }
c609719b
WD		 372
373 /* Enable the clock drivers */
374 iopa->pdat &= ~SLRCLK_EN_MASK;
375}
376
377void Daq_Stop_Clocks(void)
378
379{
380#ifdef TIGHTEN_UP_BRG_TIMING
6d0f6bcf 381 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
eb9401e3
WD		 382 register uint mclk_brg; /* MCLK BRG value */
383 register uint sclk_brg; /* SCLK BRG value */
384 register uint lrclk_brg; /* LRCLK BRG value */
385 unsigned long flag; /* Interrupt flags */
c609719b
WD		 386#endif
387
388# ifdef TIGHTEN_UP_BRG_TIMING
8bde7f77
WD		 389 /*
390 * Obtain MCLK BRG reset/disabled value
391 */
c609719b 392# if (MCLK_BRG == 0)
8bde7f77 393 mclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
c609719b
WD		 394# endif
395# if (MCLK_BRG == 1)
8bde7f77 396 mclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
c609719b
WD		 397# endif
398# if (MCLK_BRG == 2)
8bde7f77 399 mclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
c609719b
WD		 400# endif
401# if (MCLK_BRG == 3)
8bde7f77 402 mclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
c609719b
WD		 403# endif
404# if (MCLK_BRG == 4)
8bde7f77 405 mclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
c609719b
WD		 406# endif
407# if (MCLK_BRG == 5)
8bde7f77 408 mclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
c609719b
WD		 409# endif
410# if (MCLK_BRG == 6)
8bde7f77 411 mclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
c609719b
WD		 412# endif
413# if (MCLK_BRG == 7)
8bde7f77 414 mclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
c609719b
WD		 415# endif
416
8bde7f77
WD		 417 /*
418 * Obtain SCLK BRG reset/disabled value
419 */
c609719b 420# if (SCLK_BRG == 0)
8bde7f77 421 sclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
c609719b
WD		 422# endif
423# if (SCLK_BRG == 1)
8bde7f77 424 sclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
c609719b
WD		 425# endif
426# if (SCLK_BRG == 2)
8bde7f77 427 sclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
c609719b
WD		 428# endif
429# if (SCLK_BRG == 3)
8bde7f77 430 sclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
c609719b
WD		 431# endif
432# if (SCLK_BRG == 4)
8bde7f77 433 sclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
c609719b
WD		 434# endif
435# if (SCLK_BRG == 5)
8bde7f77 436 sclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
c609719b
WD		 437# endif
438# if (SCLK_BRG == 6)
8bde7f77 439 sclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
c609719b
WD		 440# endif
441# if (SCLK_BRG == 7)
8bde7f77 442 sclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
c609719b
WD		 443# endif
444
8bde7f77
WD		 445 /*
446 * Obtain LRCLK BRG reset/disabled value
447 */
eb9401e3 448# if (LRCLK_BRG == 0)
8bde7f77 449 lrclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
eb9401e3
WD		 450# endif
451# if (LRCLK_BRG == 1)
8bde7f77 452 lrclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
eb9401e3
WD		 453# endif
454# if (LRCLK_BRG == 2)
8bde7f77 455 lrclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
eb9401e3
WD		 456# endif
457# if (LRCLK_BRG == 3)
8bde7f77 458 lrclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
eb9401e3
WD		 459# endif
460# if (LRCLK_BRG == 4)
8bde7f77 461 lrclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
eb9401e3
WD		 462# endif
463# if (LRCLK_BRG == 5)
8bde7f77 464 lrclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
eb9401e3
WD		 465# endif
466# if (LRCLK_BRG == 6)
8bde7f77 467 lrclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
eb9401e3
WD		 468# endif
469# if (LRCLK_BRG == 7)
8bde7f77 470 lrclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
eb9401e3 471# endif
8bde7f77 472
eb9401e3
WD		 473 /*
474 * Disable interrupt and save the current state
475 */
476 flag = disable_interrupts();
477
8bde7f77
WD		 478 /*
479 * Set reset on MCLK BRG
480 */
eb9401e3 481# if (MCLK_BRG == 0)
8bde7f77 482 *IM_BRGC1 = mclk_brg;
eb9401e3
WD		 483# endif
484# if (MCLK_BRG == 1)
8bde7f77 485 *IM_BRGC2 = mclk_brg;
eb9401e3
WD		 486# endif
487# if (MCLK_BRG == 2)
8bde7f77 488 *IM_BRGC3 = mclk_brg;
eb9401e3
WD		 489# endif
490# if (MCLK_BRG == 3)
8bde7f77 491 *IM_BRGC4 = mclk_brg;
eb9401e3
WD		 492# endif
493# if (MCLK_BRG == 4)
8bde7f77 494 *IM_BRGC5 = mclk_brg;
eb9401e3
WD		 495# endif
496# if (MCLK_BRG == 5)
8bde7f77 497 *IM_BRGC6 = mclk_brg;
eb9401e3
WD		 498# endif
499# if (MCLK_BRG == 6)
8bde7f77 500 *IM_BRGC7 = mclk_brg;
eb9401e3
WD		 501# endif
502# if (MCLK_BRG == 7)
8bde7f77 503 *IM_BRGC8 = mclk_brg;
eb9401e3
WD		 504# endif
505
8bde7f77
WD		 506 /*
507 * Set reset on SCLK BRG
508 */
eb9401e3 509# if (SCLK_BRG == 0)
8bde7f77 510 *IM_BRGC1 = sclk_brg;
eb9401e3
WD		 511# endif
512# if (SCLK_BRG == 1)
8bde7f77 513 *IM_BRGC2 = sclk_brg;
eb9401e3
WD		 514# endif
515# if (SCLK_BRG == 2)
8bde7f77 516 *IM_BRGC3 = sclk_brg;
eb9401e3
WD		 517# endif
518# if (SCLK_BRG == 3)
8bde7f77 519 *IM_BRGC4 = sclk_brg;
eb9401e3
WD		 520# endif
521# if (SCLK_BRG == 4)
8bde7f77 522 *IM_BRGC5 = sclk_brg;
eb9401e3
WD		 523# endif
524# if (SCLK_BRG == 5)
8bde7f77 525 *IM_BRGC6 = sclk_brg;
eb9401e3
WD		 526# endif
527# if (SCLK_BRG == 6)
8bde7f77 528 *IM_BRGC7 = sclk_brg;
eb9401e3
WD		 529# endif
530# if (SCLK_BRG == 7)
8bde7f77 531 *IM_BRGC8 = sclk_brg;
eb9401e3
WD		 532# endif
533
8bde7f77
WD		 534 /*
535 * Set reset on LRCLK BRG
536 */
eb9401e3 537# if (LRCLK_BRG == 0)
8bde7f77 538 *IM_BRGC1 = lrclk_brg;
eb9401e3
WD		 539# endif
540# if (LRCLK_BRG == 1)
8bde7f77 541 *IM_BRGC2 = lrclk_brg;
eb9401e3
WD		 542# endif
543# if (LRCLK_BRG == 2)
8bde7f77 544 *IM_BRGC3 = lrclk_brg;
eb9401e3
WD		 545# endif
546# if (LRCLK_BRG == 3)
8bde7f77 547 *IM_BRGC4 = lrclk_brg;
eb9401e3
WD		 548# endif
549# if (LRCLK_BRG == 4)
8bde7f77 550 *IM_BRGC5 = lrclk_brg;
eb9401e3
WD		 551# endif
552# if (LRCLK_BRG == 5)
8bde7f77 553 *IM_BRGC6 = lrclk_brg;
eb9401e3
WD		 554# endif
555# if (LRCLK_BRG == 6)
8bde7f77 556 *IM_BRGC7 = lrclk_brg;
eb9401e3
WD		 557# endif
558# if (LRCLK_BRG == 7)
8bde7f77 559 *IM_BRGC8 = lrclk_brg;
eb9401e3 560# endif
8bde7f77
WD		 561
562 /*
563 * Clear reset on MCLK BRG
564 */
eb9401e3 565# if (MCLK_BRG == 0)
8bde7f77 566 *IM_BRGC1 = mclk_brg & ~CPM_BRG_RST;
eb9401e3
WD		 567# endif
568# if (MCLK_BRG == 1)
8bde7f77 569 *IM_BRGC2 = mclk_brg & ~CPM_BRG_RST;
eb9401e3
WD		 570# endif
571# if (MCLK_BRG == 2)
8bde7f77 572 *IM_BRGC3 = mclk_brg & ~CPM_BRG_RST;
eb9401e3
WD		 573# endif
574# if (MCLK_BRG == 3)
8bde7f77 575 *IM_BRGC4 = mclk_brg & ~CPM_BRG_RST;
eb9401e3
WD		 576# endif
577# if (MCLK_BRG == 4)
8bde7f77 578 *IM_BRGC5 = mclk_brg & ~CPM_BRG_RST;
eb9401e3
WD		 579# endif
580# if (MCLK_BRG == 5)
8bde7f77 581 *IM_BRGC6 = mclk_brg & ~CPM_BRG_RST;
eb9401e3
WD		 582# endif
583# if (MCLK_BRG == 6)
8bde7f77 584 *IM_BRGC7 = mclk_brg & ~CPM_BRG_RST;
eb9401e3
WD		 585# endif
586# if (MCLK_BRG == 7)
8bde7f77 587 *IM_BRGC8 = mclk_brg & ~CPM_BRG_RST;
eb9401e3
WD		 588# endif
589
8bde7f77
WD		 590 /*
591 * Clear reset on SCLK BRG
592 */
eb9401e3 593# if (SCLK_BRG == 0)
8bde7f77 594 *IM_BRGC1 = sclk_brg & ~CPM_BRG_RST;
eb9401e3
WD		 595# endif
596# if (SCLK_BRG == 1)
8bde7f77 597 *IM_BRGC2 = sclk_brg & ~CPM_BRG_RST;
eb9401e3
WD		 598# endif
599# if (SCLK_BRG == 2)
8bde7f77 600 *IM_BRGC3 = sclk_brg & ~CPM_BRG_RST;
eb9401e3
WD		 601# endif
602# if (SCLK_BRG == 3)
8bde7f77 603 *IM_BRGC4 = sclk_brg & ~CPM_BRG_RST;
eb9401e3
WD		 604# endif
605# if (SCLK_BRG == 4)
8bde7f77 606 *IM_BRGC5 = sclk_brg & ~CPM_BRG_RST;
eb9401e3
WD		 607# endif
608# if (SCLK_BRG == 5)
8bde7f77 609 *IM_BRGC6 = sclk_brg & ~CPM_BRG_RST;
eb9401e3
WD		 610# endif
611# if (SCLK_BRG == 6)
8bde7f77 612 *IM_BRGC7 = sclk_brg & ~CPM_BRG_RST;
eb9401e3
WD		 613# endif
614# if (SCLK_BRG == 7)
8bde7f77 615 *IM_BRGC8 = sclk_brg & ~CPM_BRG_RST;
eb9401e3
WD		 616# endif
617
8bde7f77
WD		 618 /*
619 * Clear reset on LRCLK BRG
620 */
c609719b 621# if (LRCLK_BRG == 0)
8bde7f77 622 *IM_BRGC1 = lrclk_brg & ~CPM_BRG_RST;
c609719b
WD		 623# endif
624# if (LRCLK_BRG == 1)
8bde7f77 625 *IM_BRGC2 = lrclk_brg & ~CPM_BRG_RST;
c609719b
WD		 626# endif
627# if (LRCLK_BRG == 2)
8bde7f77 628 *IM_BRGC3 = lrclk_brg & ~CPM_BRG_RST;
c609719b
WD		 629# endif
630# if (LRCLK_BRG == 3)
8bde7f77 631 *IM_BRGC4 = lrclk_brg & ~CPM_BRG_RST;
c609719b
WD		 632# endif
633# if (LRCLK_BRG == 4)
8bde7f77 634 *IM_BRGC5 = lrclk_brg & ~CPM_BRG_RST;
c609719b
WD		 635# endif
636# if (LRCLK_BRG == 5)
8bde7f77 637 *IM_BRGC6 = lrclk_brg & ~CPM_BRG_RST;
c609719b
WD		 638# endif
639# if (LRCLK_BRG == 6)
8bde7f77 640 *IM_BRGC7 = lrclk_brg & ~CPM_BRG_RST;
c609719b
WD		 641# endif
642# if (LRCLK_BRG == 7)
8bde7f77 643 *IM_BRGC8 = lrclk_brg & ~CPM_BRG_RST;
c609719b 644# endif
8bde7f77 645
eb9401e3
WD		 646 /*
647 * Restore the Interrupt state
648 */
649 if (flag) {
8bde7f77 650 enable_interrupts();
eb9401e3 651 }
c609719b 652# else
8bde7f77
WD		 653 /*
654 * Reset the clocks
655 */
656 Daq_BRG_Reset(MCLK_BRG);
657 Daq_BRG_Reset(SCLK_BRG);
658 Daq_BRG_Reset(LRCLK_BRG);
c609719b
WD		 659# endif
660}
661
662void Daq_Start_Clocks(int sample_rate)
663
664{
665#ifdef TIGHTEN_UP_BRG_TIMING
6d0f6bcf 666 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
c609719b 667
eb9401e3
WD		 668 register uint mclk_brg; /* MCLK BRG value */
669 register uint sclk_brg; /* SCLK BRG value */
670 register uint temp_lrclk_brg; /* Temporary LRCLK BRG value */
671 register uint real_lrclk_brg; /* Permanent LRCLK BRG value */
c609719b 672 uint lrclk_brg; /* LRCLK BRG value */
c609719b
WD		 673 unsigned long flags; /* Interrupt flags */
674 uint sclk_cnt; /* SCLK count */
675 uint delay_cnt; /* Delay count */
676#endif
677
678# ifdef TIGHTEN_UP_BRG_TIMING
8bde7f77
WD		 679 /*
680 * Obtain the enabled MCLK BRG value
681 */
c609719b 682# if (MCLK_BRG == 0)
8bde7f77 683 mclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
c609719b
WD		 684# endif
685# if (MCLK_BRG == 1)
8bde7f77 686 mclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
c609719b
WD		 687# endif
688# if (MCLK_BRG == 2)
8bde7f77 689 mclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
c609719b
WD		 690# endif
691# if (MCLK_BRG == 3)
8bde7f77 692 mclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
c609719b
WD		 693# endif
694# if (MCLK_BRG == 4)
8bde7f77 695 mclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
c609719b
WD		 696# endif
697# if (MCLK_BRG == 5)
8bde7f77 698 mclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
c609719b
WD		 699# endif
700# if (MCLK_BRG == 6)
8bde7f77 701 mclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
c609719b
WD		 702# endif
703# if (MCLK_BRG == 7)
8bde7f77 704 mclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
c609719b
WD		 705# endif
706
8bde7f77
WD		 707 /*
708 * Obtain the enabled SCLK BRG value
709 */
c609719b 710# if (SCLK_BRG == 0)
8bde7f77 711 sclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
c609719b
WD		 712# endif
713# if (SCLK_BRG == 1)
8bde7f77 714 sclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
c609719b
WD		 715# endif
716# if (SCLK_BRG == 2)
8bde7f77 717 sclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
c609719b
WD		 718# endif
719# if (SCLK_BRG == 3)
8bde7f77 720 sclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
c609719b
WD		 721# endif
722# if (SCLK_BRG == 4)
8bde7f77 723 sclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
c609719b
WD		 724# endif
725# if (SCLK_BRG == 5)
8bde7f77 726 sclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
c609719b
WD		 727# endif
728# if (SCLK_BRG == 6)
8bde7f77 729 sclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
c609719b
WD		 730# endif
731# if (SCLK_BRG == 7)
8bde7f77 732 sclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
c609719b
WD		 733# endif
734
8bde7f77
WD		 735 /*
736 * Obtain the enabled LRCLK BRG value
737 */
c609719b 738# if (LRCLK_BRG == 0)
8bde7f77 739 lrclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
c609719b
WD		 740# endif
741# if (LRCLK_BRG == 1)
8bde7f77 742 lrclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
c609719b
WD		 743# endif
744# if (LRCLK_BRG == 2)
8bde7f77 745 lrclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
c609719b
WD		 746# endif
747# if (LRCLK_BRG == 3)
8bde7f77 748 lrclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
c609719b
WD		 749# endif
750# if (LRCLK_BRG == 4)
8bde7f77 751 lrclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
c609719b
WD		 752# endif
753# if (LRCLK_BRG == 5)
8bde7f77 754 lrclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
c609719b
WD		 755# endif
756# if (LRCLK_BRG == 6)
8bde7f77 757 lrclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
c609719b
WD		 758# endif
759# if (LRCLK_BRG == 7)
8bde7f77 760 lrclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
c609719b
WD		 761# endif
762
763 /* Save off the real LRCLK value */
764 real_lrclk_brg = lrclk_brg;
765
766 /* Obtain the current SCLK count */
767 sclk_cnt = ((sclk_brg & 0x00001FFE) >> 1) + 1;
768
769 /* Compute the delay as a function of SCLK count */
8bde7f77 770 delay_cnt = ((sclk_cnt / 4) - 2) * 10 + 6;
eb9401e3 771 if (DaqSampleRate == 43402) {
c609719b
WD		 772 delay_cnt++;
773 }
774
8bde7f77 775 /* Clear out the count */
c609719b
WD		 776 temp_lrclk_brg = sclk_brg & ~0x00001FFE;
777
8bde7f77 778 /* Insert the count */
c609719b
WD		 779 temp_lrclk_brg |= ((delay_cnt + (sclk_cnt / 2) - 1) << 1) & 0x00001FFE;
780
eb9401e3
WD		 781 /*
782 * Disable interrupt and save the current state
783 */
784 flag = disable_interrupts();
785
8bde7f77
WD		 786 /*
787 * Enable MCLK BRG
788 */
c609719b 789# if (MCLK_BRG == 0)
8bde7f77 790 *IM_BRGC1 = mclk_brg;
c609719b
WD		 791# endif
792# if (MCLK_BRG == 1)
8bde7f77 793 *IM_BRGC2 = mclk_brg;
c609719b
WD		 794# endif
795# if (MCLK_BRG == 2)
8bde7f77 796 *IM_BRGC3 = mclk_brg;
c609719b
WD		 797# endif
798# if (MCLK_BRG == 3)
8bde7f77 799 *IM_BRGC4 = mclk_brg;
c609719b
WD		 800# endif
801# if (MCLK_BRG == 4)
8bde7f77 802 *IM_BRGC5 = mclk_brg;
c609719b
WD		 803# endif
804# if (MCLK_BRG == 5)
8bde7f77 805 *IM_BRGC6 = mclk_brg;
c609719b
WD		 806# endif
807# if (MCLK_BRG == 6)
8bde7f77 808 *IM_BRGC7 = mclk_brg;
c609719b
WD		 809# endif
810# if (MCLK_BRG == 7)
8bde7f77 811 *IM_BRGC8 = mclk_brg;
c609719b
WD		 812# endif
813
8bde7f77
WD		 814 /*
815 * Enable SCLK BRG
816 */
c609719b 817# if (SCLK_BRG == 0)
8bde7f77 818 *IM_BRGC1 = sclk_brg;
c609719b
WD		 819# endif
820# if (SCLK_BRG == 1)
8bde7f77 821 *IM_BRGC2 = sclk_brg;
c609719b
WD		 822# endif
823# if (SCLK_BRG == 2)
8bde7f77 824 *IM_BRGC3 = sclk_brg;
c609719b
WD		 825# endif
826# if (SCLK_BRG == 3)
8bde7f77 827 *IM_BRGC4 = sclk_brg;
c609719b
WD		 828# endif
829# if (SCLK_BRG == 4)
8bde7f77 830 *IM_BRGC5 = sclk_brg;
c609719b
WD		 831# endif
832# if (SCLK_BRG == 5)
8bde7f77 833 *IM_BRGC6 = sclk_brg;
c609719b
WD		 834# endif
835# if (SCLK_BRG == 6)
8bde7f77 836 *IM_BRGC7 = sclk_brg;
c609719b
WD		 837# endif
838# if (SCLK_BRG == 7)
8bde7f77 839 *IM_BRGC8 = sclk_brg;
c609719b
WD		 840# endif
841
8bde7f77
WD		 842 /*
843 * Enable LRCLK BRG (1st time - temporary)
844 */
c609719b 845# if (LRCLK_BRG == 0)
8bde7f77 846 *IM_BRGC1 = temp_lrclk_brg;
c609719b
WD		 847# endif
848# if (LRCLK_BRG == 1)
8bde7f77 849 *IM_BRGC2 = temp_lrclk_brg;
c609719b
WD		 850# endif
851# if (LRCLK_BRG == 2)
8bde7f77 852 *IM_BRGC3 = temp_lrclk_brg;
c609719b
WD		 853# endif
854# if (LRCLK_BRG == 3)
8bde7f77 855 *IM_BRGC4 = temp_lrclk_brg;
c609719b
WD		 856# endif
857# if (LRCLK_BRG == 4)
8bde7f77 858 *IM_BRGC5 = temp_lrclk_brg;
c609719b
WD		 859# endif
860# if (LRCLK_BRG == 5)
8bde7f77 861 *IM_BRGC6 = temp_lrclk_brg;
c609719b
WD		 862# endif
863# if (LRCLK_BRG == 6)
8bde7f77 864 *IM_BRGC7 = temp_lrclk_brg;
c609719b
WD		 865# endif
866# if (LRCLK_BRG == 7)
8bde7f77 867 *IM_BRGC8 = temp_lrclk_brg;
c609719b 868# endif
8bde7f77
WD		 869
870 /*
871 * Enable LRCLK BRG (2nd time - permanent)
872 */
c609719b 873# if (LRCLK_BRG == 0)
8bde7f77 874 *IM_BRGC1 = real_lrclk_brg;
c609719b
WD		 875# endif
876# if (LRCLK_BRG == 1)
8bde7f77 877 *IM_BRGC2 = real_lrclk_brg;
c609719b
WD		 878# endif
879# if (LRCLK_BRG == 2)
8bde7f77 880 *IM_BRGC3 = real_lrclk_brg;
c609719b
WD		 881# endif
882# if (LRCLK_BRG == 3)
8bde7f77 883 *IM_BRGC4 = real_lrclk_brg;
c609719b
WD		 884# endif
885# if (LRCLK_BRG == 4)
8bde7f77 886 *IM_BRGC5 = real_lrclk_brg;
c609719b
WD		 887# endif
888# if (LRCLK_BRG == 5)
8bde7f77 889 *IM_BRGC6 = real_lrclk_brg;
c609719b
WD		 890# endif
891# if (LRCLK_BRG == 6)
8bde7f77 892 *IM_BRGC7 = real_lrclk_brg;
c609719b
WD		 893# endif
894# if (LRCLK_BRG == 7)
8bde7f77 895 *IM_BRGC8 = real_lrclk_brg;
c609719b 896# endif
eb9401e3
WD		 897
898 /*
899 * Restore the Interrupt state
900 */
901 if (flag) {
902 enable_interrupts();
8bde7f77 903 }
c609719b 904# else
8bde7f77
WD		 905 /*
906 * Enable the clocks
907 */
908 Daq_BRG_Enable(LRCLK_BRG);
909 Daq_BRG_Enable(SCLK_BRG);
910 Daq_BRG_Enable(MCLK_BRG);
c609719b
WD		 911# endif
912}
913
914void Daq_Display_Clocks(void)
915
916{
6d0f6bcf 917 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
c609719b
WD		 918 uint mclk_divisor; /* Detected MCLK divisor */
919 uint sclk_divisor; /* Detected SCLK divisor */
920
921 printf("\nBRG:\n");
922 if (immr->im_brgc4 != 0) {
8bde7f77 923 printf("\tbrgc4\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, MCLK\n",
c609719b
WD		 924 immr->im_brgc4,
925 (uint)&(immr->im_brgc4),
926 Daq_BRG_Get_Count(3),
927 Daq_BRG_Get_ExtClk(3),
928 Daq_BRG_Get_ExtClk_Description(3));
929 }
930 if (immr->im_brgc8 != 0) {
8bde7f77 931 printf("\tbrgc8\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCLK\n",
c609719b
WD		 932 immr->im_brgc8,
933 (uint)&(immr->im_brgc8),
934 Daq_BRG_Get_Count(7),
935 Daq_BRG_Get_ExtClk(7),
936 Daq_BRG_Get_ExtClk_Description(7));
937 }
938 if (immr->im_brgc6 != 0) {
8bde7f77 939 printf("\tbrgc6\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, LRCLK\n",
c609719b
WD		 940 immr->im_brgc6,
941 (uint)&(immr->im_brgc6),
942 Daq_BRG_Get_Count(5),
943 Daq_BRG_Get_ExtClk(5),
944 Daq_BRG_Get_ExtClk_Description(5));
945 }
946 if (immr->im_brgc1 != 0) {
8bde7f77 947 printf("\tbrgc1\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC1\n",
c609719b
WD		 948 immr->im_brgc1,
949 (uint)&(immr->im_brgc1),
950 Daq_BRG_Get_Count(0),
951 Daq_BRG_Get_ExtClk(0),
952 Daq_BRG_Get_ExtClk_Description(0));
953 }
954 if (immr->im_brgc2 != 0) {
8bde7f77 955 printf("\tbrgc2\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC2\n",
c609719b
WD		 956 immr->im_brgc2,
957 (uint)&(immr->im_brgc2),
958 Daq_BRG_Get_Count(1),
959 Daq_BRG_Get_ExtClk(1),
960 Daq_BRG_Get_ExtClk_Description(1));
961 }
962 if (immr->im_brgc3 != 0) {
8bde7f77 963 printf("\tbrgc3\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCC1\n",
c609719b
WD		 964 immr->im_brgc3,
965 (uint)&(immr->im_brgc3),
966 Daq_BRG_Get_Count(2),
967 Daq_BRG_Get_ExtClk(2),
968 Daq_BRG_Get_ExtClk_Description(2));
969 }
970 if (immr->im_brgc5 != 0) {
8bde7f77 971 printf("\tbrgc5\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
c609719b
WD		 972 immr->im_brgc5,
973 (uint)&(immr->im_brgc5),
974 Daq_BRG_Get_Count(4),
975 Daq_BRG_Get_ExtClk(4),
976 Daq_BRG_Get_ExtClk_Description(4));
977 }
978 if (immr->im_brgc7 != 0) {
8bde7f77 979 printf("\tbrgc7\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
c609719b
WD		 980 immr->im_brgc7,
981 (uint)&(immr->im_brgc7),
982 Daq_BRG_Get_Count(6),
983 Daq_BRG_Get_ExtClk(6),
984 Daq_BRG_Get_ExtClk_Description(6));
985 }
986
987# ifdef RUN_SCLK_ON_BRG_INT
8bde7f77 988 mclk_divisor = Daq_BRG_Rate(MCLK_BRG) / Daq_BRG_Rate(SCLK_BRG);
c609719b 989# else
8bde7f77 990 mclk_divisor = Daq_BRG_Get_Count(SCLK_BRG);
c609719b
WD		 991# endif
992# ifdef RUN_LRCLK_ON_BRG_INT
8bde7f77 993 sclk_divisor = Daq_BRG_Rate(SCLK_BRG) / Daq_BRG_Rate(LRCLK_BRG);
c609719b 994# else
8bde7f77 995 sclk_divisor = Daq_BRG_Get_Count(LRCLK_BRG);
c609719b
WD		 996# endif
997
998 printf("\nADC/DAC Clocking (%d/%d):\n", sclk_divisor, mclk_divisor);
999 printf("\tMCLK %8d Hz, or %3dx SCLK, or %3dx LRCLK\n",
1000 Daq_BRG_Rate(MCLK_BRG),
1001 mclk_divisor,
1002 mclk_divisor * sclk_divisor);
1003# ifdef RUN_SCLK_ON_BRG_INT
8bde7f77 1004 printf("\tSCLK %8d Hz, or %3dx LRCLK\n",
c609719b
WD		 1005 Daq_BRG_Rate(SCLK_BRG),
1006 sclk_divisor);
1007# else
8bde7f77 1008 printf("\tSCLK %8d Hz, or %3dx LRCLK\n",
c609719b
WD		 1009 Daq_BRG_Rate(MCLK_BRG) / mclk_divisor,
1010 sclk_divisor);
1011# endif
1012# ifdef RUN_LRCLK_ON_BRG_INT
8bde7f77 1013 printf("\tLRCLK %8d Hz\n",
c609719b
WD		 1014 Daq_BRG_Rate(LRCLK_BRG));
1015# else
1016# ifdef RUN_SCLK_ON_BRG_INT
8bde7f77 1017 printf("\tLRCLK %8d Hz\n",
c609719b
WD		 1018 Daq_BRG_Rate(SCLK_BRG) / sclk_divisor);
1019# else
8bde7f77 1020 printf("\tLRCLK %8d Hz\n",
c609719b
WD		 1021 Daq_BRG_Rate(MCLK_BRG) / (mclk_divisor * sclk_divisor));
1022# endif
1023# endif
1024 printf("\n");
1025}
"Das U-Boot" Source Tree