[people/ms/u-boot.git] / board / samsung / smdkc100 / mem_setup.S

/*
 * Originates from Samsung's u-boot 1.1.6 port to S5PC1xx
 *
 * Copyright (C) 2009 Samsung Electrnoics
 * Inki Dae <inki.dae@samsung.com>
 * Heungjun Kim <riverful.kim@samsung.com>
 * Minkyu Kang <mk7.kang@samsung.com>
 * Kyungmin Park <kyungmin.park@samsung.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <config.h>

	.globl mem_ctrl_asm_init
mem_ctrl_asm_init:
	ldr	r6, =S5PC100_DMC_BASE			@ 0xE6000000

	/* DLL parameter setting */
	ldr	r1, =0x50101000
	str	r1, [r6, #0x018]			@ PHYCONTROL0
	ldr	r1, =0xf4
	str	r1, [r6, #0x01C]			@ PHYCONTROL1
	ldr	r1, =0x0
	str	r1, [r6, #0x020]			@ PHYCONTROL2

	/* DLL on */
	ldr	r1, =0x50101002
	str	r1, [r6, #0x018]			@ PHYCONTROL0

	/* DLL start */
	ldr	r1, =0x50101003
	str	r1, [r6, #0x018]			@ PHYCONTROL0

	/* Force value locking for DLL off */
	str	r1, [r6, #0x018]			@ PHYCONTROL0

	/* DLL off */
	ldr	r1, =0x50101001
	str	r1, [r6, #0x018]			@ PHYCONTROL0

	/* auto refresh off */
	ldr	r1, =0xff001010
	str	r1, [r6, #0x000]			@ CONCONTROL

	/*
	 * Burst Length 4, 2 chips, 32-bit, LPDDR
	 * OFF: dynamic self refresh, force precharge, dynamic power down off
	 */
	ldr	r1, =0x00212100
	str	r1, [r6, #0x004]			@ MEMCONTROL

	/*
	 * Note:
	 * If Bank0 has OneDRAM we place it at 0x2800'0000
	 * So finally Bank1 should address start at at 0x2000'0000
	 */
	mov	r4, #0x0

swap_memory:
	/*
	 * Bank0
	 * 0x30 -> 0x30000000
	 * 0xf8 -> 0x37FFFFFF
	 * [15:12] 0: Linear
	 * [11:8 ] 2: 9 bits
	 * [ 7:4 ] 2: 14 bits
	 * [ 3:0 ] 2: 4 banks
	 */
	ldr	r1, =0x30f80222
	/* if r4 is 1, swap the bank */
	cmp	r4, #0x1
	orreq	r1, r1, #0x08000000
	str	r1, [r6, #0x008]			@ MEMCONFIG0

	/*
	 * Bank1
	 * 0x38 -> 0x38000000
	 * 0xf8 -> 0x3fFFFFFF
	 * [15:12] 0: Linear
	 * [11:8 ] 2: 9 bits
	 * [ 7:4 ] 2: 14 bits
	 * [ 3:0 ] 2: 4 banks
	 */
	ldr	r1, =0x38f80222
	/* if r4 is 1, swap the bank */
	cmp	r4, #0x1
	biceq	r1, r1, #0x08000000
	str	r1, [r6, #0x00c]			@ MEMCONFIG1

	ldr	r1, =0x20000000
	str	r1, [r6, #0x014]			@ PRECHCONFIG

	/*
	 * FIXME: Please verify these values
	 * 7.8us * 166MHz %LE %LONG1294(0x50E)
	 * 7.8us * 133MHz %LE %LONG1038(0x40E),
	 * 7.8us * 100MHz %LE %LONG780(0x30C),
	 * 7.8us * 20MHz  %LE %LONG156(0x9C),
	 * 7.8us * 10MHz  %LE %LONG78(0x4E)
	 */
	ldr	r1, =0x0000050e
	str	r1, [r6, #0x030]			@ TIMINGAREF

	/* 166 MHz */
	ldr	r1, =0x0c233287
	str	r1, [r6, #0x034]			@ TIMINGROW

	/* twtr=3 twr=2 trtp=3 cl=3 wl=3 rl=3 */
	ldr	r1, =0x32330303
	str	r1, [r6, #0x038]			@ TIMINGDATA

	/* tfaw=4 sxsr=0x14 txp=0x14 tcke=3 tmrd=3 */
	ldr	r1, =0x04141433
	str	r1, [r6, #0x03C]			@ TIMINGPOWER

	/* chip0 Deselect */
	ldr	r1, =0x07000000
	str	r1, [r6, #0x010]			@ DIRECTCMD

	/* chip0 PALL */
	ldr	r1, =0x01000000
	str	r1, [r6, #0x010]			@ DIRECTCMD

	/* chip0 REFA */
	ldr	r1, =0x05000000
	str	r1, [r6, #0x010]			@ DIRECTCMD
	/* chip0 REFA */
	str	r1, [r6, #0x010]			@ DIRECTCMD

	/* chip0 MRS, CL%LE %LONG3, BL%LE %LONG4 */
	ldr	r1, =0x00000032
	str	r1, [r6, #0x010]			@ DIRECTCMD

	/* chip1 Deselect */
	ldr	r1, =0x07100000
	str	r1, [r6, #0x010]			@ DIRECTCMD

	/* chip1 PALL */
	ldr	r1, =0x01100000
	str	r1, [r6, #0x010]			@ DIRECTCMD

	/* chip1 REFA */
	ldr	r1, =0x05100000
	str	r1, [r6, #0x010]			@ DIRECTCMD
	/* chip1 REFA */
	str	r1, [r6, #0x010]			@ DIRECTCMD

	/* chip1 MRS, CL%LE %LONG3, BL%LE %LONG4 */
	ldr	r1, =0x00100032
	str	r1, [r6, #0x010]			@ DIRECTCMD

	/* auto refresh on */
	ldr	r1, =0xff002030
	str	r1, [r6, #0x000]			@ CONCONTROL

	/* PwrdnConfig */
	ldr	r1, =0x00100002
	str	r1, [r6, #0x028]			@ PWRDNCONFIG

	/* BL%LE %LONG */
	ldr	r1, =0xff212100
	str	r1, [r6, #0x004]			@ MEMCONTROL


	/* Try to test memory area */
	cmp	r4, #0x1
	beq	1f

	mov	r4, #0x1
	ldr	r1, =0x37ffff00
	str	r4, [r1]
	str	r4, [r1, #0x4]				@ dummy write
	ldr	r0, [r1]
	cmp	r0, r4
	bne	swap_memory

1:
	mov	pc, lr

	.ltorg
Commit	Line	Data
8bc4ee9e MK	1	/*
	2	* Originates from Samsung's u-boot 1.1.6 port to S5PC1xx
	3	*
	4	* Copyright (C) 2009 Samsung Electrnoics
	5	* Inki Dae <inki.dae@samsung.com>
	6	* Heungjun Kim <riverful.kim@samsung.com>
	7	* Minkyu Kang <mk7.kang@samsung.com>
	8	* Kyungmin Park <kyungmin.park@samsung.com>
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
8bc4ee9e MK	11	*/
	12
	13	#include <config.h>
	14
	15	.globl mem_ctrl_asm_init
	16	mem_ctrl_asm_init:
	17	ldr r6, =S5PC100_DMC_BASE @ 0xE6000000
	18
	19	/* DLL parameter setting */
	20	ldr r1, =0x50101000
	21	str r1, [r6, #0x018] @ PHYCONTROL0
	22	ldr r1, =0xf4
	23	str r1, [r6, #0x01C] @ PHYCONTROL1
	24	ldr r1, =0x0
	25	str r1, [r6, #0x020] @ PHYCONTROL2
	26
	27	/* DLL on */
	28	ldr r1, =0x50101002
	29	str r1, [r6, #0x018] @ PHYCONTROL0
	30
	31	/* DLL start */
	32	ldr r1, =0x50101003
	33	str r1, [r6, #0x018] @ PHYCONTROL0
	34
	35	/* Force value locking for DLL off */
	36	str r1, [r6, #0x018] @ PHYCONTROL0
	37
	38	/* DLL off */
	39	ldr r1, =0x50101001
	40	str r1, [r6, #0x018] @ PHYCONTROL0
	41
	42	/* auto refresh off */
	43	ldr r1, =0xff001010
	44	str r1, [r6, #0x000] @ CONCONTROL
	45
	46	/*
	47	* Burst Length 4, 2 chips, 32-bit, LPDDR
	48	* OFF: dynamic self refresh, force precharge, dynamic power down off
	49	*/
	50	ldr r1, =0x00212100
	51	str r1, [r6, #0x004] @ MEMCONTROL
	52
	53	/*
	54	* Note:
	55	* If Bank0 has OneDRAM we place it at 0x2800'0000
	56	* So finally Bank1 should address start at at 0x2000'0000
	57	*/
	58	mov r4, #0x0
	59
	60	swap_memory:
	61	/*
	62	* Bank0
	63	* 0x30 -> 0x30000000
	64	* 0xf8 -> 0x37FFFFFF
	65	* [15:12] 0: Linear
	66	* [11:8 ] 2: 9 bits
	67	* [ 7:4 ] 2: 14 bits
	68	* [ 3:0 ] 2: 4 banks
	69	*/
	70	ldr r1, =0x30f80222
	71	/* if r4 is 1, swap the bank */
	72	cmp r4, #0x1
	73	orreq r1, r1, #0x08000000
	74	str r1, [r6, #0x008] @ MEMCONFIG0
75
76	/*
77	* Bank1
78	* 0x38 -> 0x38000000
79	* 0xf8 -> 0x3fFFFFFF
80	* [15:12] 0: Linear
81	* [11:8 ] 2: 9 bits
82	* [ 7:4 ] 2: 14 bits
83	* [ 3:0 ] 2: 4 banks
84	*/
85	ldr r1, =0x38f80222
86	/* if r4 is 1, swap the bank */
87	cmp r4, #0x1
88	biceq r1, r1, #0x08000000
89	str r1, [r6, #0x00c] @ MEMCONFIG1
90
91	ldr r1, =0x20000000
92	str r1, [r6, #0x014] @ PRECHCONFIG
93
94	/*
95	* FIXME: Please verify these values
96	* 7.8us * 166MHz %LE %LONG1294(0x50E)
97	* 7.8us * 133MHz %LE %LONG1038(0x40E),
98	* 7.8us * 100MHz %LE %LONG780(0x30C),
99	* 7.8us * 20MHz %LE %LONG156(0x9C),
100	* 7.8us * 10MHz %LE %LONG78(0x4E)
101	*/
102	ldr r1, =0x0000050e
103	str r1, [r6, #0x030] @ TIMINGAREF
104
105	/* 166 MHz */
106	ldr r1, =0x0c233287
107	str r1, [r6, #0x034] @ TIMINGROW
108
109	/* twtr=3 twr=2 trtp=3 cl=3 wl=3 rl=3 */
110	ldr r1, =0x32330303
111	str r1, [r6, #0x038] @ TIMINGDATA
112
113	/* tfaw=4 sxsr=0x14 txp=0x14 tcke=3 tmrd=3 */
114	ldr r1, =0x04141433
115	str r1, [r6, #0x03C] @ TIMINGPOWER
116
117	/* chip0 Deselect */
118	ldr r1, =0x07000000
119	str r1, [r6, #0x010] @ DIRECTCMD
120
121	/* chip0 PALL */
122	ldr r1, =0x01000000
123	str r1, [r6, #0x010] @ DIRECTCMD
124
125	/* chip0 REFA */
126	ldr r1, =0x05000000
127	str r1, [r6, #0x010] @ DIRECTCMD
128	/* chip0 REFA */
129	str r1, [r6, #0x010] @ DIRECTCMD
130
131	/* chip0 MRS, CL%LE %LONG3, BL%LE %LONG4 */
132	ldr r1, =0x00000032
133	str r1, [r6, #0x010] @ DIRECTCMD
134
135	/* chip1 Deselect */
136	ldr r1, =0x07100000
137	str r1, [r6, #0x010] @ DIRECTCMD
138
139	/* chip1 PALL */
140	ldr r1, =0x01100000
141	str r1, [r6, #0x010] @ DIRECTCMD
142
143	/* chip1 REFA */
144	ldr r1, =0x05100000
145	str r1, [r6, #0x010] @ DIRECTCMD
146	/* chip1 REFA */
147	str r1, [r6, #0x010] @ DIRECTCMD
148
149	/* chip1 MRS, CL%LE %LONG3, BL%LE %LONG4 */
150	ldr r1, =0x00100032
151	str r1, [r6, #0x010] @ DIRECTCMD
152
153	/* auto refresh on */
154	ldr r1, =0xff002030
155	str r1, [r6, #0x000] @ CONCONTROL
156
157	/* PwrdnConfig */
158	ldr r1, =0x00100002
159	str r1, [r6, #0x028] @ PWRDNCONFIG
160
161	/* BL%LE %LONG */
162	ldr r1, =0xff212100
163	str r1, [r6, #0x004] @ MEMCONTROL
164
165
166	/* Try to test memory area */
167	cmp r4, #0x1
168	beq 1f
169
170	mov r4, #0x1
171	ldr r1, =0x37ffff00
172	str r4, [r1]
173	str r4, [r1, #0x4] @ dummy write
174	ldr r0, [r1]
175	cmp r0, r4
176	bne swap_memory
177
178	1:
179	mov pc, lr
180
181	.ltorg