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c609719b WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | ||
25 | #include <common.h> | |
26 | #include <mpc8260.h> | |
27 | #include <common.h> | |
28 | #include "../common/fpga.h" | |
29 | ||
30 | fpga_t fpga_list[] = { | |
6d0f6bcf JCPV |
31 | {"FIOX", CONFIG_SYS_FIOX_BASE, |
32 | CONFIG_SYS_PD_FIOX_INIT, CONFIG_SYS_PD_FIOX_PROG, CONFIG_SYS_PD_FIOX_DONE} | |
bf9e3b38 | 33 | , |
6d0f6bcf JCPV |
34 | {"FDOHM", CONFIG_SYS_FDOHM_BASE, |
35 | CONFIG_SYS_PD_FDOHM_INIT, CONFIG_SYS_PD_FDOHM_PROG, CONFIG_SYS_PD_FDOHM_DONE} | |
c609719b | 36 | }; |
bf9e3b38 | 37 | int fpga_count = sizeof (fpga_list) / sizeof (fpga_t); |
c609719b WD |
38 | |
39 | ||
bf9e3b38 | 40 | ulong fpga_control (fpga_t * fpga, int cmd) |
c609719b | 41 | { |
6d0f6bcf | 42 | volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
bf9e3b38 WD |
43 | |
44 | switch (cmd) { | |
45 | case FPGA_INIT_IS_HIGH: | |
46 | immr->im_ioport.iop_pdird &= ~fpga->init_mask; /* input */ | |
47 | return (immr->im_ioport.iop_pdatd & fpga->init_mask) ? 1 : 0; | |
48 | ||
49 | case FPGA_INIT_SET_LOW: | |
50 | immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */ | |
51 | immr->im_ioport.iop_pdatd &= ~fpga->init_mask; | |
52 | break; | |
53 | ||
54 | case FPGA_INIT_SET_HIGH: | |
55 | immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */ | |
56 | immr->im_ioport.iop_pdatd |= fpga->init_mask; | |
57 | break; | |
58 | ||
59 | case FPGA_PROG_SET_LOW: | |
60 | immr->im_ioport.iop_pdatd &= ~fpga->prog_mask; | |
61 | break; | |
62 | ||
63 | case FPGA_PROG_SET_HIGH: | |
64 | immr->im_ioport.iop_pdatd |= fpga->prog_mask; | |
65 | break; | |
66 | ||
67 | case FPGA_DONE_IS_HIGH: | |
68 | return (immr->im_ioport.iop_pdatd & fpga->done_mask) ? 1 : 0; | |
69 | ||
70 | case FPGA_READ_MODE: | |
71 | break; | |
72 | ||
73 | case FPGA_LOAD_MODE: | |
74 | break; | |
75 | ||
76 | case FPGA_GET_ID: | |
6d0f6bcf | 77 | if (fpga->conf_base == CONFIG_SYS_FIOX_BASE) { |
bf9e3b38 WD |
78 | ulong ver = |
79 | *(volatile ulong *) (fpga->conf_base + 0x10); | |
80 | return ((ver >> 10) & 0xf) + ((ver >> 2) & 0xf0); | |
6d0f6bcf | 81 | } else if (fpga->conf_base == CONFIG_SYS_FDOHM_BASE) { |
bf9e3b38 WD |
82 | return (*(volatile ushort *) fpga->conf_base) & 0xff; |
83 | } else { | |
84 | return *(volatile ulong *) fpga->conf_base; | |
85 | } | |
86 | ||
87 | case FPGA_INIT_PORTS: | |
88 | immr->im_ioport.iop_ppard &= ~fpga->init_mask; /* INIT I/O */ | |
89 | immr->im_ioport.iop_psord &= ~fpga->init_mask; | |
90 | immr->im_ioport.iop_pdird &= ~fpga->init_mask; | |
91 | ||
92 | immr->im_ioport.iop_ppard &= ~fpga->prog_mask; /* PROG Output */ | |
93 | immr->im_ioport.iop_psord &= ~fpga->prog_mask; | |
94 | immr->im_ioport.iop_pdird |= fpga->prog_mask; | |
95 | ||
96 | immr->im_ioport.iop_ppard &= ~fpga->done_mask; /* DONE Input */ | |
97 | immr->im_ioport.iop_psord &= ~fpga->done_mask; | |
98 | immr->im_ioport.iop_pdird &= ~fpga->done_mask; | |
99 | ||
100 | break; | |
c609719b | 101 | |
c609719b | 102 | } |
bf9e3b38 | 103 | return 0; |
c609719b | 104 | } |