[thirdparty/u-boot.git] / board / siemens / smartweb / smartweb.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * Achim Ehrlich <aehrlich@taskit.de>
 * taskit GmbH <www.taskit.de>
 *
 * (C) Copyright 2012-
 * Markus Hubig <mhubig@imko.de>
 * IMKO GmbH <www.imko.de>
 * (C) Copyright 2014
 * Heiko Schocher <hs@denx.de>
 * DENX Software Engineering GmbH
 */

#include <common.h>
#include <dm.h>
#include <init.h>
#include <net.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91sam9_sdramc.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/atmel_serial.h>
#include <asm/arch/at91_spi.h>
#include <spi.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/gpio.h>
#include <watchdog.h>
# include <net.h>
#ifndef CONFIG_DM_ETH
# include <netdev.h>
#endif
#include <g_dnl.h>

DECLARE_GLOBAL_DATA_PTR;

static void smartweb_request_gpio(void)
{
	gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena");
	gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy");
	gpio_request(AT91_PIN_PA26, "ena PHY");
}

static void smartweb_nand_hw_init(void)
{
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
	unsigned long csa;

	/* Assign CS3 to NAND/SmartMedia Interface */
	csa = readl(&matrix->ebicsa);
	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
	writel(csa, &matrix->ebicsa);

	/* Configure SMC CS3 for NAND/SmartMedia */
	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
		&smc->cs[3].setup);
	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
		&smc->cs[3].pulse);
	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
	       &smc->cs[3].cycle);
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
		AT91_SMC_MODE_TDF_CYCLE(2),
		&smc->cs[3].mode);

	/* Configure RDY/BSY */
	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);

	/* Enable NandFlash */
	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}

static void smartweb_macb_hw_init(void)
{
	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;

	/* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */
	at91_set_gpio_output(AT91_PIN_PA26, 0);

	/*
	 * Disable pull-up on:
	 *	RXDV (PA17) => PHY normal mode (not Test mode)
	 *	ERX0 (PA14) => PHY ADDR0
	 *	ERX1 (PA15) => PHY ADDR1
	 *	ERX2 (PA25) => PHY ADDR2
	 *	ERX3 (PA26) => PHY ADDR3
	 *	ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
	 *
	 * PHY has internal pull-down
	 */
	writel(pin_to_mask(AT91_PIN_PA14) |
		pin_to_mask(AT91_PIN_PA15) |
		pin_to_mask(AT91_PIN_PA17) |
		pin_to_mask(AT91_PIN_PA25) |
		pin_to_mask(AT91_PIN_PA26) |
		pin_to_mask(AT91_PIN_PA28) |
		pin_to_mask(AT91_PIN_PA29),
		&pioa->pudr);

	at91_phy_reset();

	/* Re-enable pull-up */
	writel(pin_to_mask(AT91_PIN_PA14) |
		pin_to_mask(AT91_PIN_PA15) |
		pin_to_mask(AT91_PIN_PA17) |
		pin_to_mask(AT91_PIN_PA25) |
		pin_to_mask(AT91_PIN_PA26) |
		pin_to_mask(AT91_PIN_PA28) |
		pin_to_mask(AT91_PIN_PA29),
		&pioa->puer);

	/* Initialize EMAC=MACB hardware */
	at91_macb_hw_init();
}

#ifdef CONFIG_USB_GADGET_AT91
#include <linux/usb/at91_udc.h>

void at91_udp_hw_init(void)
{
	/* Enable PLLB */
	at91_pllb_clk_enable(get_pllb_init());

	/* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
	at91_periph_clk_enable(ATMEL_ID_UDP);

	at91_system_clk_enable(AT91SAM926x_PMC_UDP);
}

struct at91_udc_data board_udc_data  = {
	.baseaddr = ATMEL_BASE_UDP0,
};
#endif

int board_early_init_f(void)
{
	/* enable this here, as we have SPL without serial support */
	at91_seriald_hw_init();
	smartweb_request_gpio();
	return 0;
}

int board_init(void)
{
	smartweb_request_gpio();
	/* power LED red */
	at91_set_gpio_output(AT91_PIN_PC6, 0);
	at91_set_gpio_output(AT91_PIN_PC7, 1);
	/* alarm LED off */
	at91_set_gpio_output(AT91_PIN_PC8, 0);
	at91_set_gpio_output(AT91_PIN_PC9, 0);
	/* prog LED red */
	at91_set_gpio_output(AT91_PIN_PC10, 0);
	at91_set_gpio_output(AT91_PIN_PC11, 1);

#ifdef CONFIG_USB_GADGET_AT91
	at91_udp_hw_init();
	at91_udc_probe(&board_udc_data);
#endif

	/* Adress of boot parameters */
	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;

	smartweb_nand_hw_init();
	smartweb_macb_hw_init();
	return 0;
}

int dram_init(void)
{
	gd->ram_size = get_ram_size(
		(void *)CFG_SYS_SDRAM_BASE,
		CFG_SYS_SDRAM_SIZE);
	return 0;
}

#ifndef CONFIG_DM_ETH
#ifdef CONFIG_MACB
int board_eth_init(struct bd_info *bis)
{
	return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
}
#endif /* CONFIG_MACB */
#endif

#if defined(CONFIG_SPL_BUILD)
#include <spl.h>
#include <nand.h>
#include <spi_flash.h>

void matrix_init(void)
{
	struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;

	writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE))
			| AT91_MATRIX_SLOT_CYCLE_(0x40),
			&mat->scfg[3]);
}

void at91_spl_board_init(void)
{
	smartweb_request_gpio();
	/* power LED orange */
	at91_set_gpio_output(AT91_PIN_PC6, 1);
	at91_set_gpio_output(AT91_PIN_PC7, 1);
	/* alarm LED orange */
	at91_set_gpio_output(AT91_PIN_PC8, 1);
	at91_set_gpio_output(AT91_PIN_PC9, 1);
	/* prog LED red */
	at91_set_gpio_output(AT91_PIN_PC10, 0);
	at91_set_gpio_output(AT91_PIN_PC11, 1);

	smartweb_nand_hw_init();
	at91_set_gpio_input(AT91_PIN_PA28, 1);
	at91_set_gpio_input(AT91_PIN_PA29, 1);

	/* check if both  button are pressed */
	if (at91_get_gpio_value(AT91_PIN_PA28) == 0 &&
		at91_get_gpio_value(AT91_PIN_PA29) == 0) {
		smartweb_nand_hw_init();
		nand_init();
		spl_nand_erase_one(0, 0);
	}
}

#define SDRAM_BASE_CONF	(AT91_SDRAMC_NC_9 | AT91_SDRAMC_NR_13 \
			 | AT91_SDRAMC_CAS_2 \
			 | AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \
			 | AT91_SDRAMC_TWR_VAL(2) | AT91_SDRAMC_TRC_VAL(7) \
			 | AT91_SDRAMC_TRP_VAL(2) | AT91_SDRAMC_TRCD_VAL(2) \
			 | AT91_SDRAMC_TRAS_VAL(5) | AT91_SDRAMC_TXSR_VAL(8))

void mem_init(void)
{
	struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX;
	struct at91_port *port = (struct at91_port *)ATMEL_BASE_PIOC;
	struct sdramc_reg setting;

	setting.cr = SDRAM_BASE_CONF;
	setting.mdr = AT91_SDRAMC_MD_SDRAM;
	setting.tr = (CFG_SYS_MASTER_CLOCK * 7) / 1000000;

	/*
	 * I write here directly in this register, because this
	 * approach is smaller than calling at91_set_a_periph() in a
	 * for loop. This saved me 96 bytes.
	 */
	writel(0xffff0000, &port->pdr);

	writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC, &ma->ebicsa);
	sdramc_initialize(ATMEL_BASE_CS1, &setting);
}
#endif

int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
{
	g_dnl_set_serialnumber("1");
	return 0;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
3b5df50e HS	2	/*
	3	* (C) Copyright 2007-2008
	4	* Stelian Pop <stelian@popies.net>
	5	* Lead Tech Design <www.leadtechdesign.com>
	6	*
	7	* Achim Ehrlich <aehrlich@taskit.de>
	8	* taskit GmbH <www.taskit.de>
	9	*
	10	* (C) Copyright 2012-
	11	* Markus Hubig <mhubig@imko.de>
	12	* IMKO GmbH <www.imko.de>
	13	* (C) Copyright 2014
	14	* Heiko Schocher <hs@denx.de>
	15	* DENX Software Engineering GmbH
3b5df50e HS	16	*/
3b5df50e HS	17
d678a59d	18	#include <common.h>
13ee7890	19	#include <dm.h>
9b4a205f	20	#include <init.h>
90526e9f	21	#include <net.h>
401d1c4f	22	#include <asm/global_data.h>
3b5df50e HS	23	#include <asm/io.h>
	24	#include <asm/arch/at91sam9_sdramc.h>
	25	#include <asm/arch/at91sam9260_matrix.h>
	26	#include <asm/arch/at91sam9_smc.h>
	27	#include <asm/arch/at91_common.h>
13ee7890	28	#include <asm/arch/atmel_serial.h>
3b5df50e HS	29	#include <asm/arch/at91_spi.h>
3b5df50e HS	30	#include <spi.h>
e8b81eef	31	#include <asm/arch/clk.h>
3b5df50e	32	#include <asm/arch/gpio.h>
13ee7890	33	#include <asm/gpio.h>
3b5df50e	34	#include <watchdog.h>
3b5df50e	35	# include <net.h>
13ee7890	36	#ifndef CONFIG_DM_ETH
3b5df50e HS	37	# include <netdev.h>
3b5df50e HS	38	#endif
e91ead86	39	#include <g_dnl.h>
3b5df50e HS	40
	41	DECLARE_GLOBAL_DATA_PTR;
	42
13ee7890 HS	43	static void smartweb_request_gpio(void)
13ee7890 HS	44	{
4e590945 TR	45	gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena");
4e590945 TR	46	gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy");
13ee7890 HS	47	gpio_request(AT91_PIN_PA26, "ena PHY");
	48	}
	49
3b5df50e HS	50	static void smartweb_nand_hw_init(void)
	51	{
	52	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC;
	53	struct at91_matrix matrix = (struct at91_matrix )ATMEL_BASE_MATRIX;
	54	unsigned long csa;
	55
	56	/* Assign CS3 to NAND/SmartMedia Interface */
	57	csa = readl(&matrix->ebicsa);
	58	csa \|= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
	59	writel(csa, &matrix->ebicsa);
	60
	61	/* Configure SMC CS3 for NAND/SmartMedia */
	62	writel(AT91_SMC_SETUP_NWE(1) \| AT91_SMC_SETUP_NCS_WR(0) \|
	63	AT91_SMC_SETUP_NRD(1) \| AT91_SMC_SETUP_NCS_RD(0),
	64	&smc->cs[3].setup);
	65	writel(AT91_SMC_PULSE_NWE(3) \| AT91_SMC_PULSE_NCS_WR(3) \|
	66	AT91_SMC_PULSE_NRD(3) \| AT91_SMC_PULSE_NCS_RD(3),
	67	&smc->cs[3].pulse);
	68	writel(AT91_SMC_CYCLE_NWE(5) \| AT91_SMC_CYCLE_NRD(5),
	69	&smc->cs[3].cycle);
	70	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	71	AT91_SMC_MODE_TDF_CYCLE(2),
	72	&smc->cs[3].mode);
	73
	74	/* Configure RDY/BSY */
4e590945	75	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
3b5df50e HS	76
3b5df50e HS	77	/* Enable NandFlash */
4e590945	78	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
3b5df50e HS	79	}
3b5df50e HS	80
3b5df50e HS	81	static void smartweb_macb_hw_init(void)
	82	{
	83	struct at91_port pioa = (struct at91_port )ATMEL_BASE_PIOA;
	84
	85	/* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */
	86	at91_set_gpio_output(AT91_PIN_PA26, 0);
	87
	88	/*
	89	* Disable pull-up on:
	90	* RXDV (PA17) => PHY normal mode (not Test mode)
	91	* ERX0 (PA14) => PHY ADDR0
	92	* ERX1 (PA15) => PHY ADDR1
	93	* ERX2 (PA25) => PHY ADDR2
	94	* ERX3 (PA26) => PHY ADDR3
	95	* ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
	96	*
	97	* PHY has internal pull-down
	98	*/
	99	writel(pin_to_mask(AT91_PIN_PA14) \|
	100	pin_to_mask(AT91_PIN_PA15) \|
	101	pin_to_mask(AT91_PIN_PA17) \|
	102	pin_to_mask(AT91_PIN_PA25) \|
	103	pin_to_mask(AT91_PIN_PA26) \|
aca5d083 HS	104	pin_to_mask(AT91_PIN_PA28) \|
aca5d083 HS	105	pin_to_mask(AT91_PIN_PA29),
3b5df50e HS	106	&pioa->pudr);
	107
	108	at91_phy_reset();
	109
	110	/* Re-enable pull-up */
	111	writel(pin_to_mask(AT91_PIN_PA14) \|
	112	pin_to_mask(AT91_PIN_PA15) \|
	113	pin_to_mask(AT91_PIN_PA17) \|
	114	pin_to_mask(AT91_PIN_PA25) \|
	115	pin_to_mask(AT91_PIN_PA26) \|
aca5d083 HS	116	pin_to_mask(AT91_PIN_PA28) \|
aca5d083 HS	117	pin_to_mask(AT91_PIN_PA29),
3b5df50e HS	118	&pioa->puer);
	119
	120	/* Initialize EMAC=MACB hardware */
	121	at91_macb_hw_init();
	122	}
3b5df50e	123
e8b81eef HS	124	#ifdef CONFIG_USB_GADGET_AT91
	125	#include <linux/usb/at91_udc.h>
	126
	127	void at91_udp_hw_init(void)
	128	{
e8b81eef	129	/* Enable PLLB */
30f65c85	130	at91_pllb_clk_enable(get_pllb_init());
e8b81eef HS	131
	132	/* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
	133	at91_periph_clk_enable(ATMEL_ID_UDP);
	134
70341e2e	135	at91_system_clk_enable(AT91SAM926x_PMC_UDP);
e8b81eef HS	136	}
	137
	138	struct at91_udc_data board_udc_data = {
	139	.baseaddr = ATMEL_BASE_UDP0,
	140	};
	141	#endif
	142
3b5df50e HS	143	int board_early_init_f(void)
	144	{
	145	/* enable this here, as we have SPL without serial support */
	146	at91_seriald_hw_init();
13ee7890	147	smartweb_request_gpio();
3b5df50e HS	148	return 0;
	149	}
	150
	151	int board_init(void)
	152	{
13ee7890	153	smartweb_request_gpio();
3b5df50e HS	154	/* power LED red */
	155	at91_set_gpio_output(AT91_PIN_PC6, 0);
	156	at91_set_gpio_output(AT91_PIN_PC7, 1);
	157	/* alarm LED off */
	158	at91_set_gpio_output(AT91_PIN_PC8, 0);
	159	at91_set_gpio_output(AT91_PIN_PC9, 0);
	160	/* prog LED red */
	161	at91_set_gpio_output(AT91_PIN_PC10, 0);
	162	at91_set_gpio_output(AT91_PIN_PC11, 1);
	163
e8b81eef HS	164	#ifdef CONFIG_USB_GADGET_AT91
	165	at91_udp_hw_init();
	166	at91_udc_probe(&board_udc_data);
	167	#endif
	168
aca5d083	169	/* Adress of boot parameters */
aa6e94de	170	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
aca5d083 HS	171
aca5d083 HS	172	smartweb_nand_hw_init();
aca5d083	173	smartweb_macb_hw_init();
3b5df50e HS	174	return 0;
	175	}
	176
	177	int dram_init(void)
	178	{
	179	gd->ram_size = get_ram_size(
aa6e94de TR	180	(void *)CFG_SYS_SDRAM_BASE,
aa6e94de TR	181	CFG_SYS_SDRAM_SIZE);
3b5df50e HS	182	return 0;
	183	}
	184
13ee7890	185	#ifndef CONFIG_DM_ETH
3b5df50e	186	#ifdef CONFIG_MACB
b75d8dc5	187	int board_eth_init(struct bd_info *bis)
3b5df50e HS	188	{
	189	return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
	190	}
	191	#endif /* CONFIG_MACB */
13ee7890	192	#endif
3b5df50e HS	193
	194	#if defined(CONFIG_SPL_BUILD)
	195	#include <spl.h>
	196	#include <nand.h>
	197	#include <spi_flash.h>
	198
	199	void matrix_init(void)
	200	{
	201	struct at91_matrix mat = (struct at91_matrix )ATMEL_BASE_MATRIX;
	202
	203	writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE))
	204	\| AT91_MATRIX_SLOT_CYCLE_(0x40),
	205	&mat->scfg[3]);
	206	}
	207
13ee7890	208	void at91_spl_board_init(void)
3b5df50e	209	{
13ee7890	210	smartweb_request_gpio();
aca5d083	211	/* power LED orange */
3b5df50e HS	212	at91_set_gpio_output(AT91_PIN_PC6, 1);
	213	at91_set_gpio_output(AT91_PIN_PC7, 1);
	214	/* alarm LED orange */
	215	at91_set_gpio_output(AT91_PIN_PC8, 1);
	216	at91_set_gpio_output(AT91_PIN_PC9, 1);
	217	/* prog LED red */
	218	at91_set_gpio_output(AT91_PIN_PC10, 0);
	219	at91_set_gpio_output(AT91_PIN_PC11, 1);
	220
	221	smartweb_nand_hw_init();
	222	at91_set_gpio_input(AT91_PIN_PA28, 1);
	223	at91_set_gpio_input(AT91_PIN_PA29, 1);
	224
	225	/* check if both button are pressed */
	226	if (at91_get_gpio_value(AT91_PIN_PA28) == 0 &&
aca5d083 HS	227	at91_get_gpio_value(AT91_PIN_PA29) == 0) {
aca5d083 HS	228	smartweb_nand_hw_init();
3b5df50e HS	229	nand_init();
	230	spl_nand_erase_one(0, 0);
	231	}
	232	}
	233
	234	#define SDRAM_BASE_CONF (AT91_SDRAMC_NC_9 \| AT91_SDRAMC_NR_13 \
	235	\| AT91_SDRAMC_CAS_2 \
	236	\| AT91_SDRAMC_NB_4 \| AT91_SDRAMC_DBW_32 \
	237	\| AT91_SDRAMC_TWR_VAL(2) \| AT91_SDRAMC_TRC_VAL(7) \
	238	\| AT91_SDRAMC_TRP_VAL(2) \| AT91_SDRAMC_TRCD_VAL(2) \
	239	\| AT91_SDRAMC_TRAS_VAL(5) \| AT91_SDRAMC_TXSR_VAL(8))
	240
	241	void mem_init(void)
	242	{
	243	struct at91_matrix ma = (struct at91_matrix )ATMEL_BASE_MATRIX;
	244	struct at91_port port = (struct at91_port )ATMEL_BASE_PIOC;
	245	struct sdramc_reg setting;
	246
	247	setting.cr = SDRAM_BASE_CONF;
	248	setting.mdr = AT91_SDRAMC_MD_SDRAM;
65cc0e2a	249	setting.tr = (CFG_SYS_MASTER_CLOCK * 7) / 1000000;
3b5df50e HS	250
	251	/*
	252	* I write here directly in this register, because this
	253	* approach is smaller than calling at91_set_a_periph() in a
	254	* for loop. This saved me 96 bytes.
	255	*/
	256	writel(0xffff0000, &port->pdr);
	257
	258	writel(readl(&ma->ebicsa) \| AT91_MATRIX_CS1A_SDRAMC, &ma->ebicsa);
	259	sdramc_initialize(ATMEL_BASE_CS1, &setting);
	260	}
	261	#endif
e91ead86 HS	262
	263	int g_dnl_bind_fixup(struct usb_device_descriptor dev, const char name)
	264	{
	265	g_dnl_set_serialnumber("1");
	266	return 0;
	267	}