[thirdparty/u-boot.git] / board / siemens / taurus / taurus.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Board functions for Siemens TAURUS (AT91SAM9G20) based boards
 * (C) Copyright Siemens AG
 *
 * Based on:
 * U-Boot file: board/atmel/at91sam9260ek/at91sam9260ek.c
 *
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 */

#include <command.h>
#include <common.h>
#include <dm.h>
#include <env.h>
#include <init.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91sam9_sdramc.h>
#include <asm/arch/atmel_serial.h>
#include <asm/arch/clk.h>
#include <asm/gpio.h>
#include <linux/mtd/rawnand.h>
#include <atmel_mci.h>
#include <asm/arch/at91_spi.h>
#include <spi.h>

#include <net.h>
#ifndef CONFIG_DM_ETH
#include <netdev.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

static void taurus_request_gpio(void)
{
	gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena");
	gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy");
	gpio_request(AT91_PIN_PA25, "ena PHY");
}

static void taurus_nand_hw_init(void)
{
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
	unsigned long csa;

	/* Assign CS3 to NAND/SmartMedia Interface */
	csa = readl(&matrix->ebicsa);
	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
	writel(csa, &matrix->ebicsa);

	/* Configure SMC CS3 for NAND/SmartMedia */
	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
	       &smc->cs[3].setup);
	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
	       AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(3),
	       &smc->cs[3].pulse);
	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
	       &smc->cs[3].cycle);
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
	       AT91_SMC_MODE_EXNW_DISABLE |
	       AT91_SMC_MODE_DBW_8 |
	       AT91_SMC_MODE_TDF_CYCLE(3),
	       &smc->cs[3].mode);

	/* Configure RDY/BSY */
	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);

	/* Enable NandFlash */
	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}

#if defined(CONFIG_SPL_BUILD)
#include <spl.h>
#include <nand.h>
#include <spi_flash.h>

void matrix_init(void)
{
	struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;

	writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE))
			| AT91_MATRIX_SLOT_CYCLE_(0x40),
			&mat->scfg[3]);
}

#if defined(CONFIG_BOARD_AXM)
static int at91_is_recovery(void)
{
	if ((at91_get_gpio_value(AT91_PIN_PA26) == 0) &&
	    (at91_get_gpio_value(AT91_PIN_PA27) == 0))
		return 1;

	return 0;
}
#elif defined(CONFIG_BOARD_TAURUS)
static int at91_is_recovery(void)
{
	if (at91_get_gpio_value(AT91_PIN_PA31) == 0)
		return 1;

	return 0;
}
#endif

void spl_board_init(void)
{
	taurus_nand_hw_init();
	at91_spi0_hw_init(TAURUS_SPI_MASK);

#if defined(CONFIG_BOARD_AXM)
	/* Configure LED PINs */
	at91_set_gpio_output(AT91_PIN_PA6, 0);
	at91_set_gpio_output(AT91_PIN_PA8, 0);
	at91_set_gpio_output(AT91_PIN_PA9, 0);
	at91_set_gpio_output(AT91_PIN_PA10, 0);
	at91_set_gpio_output(AT91_PIN_PA11, 0);
	at91_set_gpio_output(AT91_PIN_PA12, 0);

	/* Configure recovery button PINs */
	at91_set_gpio_input(AT91_PIN_PA26, 1);
	at91_set_gpio_input(AT91_PIN_PA27, 1);
#elif defined(CONFIG_BOARD_TAURUS)
	at91_set_gpio_input(AT91_PIN_PA31, 1);
#endif

	/* check for recovery mode */
	if (at91_is_recovery() == 1) {
		struct spi_flash *flash;

		puts("Recovery button pressed\n");
		nand_init();
		spl_nand_erase_one(0, 0);
		flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
					0,
					CONFIG_SF_DEFAULT_SPEED,
					CONFIG_SF_DEFAULT_MODE);
		if (!flash) {
			puts("no flash\n");
		} else {
			puts("erase spi flash sector 0\n");
			spi_flash_erase(flash, 0,
					CFG_SYS_NAND_U_BOOT_SIZE);
		}
	}
}

#define SDRAM_BASE_CONF	(AT91_SDRAMC_NR_13 | AT91_SDRAMC_CAS_3 \
			 |AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \
			 | AT91_SDRAMC_TWR_VAL(3) | AT91_SDRAMC_TRC_VAL(9) \
			 | AT91_SDRAMC_TRP_VAL(3) | AT91_SDRAMC_TRCD_VAL(3) \
			 | AT91_SDRAMC_TRAS_VAL(6) | AT91_SDRAMC_TXSR_VAL(10))

void sdramc_configure(unsigned int mask)
{
	struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX;
	struct sdramc_reg setting;

	at91_sdram_hw_init();
	setting.cr = SDRAM_BASE_CONF | mask;
	setting.mdr = AT91_SDRAMC_MD_SDRAM;
	setting.tr = (CFG_SYS_MASTER_CLOCK * 7) / 1000000;

	writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC |
		AT91_MATRIX_VDDIOMSEL_3_3V | AT91_MATRIX_EBI_IOSR_SEL,
		&ma->ebicsa);

	sdramc_initialize(ATMEL_BASE_CS1, &setting);
}

void mem_init(void)
{
	unsigned int ram_size = 0;

	/* Configure SDRAM for 128MB */
	sdramc_configure(AT91_SDRAMC_NC_10);

	/* Do memtest for 128MB */
	ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
				CFG_SYS_SDRAM_SIZE);

	/*
	 * If 32MB or 16MB should be supported check also for
	 * expected mirroring at A16 and A17
	 * To find mirror addresses depends how the collumns are connected
	 * at RAM (internaly or externaly)
	 * If the collumns are not in inverted order the mirror size effect
	 * behaves like normal SRAM with A0,A1,A2,etc. connected incremantal
	 */

	/* Mirrors at A15 on ATMEL G20 SDRAM Controller with 64MB*/
	if (ram_size == 0x800) {
		printf("\n\r 64MB\n");
		sdramc_configure(AT91_SDRAMC_NC_9);
	} else {
		/* Size already initialized */
		printf("\n\r 128MB\n");
	}
}
#endif

#ifdef CONFIG_MACB
static void siemens_phy_reset(void)
{
	/*
	 * we need to reset PHY for 200us
	 * because of bug in ATMEL G20 CPU (undefined initial state of GPIO)
	 */
	if ((readl(AT91_ASM_RSTC_SR) & AT91_RSTC_RSTTYP) ==
	    AT91_RSTC_RSTTYP_GENERAL)
		at91_set_gpio_value(AT91_PIN_PA25, 0); /* reset eth switch */
}

static void taurus_macb_hw_init(void)
{
	/* Enable EMAC clock */
	at91_periph_clk_enable(ATMEL_ID_EMAC0);

	/*
	 * Disable pull-up on:
	 *	RXDV (PA17) => PHY normal mode (not Test mode)
	 *	ERX0 (PA14) => PHY ADDR0
	 *	ERX1 (PA15) => PHY ADDR1
	 *	ERX2 (PA25) => PHY ADDR2
	 *	ERX3 (PA26) => PHY ADDR3
	 *	ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
	 *
	 * PHY has internal pull-down
	 */
	at91_set_pio_pullup(AT91_PIO_PORTA, 14, 0);
	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
	at91_set_pio_pullup(AT91_PIO_PORTA, 17, 0);
	at91_set_pio_pullup(AT91_PIO_PORTA, 25, 0);
	at91_set_pio_pullup(AT91_PIO_PORTA, 26, 0);
	at91_set_pio_pullup(AT91_PIO_PORTA, 28, 0);

	siemens_phy_reset();

	at91_phy_reset();

	at91_set_gpio_input(AT91_PIN_PA25, 1);   /* ERST tri-state */

	/* Re-enable pull-up */
	at91_set_pio_pullup(AT91_PIO_PORTA, 14, 1);
	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
	at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1);
	at91_set_pio_pullup(AT91_PIO_PORTA, 25, 1);
	at91_set_pio_pullup(AT91_PIO_PORTA, 26, 1);
	at91_set_pio_pullup(AT91_PIO_PORTA, 28, 1);

	/* Initialize EMAC=MACB hardware */
	at91_macb_hw_init();
}
#endif

#ifdef CONFIG_GENERIC_ATMEL_MCI
int board_mmc_init(struct bd_info *bd)
{
	at91_mci_hw_init();

	return atmel_mci_init((void *)ATMEL_BASE_MCI);
}
#endif

int board_early_init_f(void)
{
	/* Enable clocks for all PIOs */
	at91_periph_clk_enable(ATMEL_ID_PIOA);
	at91_periph_clk_enable(ATMEL_ID_PIOB);
	at91_periph_clk_enable(ATMEL_ID_PIOC);

	at91_seriald_hw_init();
	taurus_request_gpio();

	return 0;
}

#ifdef CONFIG_USB_GADGET_AT91
#include <linux/usb/at91_udc.h>

void at91_udp_hw_init(void)
{
	/* Enable PLLB */
	at91_pllb_clk_enable(get_pllb_init());

	/* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
	at91_periph_clk_enable(ATMEL_ID_UDP);

	at91_system_clk_enable(AT91SAM926x_PMC_UDP);
}

struct at91_udc_data board_udc_data  = {
	.baseaddr = ATMEL_BASE_UDP0,
};
#endif

int board_init(void)
{
	/* adress of boot parameters */
	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;

	taurus_request_gpio();
#ifdef CONFIG_CMD_NAND
	taurus_nand_hw_init();
#endif
#ifdef CONFIG_MACB
	taurus_macb_hw_init();
#endif
	at91_spi0_hw_init(TAURUS_SPI_MASK);
#ifdef CONFIG_USB_GADGET_AT91
	at91_udp_hw_init();
	at91_udc_probe(&board_udc_data);
#endif

	return 0;
}

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
				    CFG_SYS_SDRAM_SIZE);
	return 0;
}

#if !defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_BOARD_AXM)
/*
 * Booting the Fallback Image.
 *
 *  The function is used to provide and
 *  boot the image with the fallback
 *  parameters, incase if the faulty image
 *  in upgraded over the base firmware.
 *
 */
static int upgrade_failure_fallback(void)
{
	char *partitionset_active = NULL;
	char *rootfs = NULL;
	char *rootfs_fallback = NULL;
	char *kern_off;
	char *kern_off_fb;
	char *kern_size;
	char *kern_size_fb;

	partitionset_active = env_get("partitionset_active");
	if (partitionset_active) {
		if (partitionset_active[0] == 'A')
			env_set("partitionset_active", "B");
		else
			env_set("partitionset_active", "A");
	} else {
		printf("partitionset_active missing.\n");
		return -ENOENT;
	}

	rootfs = env_get("rootfs");
	rootfs_fallback = env_get("rootfs_fallback");
	env_set("rootfs", rootfs_fallback);
	env_set("rootfs_fallback", rootfs);

	kern_size = env_get("kernel_size");
	kern_size_fb = env_get("kernel_size_fallback");
	env_set("kernel_size", kern_size_fb);
	env_set("kernel_size_fallback", kern_size);

	kern_off = env_get("kernel_Off");
	kern_off_fb = env_get("kernel_Off_fallback");
	env_set("kernel_Off", kern_off_fb);
	env_set("kernel_Off_fallback", kern_off);

	env_set("bootargs", '\0');
	env_set("upgrade_available", '\0');
	env_set("boot_retries", '\0');
	env_save();

	return 0;
}

static int do_upgrade_available(struct cmd_tbl *cmdtp, int flag, int argc,
				char *const argv[])
{
	unsigned long upgrade_available = 0;
	unsigned long boot_retry = 0;
	char boot_buf[10];

	upgrade_available = dectoul(env_get("upgrade_available"), NULL);
	if (upgrade_available) {
		boot_retry = dectoul(env_get("boot_retries"), NULL);
		boot_retry++;
		sprintf(boot_buf, "%lx", boot_retry);
		env_set("boot_retries", boot_buf);
		env_save();

		/*
		 * Here the boot_retries count is checked, and if the
		 * count becomes greater than 2 switch back to the
		 * fallback, and reset the board.
		 */

		if (boot_retry > 2) {
			if (upgrade_failure_fallback() == 0)
				do_reset(NULL, 0, 0, NULL);
			return -1;
		}
	}
	return 0;
}

U_BOOT_CMD(
	upgrade_available,	1,	1,	do_upgrade_available,
	"check Siemens update",
	"no parameters"
);
#endif
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
0f8bc283 HS	2	/*
	3	* Board functions for Siemens TAURUS (AT91SAM9G20) based boards
	4	* (C) Copyright Siemens AG
	5	*
	6	* Based on:
	7	* U-Boot file: board/atmel/at91sam9260ek/at91sam9260ek.c
	8	*
	9	* (C) Copyright 2007-2008
	10	* Stelian Pop <stelian@popies.net>
	11	* Lead Tech Design <www.leadtechdesign.com>
0f8bc283 HS	12	*/
0f8bc283 HS	13
40540823	14	#include <command.h>
d678a59d	15	#include <common.h>
8e6e8221	16	#include <dm.h>
9fb625ce	17	#include <env.h>
9b4a205f	18	#include <init.h>
401d1c4f	19	#include <asm/global_data.h>
0f8bc283 HS	20	#include <asm/io.h>
	21	#include <asm/arch/at91sam9260_matrix.h>
	22	#include <asm/arch/at91sam9_smc.h>
	23	#include <asm/arch/at91_common.h>
0f8bc283 HS	24	#include <asm/arch/at91_rstc.h>
	25	#include <asm/arch/gpio.h>
	26	#include <asm/arch/at91sam9_sdramc.h>
8e6e8221	27	#include <asm/arch/atmel_serial.h>
237e3793	28	#include <asm/arch/clk.h>
8e6e8221	29	#include <asm/gpio.h>
6ae3900a	30	#include <linux/mtd/rawnand.h>
0f8bc283	31	#include <atmel_mci.h>
50921cdc HS	32	#include <asm/arch/at91_spi.h>
50921cdc HS	33	#include <spi.h>
0f8bc283 HS	34
0f8bc283 HS	35	#include <net.h>
8e6e8221	36	#ifndef CONFIG_DM_ETH
0f8bc283	37	#include <netdev.h>
8e6e8221	38	#endif
0f8bc283 HS	39
	40	DECLARE_GLOBAL_DATA_PTR;
	41
8e6e8221 HS	42	static void taurus_request_gpio(void)
8e6e8221 HS	43	{
4e590945 TR	44	gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena");
4e590945 TR	45	gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy");
8e6e8221 HS	46	gpio_request(AT91_PIN_PA25, "ena PHY");
	47	}
	48
0f8bc283 HS	49	static void taurus_nand_hw_init(void)
	50	{
	51	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC;
	52	struct at91_matrix matrix = (struct at91_matrix )ATMEL_BASE_MATRIX;
	53	unsigned long csa;
	54
	55	/* Assign CS3 to NAND/SmartMedia Interface */
	56	csa = readl(&matrix->ebicsa);
	57	csa \|= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
	58	writel(csa, &matrix->ebicsa);
	59
	60	/* Configure SMC CS3 for NAND/SmartMedia */
	61	writel(AT91_SMC_SETUP_NWE(2) \| AT91_SMC_SETUP_NCS_WR(0) \|
	62	AT91_SMC_SETUP_NRD(2) \| AT91_SMC_SETUP_NCS_RD(0),
	63	&smc->cs[3].setup);
	64	writel(AT91_SMC_PULSE_NWE(4) \| AT91_SMC_PULSE_NCS_WR(3) \|
	65	AT91_SMC_PULSE_NRD(4) \| AT91_SMC_PULSE_NCS_RD(3),
	66	&smc->cs[3].pulse);
	67	writel(AT91_SMC_CYCLE_NWE(7) \| AT91_SMC_CYCLE_NRD(7),
	68	&smc->cs[3].cycle);
	69	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	70	AT91_SMC_MODE_EXNW_DISABLE \|
	71	AT91_SMC_MODE_DBW_8 \|
	72	AT91_SMC_MODE_TDF_CYCLE(3),
	73	&smc->cs[3].mode);
	74
	75	/* Configure RDY/BSY */
4e590945	76	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
0f8bc283 HS	77
0f8bc283 HS	78	/* Enable NandFlash */
4e590945	79	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
0f8bc283	80	}
237e3793 HS	81
	82	#if defined(CONFIG_SPL_BUILD)
	83	#include <spl.h>
	84	#include <nand.h>
a1655bb2	85	#include <spi_flash.h>
237e3793 HS	86
	87	void matrix_init(void)
	88	{
	89	struct at91_matrix mat = (struct at91_matrix )ATMEL_BASE_MATRIX;
	90
	91	writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE))
	92	\| AT91_MATRIX_SLOT_CYCLE_(0x40),
	93	&mat->scfg[3]);
	94	}
	95
40540823 HS	96	#if defined(CONFIG_BOARD_AXM)
	97	static int at91_is_recovery(void)
	98	{
	99	if ((at91_get_gpio_value(AT91_PIN_PA26) == 0) &&
	100	(at91_get_gpio_value(AT91_PIN_PA27) == 0))
	101	return 1;
	102
	103	return 0;
	104	}
	105	#elif defined(CONFIG_BOARD_TAURUS)
	106	static int at91_is_recovery(void)
	107	{
	108	if (at91_get_gpio_value(AT91_PIN_PA31) == 0)
	109	return 1;
	110
	111	return 0;
	112	}
	113	#endif
	114
0ed366ff	115	void spl_board_init(void)
237e3793 HS	116	{
237e3793 HS	117	taurus_nand_hw_init();
a1655bb2	118	at91_spi0_hw_init(TAURUS_SPI_MASK);
237e3793	119
40540823 HS	120	#if defined(CONFIG_BOARD_AXM)
	121	/* Configure LED PINs */
	122	at91_set_gpio_output(AT91_PIN_PA6, 0);
	123	at91_set_gpio_output(AT91_PIN_PA8, 0);
	124	at91_set_gpio_output(AT91_PIN_PA9, 0);
	125	at91_set_gpio_output(AT91_PIN_PA10, 0);
	126	at91_set_gpio_output(AT91_PIN_PA11, 0);
	127	at91_set_gpio_output(AT91_PIN_PA12, 0);
	128
237e3793	129	/* Configure recovery button PINs */
40540823 HS	130	at91_set_gpio_input(AT91_PIN_PA26, 1);
	131	at91_set_gpio_input(AT91_PIN_PA27, 1);
	132	#elif defined(CONFIG_BOARD_TAURUS)
237e3793	133	at91_set_gpio_input(AT91_PIN_PA31, 1);
40540823	134	#endif
237e3793	135
40540823 HS	136	/* check for recovery mode */
40540823 HS	137	if (at91_is_recovery() == 1) {
a1655bb2	138	struct spi_flash *flash;
237e3793	139
0ed366ff	140	puts("Recovery button pressed\n");
a1655bb2 HS	141	nand_init();
	142	spl_nand_erase_one(0, 0);
	143	flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
	144	0,
	145	CONFIG_SF_DEFAULT_SPEED,
0ed366ff	146	CONFIG_SF_DEFAULT_MODE);
a1655bb2 HS	147	if (!flash) {
	148	puts("no flash\n");
	149	} else {
	150	puts("erase spi flash sector 0\n");
	151	spi_flash_erase(flash, 0,
4e590945	152	CFG_SYS_NAND_U_BOOT_SIZE);
237e3793 HS	153	}
	154	}
	155	}
	156
40540823 HS	157	#define SDRAM_BASE_CONF (AT91_SDRAMC_NR_13 \| AT91_SDRAMC_CAS_3 \
	158	\|AT91_SDRAMC_NB_4 \| AT91_SDRAMC_DBW_32 \
	159	\| AT91_SDRAMC_TWR_VAL(3) \| AT91_SDRAMC_TRC_VAL(9) \
	160	\| AT91_SDRAMC_TRP_VAL(3) \| AT91_SDRAMC_TRCD_VAL(3) \
	161	\| AT91_SDRAMC_TRAS_VAL(6) \| AT91_SDRAMC_TXSR_VAL(10))
	162
	163	void sdramc_configure(unsigned int mask)
237e3793 HS	164	{
	165	struct at91_matrix ma = (struct at91_matrix )ATMEL_BASE_MATRIX;
	166	struct sdramc_reg setting;
	167
	168	at91_sdram_hw_init();
40540823	169	setting.cr = SDRAM_BASE_CONF \| mask;
237e3793	170	setting.mdr = AT91_SDRAMC_MD_SDRAM;
65cc0e2a	171	setting.tr = (CFG_SYS_MASTER_CLOCK * 7) / 1000000;
237e3793	172
237e3793 HS	173	writel(readl(&ma->ebicsa) \| AT91_MATRIX_CS1A_SDRAMC \|
	174	AT91_MATRIX_VDDIOMSEL_3_3V \| AT91_MATRIX_EBI_IOSR_SEL,
	175	&ma->ebicsa);
40540823	176
237e3793 HS	177	sdramc_initialize(ATMEL_BASE_CS1, &setting);
237e3793 HS	178	}
40540823 HS	179
	180	void mem_init(void)
	181	{
	182	unsigned int ram_size = 0;
	183
	184	/* Configure SDRAM for 128MB */
	185	sdramc_configure(AT91_SDRAMC_NC_10);
	186
	187	/* Do memtest for 128MB */
aa6e94de TR	188	ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
aa6e94de TR	189	CFG_SYS_SDRAM_SIZE);
40540823 HS	190
	191	/*
	192	* If 32MB or 16MB should be supported check also for
	193	* expected mirroring at A16 and A17
	194	* To find mirror addresses depends how the collumns are connected
	195	* at RAM (internaly or externaly)
	196	* If the collumns are not in inverted order the mirror size effect
	197	* behaves like normal SRAM with A0,A1,A2,etc. connected incremantal
	198	*/
	199
	200	/* Mirrors at A15 on ATMEL G20 SDRAM Controller with 64MB*/
	201	if (ram_size == 0x800) {
0cac0fb0	202	printf("\n\r 64MB\n");
40540823 HS	203	sdramc_configure(AT91_SDRAMC_NC_9);
	204	} else {
	205	/* Size already initialized */
0cac0fb0	206	printf("\n\r 128MB\n");
40540823 HS	207	}
40540823 HS	208	}
0f8bc283 HS	209	#endif
	210
	211	#ifdef CONFIG_MACB
40540823 HS	212	static void siemens_phy_reset(void)
	213	{
	214	/*
	215	* we need to reset PHY for 200us
	216	* because of bug in ATMEL G20 CPU (undefined initial state of GPIO)
	217	*/
	218	if ((readl(AT91_ASM_RSTC_SR) & AT91_RSTC_RSTTYP) ==
	219	AT91_RSTC_RSTTYP_GENERAL)
	220	at91_set_gpio_value(AT91_PIN_PA25, 0); /* reset eth switch */
	221	}
	222
0f8bc283 HS	223	static void taurus_macb_hw_init(void)
0f8bc283 HS	224	{
0f8bc283	225	/* Enable EMAC clock */
237e3793	226	at91_periph_clk_enable(ATMEL_ID_EMAC0);
0f8bc283 HS	227
	228	/*
	229	* Disable pull-up on:
	230	* RXDV (PA17) => PHY normal mode (not Test mode)
	231	* ERX0 (PA14) => PHY ADDR0
	232	* ERX1 (PA15) => PHY ADDR1
	233	* ERX2 (PA25) => PHY ADDR2
	234	* ERX3 (PA26) => PHY ADDR3
	235	* ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
	236	*
	237	* PHY has internal pull-down
	238	*/
	239	at91_set_pio_pullup(AT91_PIO_PORTA, 14, 0);
	240	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
	241	at91_set_pio_pullup(AT91_PIO_PORTA, 17, 0);
	242	at91_set_pio_pullup(AT91_PIO_PORTA, 25, 0);
	243	at91_set_pio_pullup(AT91_PIO_PORTA, 26, 0);
	244	at91_set_pio_pullup(AT91_PIO_PORTA, 28, 0);
	245
40540823 HS	246	siemens_phy_reset();
40540823 HS	247
0f8bc283 HS	248	at91_phy_reset();
	249
	250	at91_set_gpio_input(AT91_PIN_PA25, 1); /* ERST tri-state */
	251
	252	/* Re-enable pull-up */
	253	at91_set_pio_pullup(AT91_PIO_PORTA, 14, 1);
	254	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
	255	at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1);
	256	at91_set_pio_pullup(AT91_PIO_PORTA, 25, 1);
	257	at91_set_pio_pullup(AT91_PIO_PORTA, 26, 1);
	258	at91_set_pio_pullup(AT91_PIO_PORTA, 28, 1);
	259
	260	/* Initialize EMAC=MACB hardware */
	261	at91_macb_hw_init();
	262	}
	263	#endif
	264
	265	#ifdef CONFIG_GENERIC_ATMEL_MCI
b75d8dc5	266	int board_mmc_init(struct bd_info *bd)
0f8bc283 HS	267	{
	268	at91_mci_hw_init();
	269
	270	return atmel_mci_init((void *)ATMEL_BASE_MCI);
	271	}
	272	#endif
	273
	274	int board_early_init_f(void)
	275	{
0f8bc283	276	/* Enable clocks for all PIOs */
237e3793 HS	277	at91_periph_clk_enable(ATMEL_ID_PIOA);
	278	at91_periph_clk_enable(ATMEL_ID_PIOB);
	279	at91_periph_clk_enable(ATMEL_ID_PIOC);
	280
	281	at91_seriald_hw_init();
8e6e8221	282	taurus_request_gpio();
0f8bc283 HS	283
	284	return 0;
	285	}
	286
e8b81eef HS	287	#ifdef CONFIG_USB_GADGET_AT91
	288	#include <linux/usb/at91_udc.h>
	289
	290	void at91_udp_hw_init(void)
	291	{
e8b81eef	292	/* Enable PLLB */
30f65c85	293	at91_pllb_clk_enable(get_pllb_init());
e8b81eef HS	294
	295	/* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
	296	at91_periph_clk_enable(ATMEL_ID_UDP);
	297
70341e2e	298	at91_system_clk_enable(AT91SAM926x_PMC_UDP);
e8b81eef HS	299	}
	300
	301	struct at91_udc_data board_udc_data = {
	302	.baseaddr = ATMEL_BASE_UDP0,
	303	};
	304	#endif
	305
0f8bc283 HS	306	int board_init(void)
	307	{
	308	/* adress of boot parameters */
aa6e94de	309	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
0f8bc283	310
8e6e8221	311	taurus_request_gpio();
0f8bc283 HS	312	#ifdef CONFIG_CMD_NAND
	313	taurus_nand_hw_init();
	314	#endif
	315	#ifdef CONFIG_MACB
	316	taurus_macb_hw_init();
	317	#endif
50921cdc	318	at91_spi0_hw_init(TAURUS_SPI_MASK);
e8b81eef HS	319	#ifdef CONFIG_USB_GADGET_AT91
	320	at91_udp_hw_init();
	321	at91_udc_probe(&board_udc_data);
	322	#endif
0f8bc283 HS	323
	324	return 0;
	325	}
	326
	327	int dram_init(void)
	328	{
aa6e94de TR	329	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
aa6e94de TR	330	CFG_SYS_SDRAM_SIZE);
0f8bc283 HS	331	return 0;
	332	}
	333
40540823 HS	334	#if !defined(CONFIG_SPL_BUILD)
	335	#if defined(CONFIG_BOARD_AXM)
	336	/*
	337	* Booting the Fallback Image.
	338	*
	339	* The function is used to provide and
	340	* boot the image with the fallback
	341	* parameters, incase if the faulty image
	342	* in upgraded over the base firmware.
	343	*
	344	*/
	345	static int upgrade_failure_fallback(void)
	346	{
	347	char *partitionset_active = NULL;
	348	char *rootfs = NULL;
	349	char *rootfs_fallback = NULL;
	350	char *kern_off;
	351	char *kern_off_fb;
	352	char *kern_size;
	353	char *kern_size_fb;
	354
00caae6d	355	partitionset_active = env_get("partitionset_active");
40540823 HS	356	if (partitionset_active) {
40540823 HS	357	if (partitionset_active[0] == 'A')
382bee57	358	env_set("partitionset_active", "B");
40540823	359	else
382bee57	360	env_set("partitionset_active", "A");
40540823 HS	361	} else {
	362	printf("partitionset_active missing.\n");
	363	return -ENOENT;
	364	}
	365
00caae6d SG	366	rootfs = env_get("rootfs");
00caae6d SG	367	rootfs_fallback = env_get("rootfs_fallback");
382bee57 SG	368	env_set("rootfs", rootfs_fallback);
382bee57 SG	369	env_set("rootfs_fallback", rootfs);
40540823	370
00caae6d SG	371	kern_size = env_get("kernel_size");
00caae6d SG	372	kern_size_fb = env_get("kernel_size_fallback");
382bee57 SG	373	env_set("kernel_size", kern_size_fb);
382bee57 SG	374	env_set("kernel_size_fallback", kern_size);
40540823	375
00caae6d SG	376	kern_off = env_get("kernel_Off");
00caae6d SG	377	kern_off_fb = env_get("kernel_Off_fallback");
382bee57 SG	378	env_set("kernel_Off", kern_off_fb);
382bee57 SG	379	env_set("kernel_Off_fallback", kern_off);
40540823	380
382bee57 SG	381	env_set("bootargs", '\0');
	382	env_set("upgrade_available", '\0');
	383	env_set("boot_retries", '\0');
01510091	384	env_save();
40540823 HS	385
	386	return 0;
	387	}
	388
09140113 SG	389	static int do_upgrade_available(struct cmd_tbl *cmdtp, int flag, int argc,
09140113 SG	390	char *const argv[])
40540823 HS	391	{
	392	unsigned long upgrade_available = 0;
	393	unsigned long boot_retry = 0;
	394	char boot_buf[10];
	395
0b1284eb	396	upgrade_available = dectoul(env_get("upgrade_available"), NULL);
40540823	397	if (upgrade_available) {
0b1284eb	398	boot_retry = dectoul(env_get("boot_retries"), NULL);
40540823 HS	399	boot_retry++;
40540823 HS	400	sprintf(boot_buf, "%lx", boot_retry);
382bee57	401	env_set("boot_retries", boot_buf);
01510091	402	env_save();
40540823 HS	403
	404	/*
	405	* Here the boot_retries count is checked, and if the
	406	* count becomes greater than 2 switch back to the
	407	* fallback, and reset the board.
	408	*/
	409
	410	if (boot_retry > 2) {
	411	if (upgrade_failure_fallback() == 0)
	412	do_reset(NULL, 0, 0, NULL);
	413	return -1;
	414	}
	415	}
	416	return 0;
	417	}
	418
	419	U_BOOT_CMD(
	420	upgrade_available, 1, 1, do_upgrade_available,
	421	"check Siemens update",
	422	"no parameters"
	423	);
	424	#endif
	425	#endif