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a7c81fc8 SA |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* | |
3 | * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> | |
4 | */ | |
5 | ||
d678a59d | 6 | #include <common.h> |
a7c81fc8 SA |
7 | #include <clk.h> |
8 | #include <dm.h> | |
9 | #include <fdt_support.h> | |
10 | #include <asm/io.h> | |
11 | ||
12 | phys_size_t get_effective_memsize(void) | |
13 | { | |
aa6e94de | 14 | return CFG_SYS_SDRAM_SIZE; |
a7c81fc8 SA |
15 | } |
16 | ||
23058052 | 17 | static int sram_init(void) |
a7c81fc8 SA |
18 | { |
19 | int ret, i; | |
2d64e382 | 20 | const char * const banks[] = { "sram0", "sram1", "aisram" }; |
a7c81fc8 SA |
21 | ofnode memory; |
22 | struct clk clk; | |
23 | ||
24 | /* Enable RAM clocks */ | |
fd426b31 | 25 | memory = ofnode_by_compatible(ofnode_null(), "canaan,k210-sram"); |
a7c81fc8 SA |
26 | if (ofnode_equal(memory, ofnode_null())) |
27 | return -ENOENT; | |
28 | ||
29 | for (i = 0; i < ARRAY_SIZE(banks); i++) { | |
30 | ret = clk_get_by_name_nodev(memory, banks[i], &clk); | |
31 | if (ret) | |
32 | continue; | |
33 | ||
34 | ret = clk_enable(&clk); | |
a7c81fc8 SA |
35 | if (ret) |
36 | return ret; | |
37 | } | |
38 | ||
39 | return 0; | |
40 | } | |
23058052 SA |
41 | |
42 | int board_early_init_f(void) | |
43 | { | |
44 | return sram_init(); | |
45 | } | |
46 | ||
47 | int board_init(void) | |
48 | { | |
49 | return 0; | |
50 | } |