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5d108ac8 SP |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. | |
4 | * | |
5 | * Copyright 2004 Freescale Semiconductor. | |
6 | * (C) Copyright 2002,2003, Motorola Inc. | |
7 | * Xianghua Xiao, (X.Xiao@motorola.com) | |
8 | * | |
9 | * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> | |
10 | * | |
11 | * See file CREDITS for list of people who contributed to this | |
12 | * project. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or | |
15 | * modify it under the terms of the GNU General Public License as | |
16 | * published by the Free Software Foundation; either version 2 of | |
17 | * the License, or (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
27 | * MA 02111-1307 USA | |
28 | */ | |
29 | ||
30 | #include <common.h> | |
31 | #include <pci.h> | |
32 | #include <asm/processor.h> | |
33 | #include <asm/immap_85xx.h> | |
34 | #include <ioports.h> | |
35 | #include <flash.h> | |
e18575d5 SP |
36 | #include <libfdt.h> |
37 | #include <fdt_support.h> | |
e1eb0e25 | 38 | #include <asm/io.h> |
fb661ea4 | 39 | #include <i2c.h> |
40 | #include <mb862xx.h> | |
41 | #include <video_fb.h> | |
59abd15b | 42 | #include "upm_table.h" |
3e79b588 | 43 | |
5d108ac8 SP |
44 | DECLARE_GLOBAL_DATA_PTR; |
45 | ||
46 | extern flash_info_t flash_info[]; /* FLASH chips info */ | |
fb661ea4 | 47 | extern GraphicDevice mb862xx; |
5d108ac8 SP |
48 | |
49 | void local_bus_init (void); | |
50 | ulong flash_get_size (ulong base, int banknum); | |
51 | ||
52 | int checkboard (void) | |
53 | { | |
6d0f6bcf | 54 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
3e79b588 | 55 | |
5e1882df SP |
56 | char *src; |
57 | int f; | |
5d108ac8 SP |
58 | char *s = getenv("serial#"); |
59 | ||
60 | puts("Board: Socrates"); | |
61 | if (s != NULL) { | |
62 | puts(", serial# "); | |
63 | puts(s); | |
64 | } | |
65 | putc('\n'); | |
66 | ||
67 | #ifdef CONFIG_PCI | |
e1eb0e25 AF |
68 | /* Check the PCI_clk sel bit */ |
69 | if (in_be32(&gur->porpllsr) & (1<<15)) { | |
5e1882df SP |
70 | src = "SYSCLK"; |
71 | f = CONFIG_SYS_CLK_FREQ; | |
72 | } else { | |
73 | src = "PCI_CLK"; | |
74 | f = CONFIG_PCI_CLK_FREQ; | |
75 | } | |
76 | printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src); | |
5d108ac8 SP |
77 | #else |
78 | printf ("PCI1: disabled\n"); | |
79 | #endif | |
80 | ||
81 | /* | |
82 | * Initialize local bus. | |
83 | */ | |
84 | local_bus_init (); | |
5d108ac8 SP |
85 | return 0; |
86 | } | |
87 | ||
88 | int misc_init_r (void) | |
89 | { | |
6d0f6bcf | 90 | volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); |
5d108ac8 SP |
91 | |
92 | /* | |
93 | * Adjust flash start and offset to detected values | |
94 | */ | |
95 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; | |
96 | gd->bd->bi_flashoffset = 0; | |
97 | ||
98 | /* | |
99 | * Check if boot FLASH isn't max size | |
100 | */ | |
6d0f6bcf JCPV |
101 | if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) { |
102 | memctl->or0 = gd->bd->bi_flashstart | (CONFIG_SYS_OR0_PRELIM & 0x00007fff); | |
103 | memctl->br0 = gd->bd->bi_flashstart | (CONFIG_SYS_BR0_PRELIM & 0x00007fff); | |
5d108ac8 SP |
104 | |
105 | /* | |
106 | * Re-check to get correct base address | |
107 | */ | |
6d0f6bcf | 108 | flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1); |
5d108ac8 SP |
109 | } |
110 | ||
111 | /* | |
112 | * Check if only one FLASH bank is available | |
113 | */ | |
6d0f6bcf | 114 | if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) { |
5d108ac8 SP |
115 | memctl->or1 = 0; |
116 | memctl->br1 = 0; | |
117 | ||
118 | /* | |
119 | * Re-do flash protection upon new addresses | |
120 | */ | |
121 | flash_protect (FLAG_PROTECT_CLEAR, | |
122 | gd->bd->bi_flashstart, 0xffffffff, | |
6d0f6bcf | 123 | &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); |
5d108ac8 SP |
124 | |
125 | /* Monitor protection ON by default */ | |
126 | flash_protect (FLAG_PROTECT_SET, | |
6d0f6bcf JCPV |
127 | CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, |
128 | &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); | |
5d108ac8 SP |
129 | |
130 | /* Environment protection ON by default */ | |
131 | flash_protect (FLAG_PROTECT_SET, | |
0e8d1586 JCPV |
132 | CONFIG_ENV_ADDR, |
133 | CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, | |
6d0f6bcf | 134 | &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); |
5d108ac8 SP |
135 | |
136 | /* Redundant environment protection ON by default */ | |
137 | flash_protect (FLAG_PROTECT_SET, | |
0e8d1586 JCPV |
138 | CONFIG_ENV_ADDR_REDUND, |
139 | CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1, | |
6d0f6bcf | 140 | &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); |
5d108ac8 SP |
141 | } |
142 | ||
143 | return 0; | |
144 | } | |
145 | ||
146 | /* | |
147 | * Initialize Local Bus | |
148 | */ | |
149 | void local_bus_init (void) | |
150 | { | |
6d0f6bcf JCPV |
151 | volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); |
152 | volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); | |
3e79b588 DZ |
153 | sys_info_t sysinfo; |
154 | uint clkdiv; | |
155 | uint lbc_mhz; | |
6d0f6bcf | 156 | uint lcrr = CONFIG_SYS_LBC_LCRR; |
3e79b588 DZ |
157 | |
158 | get_sys_info (&sysinfo); | |
159 | clkdiv = lbc->lcrr & 0x0f; | |
160 | lbc_mhz = sysinfo.freqSystemBus / 1000000 / clkdiv; | |
161 | ||
162 | /* Disable PLL bypass for Local Bus Clock >= 66 MHz */ | |
163 | if (lbc_mhz >= 66) | |
164 | lcrr &= ~LCRR_DBYP; /* DLL Enabled */ | |
165 | else | |
166 | lcrr |= LCRR_DBYP; /* DLL Bypass */ | |
167 | ||
168 | out_be32 (&lbc->lcrr, lcrr); | |
169 | asm ("sync;isync;msync"); | |
5d108ac8 | 170 | |
3e79b588 DZ |
171 | out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */ |
172 | out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */ | |
173 | out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */ | |
174 | out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */ | |
5d108ac8 | 175 | |
3e79b588 DZ |
176 | /* Init UPMA for FPGA access */ |
177 | out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */ | |
178 | upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int)); | |
e64987a8 | 179 | |
fb661ea4 | 180 | /* Init UPMB for Lime controller access */ |
181 | out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */ | |
182 | upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int)); | |
5d108ac8 SP |
183 | } |
184 | ||
185 | #if defined(CONFIG_PCI) | |
186 | /* | |
187 | * Initialize PCI Devices, report devices found. | |
188 | */ | |
189 | ||
190 | #ifndef CONFIG_PCI_PNP | |
191 | static struct pci_config_table pci_mpc85xxads_config_table[] = { | |
192 | {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
193 | PCI_IDSEL_NUMBER, PCI_ANY_ID, | |
194 | pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, | |
195 | PCI_ENET0_MEMADDR, | |
196 | PCI_COMMAND_MEMORY | | |
197 | PCI_COMMAND_MASTER}}, | |
198 | {} | |
199 | }; | |
200 | #endif | |
201 | ||
202 | ||
203 | static struct pci_controller hose = { | |
204 | #ifndef CONFIG_PCI_PNP | |
205 | config_table:pci_mpc85xxads_config_table, | |
206 | #endif | |
207 | }; | |
208 | ||
209 | #endif /* CONFIG_PCI */ | |
210 | ||
211 | ||
212 | void pci_init_board (void) | |
213 | { | |
214 | #ifdef CONFIG_PCI | |
215 | pci_mpc85xx_init (&hose); | |
216 | #endif /* CONFIG_PCI */ | |
217 | } | |
218 | ||
219 | #ifdef CONFIG_BOARD_EARLY_INIT_R | |
220 | int board_early_init_r (void) | |
221 | { | |
6d0f6bcf | 222 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
3e79b588 DZ |
223 | |
224 | /* set and reset the GPIO pin 2 which will reset the W83782G chip */ | |
225 | out_8((unsigned char*)&gur->gpoutdr, 0x3F ); | |
226 | out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */ | |
227 | udelay(200); | |
228 | out_8( (unsigned char*)&gur->gpoutdr, 0x1F ); | |
229 | ||
5d108ac8 SP |
230 | return (0); |
231 | } | |
232 | #endif /* CONFIG_BOARD_EARLY_INIT_R */ | |
e18575d5 SP |
233 | |
234 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) | |
235 | void | |
236 | ft_board_setup(void *blob, bd_t *bd) | |
237 | { | |
3e79b588 DZ |
238 | u32 val[12]; |
239 | int rc, i = 0; | |
e18575d5 SP |
240 | |
241 | ft_cpu_setup(blob, bd); | |
242 | ||
3e79b588 DZ |
243 | /* Fixup NOR FLASH mapping */ |
244 | val[i++] = 0; /* chip select number */ | |
245 | val[i++] = 0; /* always 0 */ | |
246 | val[i++] = gd->bd->bi_flashstart; | |
247 | val[i++] = gd->bd->bi_flashsize; | |
e18575d5 | 248 | |
6d0f6bcf | 249 | if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) { |
e64987a8 AG |
250 | /* Fixup LIME mapping */ |
251 | val[i++] = 2; /* chip select number */ | |
252 | val[i++] = 0; /* always 0 */ | |
6d0f6bcf JCPV |
253 | val[i++] = CONFIG_SYS_LIME_BASE; |
254 | val[i++] = CONFIG_SYS_LIME_SIZE; | |
e64987a8 AG |
255 | } |
256 | ||
3e79b588 DZ |
257 | /* Fixup FPGA mapping */ |
258 | val[i++] = 3; /* chip select number */ | |
259 | val[i++] = 0; /* always 0 */ | |
6d0f6bcf JCPV |
260 | val[i++] = CONFIG_SYS_FPGA_BASE; |
261 | val[i++] = CONFIG_SYS_FPGA_SIZE; | |
a23cddde | 262 | |
3e79b588 DZ |
263 | rc = fdt_find_and_setprop(blob, "/localbus", "ranges", |
264 | val, i * sizeof(u32), 1); | |
a23cddde | 265 | if (rc) |
3e79b588 | 266 | printf("Unable to update localbus ranges, err=%s\n", |
a23cddde | 267 | fdt_strerror(rc)); |
e18575d5 SP |
268 | } |
269 | #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ | |
e64987a8 | 270 | |
6d0f6bcf JCPV |
271 | #define CONFIG_SYS_LIME_SRST ((CONFIG_SYS_LIME_BASE) + 0x01FC002C) |
272 | #define CONFIG_SYS_LIME_CCF ((CONFIG_SYS_LIME_BASE) + 0x01FC0038) | |
273 | #define CONFIG_SYS_LIME_MMR ((CONFIG_SYS_LIME_BASE) + 0x01FCFFFC) | |
e64987a8 | 274 | /* Lime clock frequency */ |
6d0f6bcf JCPV |
275 | #define CONFIG_SYS_LIME_CLK_100MHZ 0x00000 |
276 | #define CONFIG_SYS_LIME_CLK_133MHZ 0x10000 | |
e64987a8 | 277 | /* SDRAM parameter */ |
6d0f6bcf | 278 | #define CONFIG_SYS_LIME_MMR_VALUE 0x4157BA63 |
e64987a8 AG |
279 | |
280 | #define DISPLAY_WIDTH 800 | |
281 | #define DISPLAY_HEIGHT 480 | |
282 | #define DEFAULT_BRIGHTNESS 25 | |
283 | #define BACKLIGHT_ENABLE (1 << 31) | |
284 | ||
e64987a8 AG |
285 | static const gdc_regs init_regs [] = |
286 | { | |
287 | {0x0100, 0x00010f00}, | |
288 | {0x0020, 0x801901df}, | |
289 | {0x0024, 0x00000000}, | |
290 | {0x0028, 0x00000000}, | |
291 | {0x002c, 0x00000000}, | |
292 | {0x0110, 0x00000000}, | |
293 | {0x0114, 0x00000000}, | |
294 | {0x0118, 0x01df0320}, | |
295 | {0x0004, 0x041f0000}, | |
296 | {0x0008, 0x031f031f}, | |
297 | {0x000c, 0x017f0349}, | |
298 | {0x0010, 0x020c0000}, | |
299 | {0x0014, 0x01df01e9}, | |
300 | {0x0018, 0x00000000}, | |
301 | {0x001c, 0x01e00320}, | |
302 | {0x0100, 0x80010f00}, | |
303 | {0x0, 0x0} | |
304 | }; | |
305 | ||
306 | const gdc_regs *board_get_regs (void) | |
307 | { | |
308 | return init_regs; | |
309 | } | |
310 | ||
6d0f6bcf JCPV |
311 | #define CONFIG_SYS_LIME_CID ((CONFIG_SYS_LIME_BASE) + 0x01FC00F0) |
312 | #define CONFIG_SYS_LIME_REV ((CONFIG_SYS_LIME_BASE) + 0x01FF8084) | |
fb661ea4 | 313 | int lime_probe(void) |
314 | { | |
6d0f6bcf | 315 | volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); |
fb661ea4 | 316 | uint cfg_br2; |
317 | uint cfg_or2; | |
318 | uint reg; | |
319 | ||
320 | cfg_br2 = memctl->br2; | |
321 | cfg_or2 = memctl->or2; | |
322 | ||
323 | /* Configure GPCM for CS2 */ | |
324 | memctl->br2 = 0; | |
325 | memctl->or2 = 0xfc000410; | |
6d0f6bcf | 326 | memctl->br2 = (CONFIG_SYS_LIME_BASE) | 0x00001901; |
fb661ea4 | 327 | |
328 | /* Try to access GDC ID/Revision registers */ | |
6d0f6bcf JCPV |
329 | reg = in_be32((void *)CONFIG_SYS_LIME_CID); |
330 | reg = in_be32((void *)CONFIG_SYS_LIME_CID); | |
fb661ea4 | 331 | if (reg == 0x303) { |
6d0f6bcf JCPV |
332 | reg = in_be32((void *)CONFIG_SYS_LIME_REV); |
333 | reg = in_be32((void *)CONFIG_SYS_LIME_REV); | |
fb661ea4 | 334 | reg = ((reg & ~0xff) == 0x20050100) ? 1 : 0; |
335 | } else | |
336 | reg = 0; | |
337 | ||
338 | /* Restore previous CS2 configuration */ | |
339 | memctl->br2 = 0; | |
340 | memctl->or2 = cfg_or2; | |
341 | memctl->br2 = cfg_br2; | |
342 | return reg; | |
343 | } | |
344 | ||
e64987a8 AG |
345 | /* Returns Lime base address */ |
346 | unsigned int board_video_init (void) | |
347 | { | |
fb661ea4 | 348 | if (!lime_probe()) |
e64987a8 AG |
349 | return 0; |
350 | ||
351 | /* | |
352 | * Reset Lime controller | |
353 | */ | |
6d0f6bcf | 354 | out_be32((void *)CONFIG_SYS_LIME_SRST, 0x1); |
e64987a8 AG |
355 | udelay(200); |
356 | ||
357 | /* Set Lime clock to 133MHz */ | |
6d0f6bcf | 358 | out_be32((void *)CONFIG_SYS_LIME_CCF, CONFIG_SYS_LIME_CLK_133MHZ); |
e64987a8 AG |
359 | /* Delay required */ |
360 | udelay(300); | |
361 | /* Set memory parameters */ | |
6d0f6bcf | 362 | out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_LIME_MMR_VALUE); |
e64987a8 AG |
363 | |
364 | mb862xx.winSizeX = DISPLAY_WIDTH; | |
365 | mb862xx.winSizeY = DISPLAY_HEIGHT; | |
366 | mb862xx.gdfIndex = GDF_15BIT_555RGB; | |
367 | mb862xx.gdfBytesPP = 2; | |
368 | ||
6d0f6bcf | 369 | return CONFIG_SYS_LIME_BASE; |
e64987a8 AG |
370 | } |
371 | ||
372 | #define W83782D_REG_CFG 0x40 | |
373 | #define W83782D_REG_BANK_SEL 0x4e | |
374 | #define W83782D_REG_ADCCLK 0x4b | |
375 | #define W83782D_REG_BEEP_CTRL 0x4d | |
376 | #define W83782D_REG_BEEP_CTRL2 0x57 | |
377 | #define W83782D_REG_PWMOUT1 0x5b | |
378 | #define W83782D_REG_VBAT 0x5d | |
379 | ||
380 | static int w83782d_hwmon_init(void) | |
381 | { | |
382 | u8 buf; | |
383 | ||
6d0f6bcf | 384 | if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1)) |
e64987a8 AG |
385 | return -1; |
386 | ||
6d0f6bcf JCPV |
387 | i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80); |
388 | i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0); | |
389 | i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40); | |
e64987a8 | 390 | |
6d0f6bcf JCPV |
391 | buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL); |
392 | i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL, | |
e64987a8 | 393 | buf | 0x80); |
6d0f6bcf JCPV |
394 | i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0); |
395 | i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47); | |
396 | i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01); | |
e64987a8 | 397 | |
6d0f6bcf JCPV |
398 | buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG); |
399 | i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, | |
e64987a8 AG |
400 | (buf & 0xf4) | 0x01); |
401 | return 0; | |
402 | } | |
403 | ||
404 | static void board_backlight_brightness(int br) | |
405 | { | |
406 | u32 reg; | |
407 | u8 buf; | |
408 | u8 old_buf; | |
409 | ||
410 | /* Select bank 0 */ | |
6d0f6bcf | 411 | if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) |
e64987a8 AG |
412 | goto err; |
413 | else | |
414 | buf = old_buf & 0xf8; | |
415 | ||
6d0f6bcf | 416 | if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1)) |
e64987a8 AG |
417 | goto err; |
418 | ||
419 | if (br > 0) { | |
420 | /* PWMOUT1 duty cycle ctrl */ | |
421 | buf = 255 / (100 / br); | |
6d0f6bcf | 422 | if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) |
e64987a8 AG |
423 | goto err; |
424 | ||
425 | /* LEDs on */ | |
6d0f6bcf | 426 | reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c)); |
e64987a8 | 427 | if (!(reg & BACKLIGHT_ENABLE)); |
6d0f6bcf | 428 | out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), |
e64987a8 AG |
429 | reg | BACKLIGHT_ENABLE); |
430 | } else { | |
431 | buf = 0; | |
6d0f6bcf | 432 | if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) |
e64987a8 AG |
433 | goto err; |
434 | ||
435 | /* LEDs off */ | |
6d0f6bcf | 436 | reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c)); |
e64987a8 | 437 | reg &= ~BACKLIGHT_ENABLE; |
6d0f6bcf | 438 | out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), reg); |
e64987a8 AG |
439 | } |
440 | /* Restore previous bank setting */ | |
6d0f6bcf | 441 | if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) |
e64987a8 AG |
442 | goto err; |
443 | ||
444 | return; | |
445 | err: | |
446 | printf("W83782G I2C access failed\n"); | |
447 | } | |
448 | ||
449 | void board_backlight_switch (int flag) | |
450 | { | |
451 | char * param; | |
452 | int rc; | |
453 | ||
454 | if (w83782d_hwmon_init()) | |
455 | printf ("hwmon IC init failed\n"); | |
456 | ||
457 | if (flag) { | |
458 | param = getenv("brightness"); | |
459 | rc = param ? simple_strtol(param, NULL, 10) : -1; | |
460 | if (rc < 0) | |
461 | rc = DEFAULT_BRIGHTNESS; | |
462 | } else { | |
463 | rc = 0; | |
464 | } | |
465 | board_backlight_brightness(rc); | |
466 | } | |
467 | ||
468 | #if defined(CONFIG_CONSOLE_EXTRA_INFO) | |
469 | /* | |
470 | * Return text to be printed besides the logo. | |
471 | */ | |
472 | void video_get_info_str (int line_number, char *info) | |
473 | { | |
474 | if (line_number == 1) { | |
475 | strcpy (info, " Board: Socrates"); | |
476 | } else { | |
477 | info [0] = '\0'; | |
478 | } | |
479 | } | |
480 | #endif |