[thirdparty/u-boot.git] / board / softing / vining_2000 / vining_2000.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2016 samtec automotive software & electronics gmbh
 * Copyright (C) 2017-2019 softing automotive electronics gmbH
 *
 * Author: Christoph Fritz <chf.fritz@googlemail.com>
 */

#include <init.h>
#include <net.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/sections.h>
#include <env.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/sizes.h>
#include <common.h>
#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <i2c.h>
#include <miiphy.h>
#include <netdev.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include <usb.h>
#include <usb/ehci-ci.h>
#include <pwm.h>
#include <wait_bit.h>

DECLARE_GLOBAL_DATA_PTR;

#define UART_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |	\
	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
	PAD_CTL_SRE_FAST)

#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE |	\
	PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm |		\
	PAD_CTL_SRE_FAST)

#define ENET_CLK_PAD_CTRL  PAD_CTL_DSE_34ohm

#define ENET_RX_PAD_CTRL  (PAD_CTL_PKE |			\
	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH |		\
	PAD_CTL_SRE_FAST)

#define I2C_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |	\
	PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED |		\
	PAD_CTL_DSE_40ohm)

#define USDHC_CLK_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_SPEED_MED |	\
	PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)

#define USDHC_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP |	\
	PAD_CTL_PKE |  PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm |	\
	PAD_CTL_SRE_FAST)

#define USDHC_RESET_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP |	\
	PAD_CTL_PKE |  PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm)

#define GPIO_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |	\
	PAD_CTL_PKE)

int dram_init(void)
{
	gd->ram_size = imx_ddr_size();

	return 0;
}

static iomux_v3_cfg_t const pwm_led_pads[] = {
	MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
	MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
	MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
};

static int board_net_init(void)
{
	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
	unsigned char eth1addr[6];
	int ret;

	/* just to get second mac address */
	imx_get_mac_from_fuse(1, eth1addr);
	if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
		eth_env_set_enetaddr("eth1addr", eth1addr);

	/*
	 * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
	 * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
	 * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
	 */
	clrsetbits_le32(&iomuxc_regs->gpr[1],
			IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
			IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
			IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
			IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);

	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
	if (ret)
		goto eth_fail;

	ret = enable_fec_anatop_clock(1, ENET_50MHZ);
	if (ret)
		goto eth_fail;

	return ret;

eth_fail:
	printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
	return ret;
}

#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1 for PMIC */
static struct i2c_pads_info i2c_pad_info1 = {
	.scl = {
		.i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
		.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
		.gp = IMX_GPIO_NR(1, 0),
	},
	.sda = {
		.i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
		.gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
		.gp = IMX_GPIO_NR(1, 1),
	},
};

static struct pmic *pfuze_init(unsigned char i2cbus)
{
	struct pmic *p;
	int ret;
	u32 reg;

	ret = power_pfuze100_init(i2cbus);
	if (ret)
		return NULL;

	p = pmic_get("PFUZE100");
	ret = pmic_probe(p);
	if (ret)
		return NULL;

	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
	printf("PMIC:  PFUZE%i00 ID=0x%02x\n", (reg & 1) ? 2 : 1, reg);

	/* Set SW1AB stanby volage to 0.975V */
	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
	reg &= ~SW1x_STBY_MASK;
	reg |= SW1x_0_975V;
	pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);

	/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
	pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
	reg &= ~SW1xCONF_DVSSPEED_MASK;
	reg |= SW1xCONF_DVSSPEED_4US;
	pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);

	/* Set SW1C standby voltage to 0.975V */
	pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
	reg &= ~SW1x_STBY_MASK;
	reg |= SW1x_0_975V;
	pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);

	/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
	pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
	reg &= ~SW1xCONF_DVSSPEED_MASK;
	reg |= SW1xCONF_DVSSPEED_4US;
	pmic_reg_write(p, PFUZE100_SW1CCONF, reg);

	return p;
}

static int pfuze_mode_init(struct pmic *p, u32 mode)
{
	unsigned char offset, i, switch_num;
	u32 id;
	int ret;

	pmic_reg_read(p, PFUZE100_DEVICEID, &id);
	id = id & 0xf;

	if (id == 0) {
		switch_num = 6;
		offset = PFUZE100_SW1CMODE;
	} else if (id == 1) {
		switch_num = 4;
		offset = PFUZE100_SW2MODE;
	} else {
		printf("Not supported, id=%d\n", id);
		return -EINVAL;
	}

	ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
	if (ret < 0) {
		printf("Set SW1AB mode error!\n");
		return ret;
	}

	for (i = 0; i < switch_num - 1; i++) {
		ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
		if (ret < 0) {
			printf("Set switch 0x%x mode error!\n",
			       offset + i * SWITCH_SIZE);
			return ret;
		}
	}

	return ret;
}

int power_init_board(void)
{
	struct pmic *p;
	int ret;

	p = pfuze_init(I2C_PMIC);
	if (!p)
		return -ENODEV;

	ret = pfuze_mode_init(p, APS_PFM);
	if (ret < 0)
		return ret;

	set_ldo_voltage(LDO_ARM, 1175);	/* Set VDDARM to 1.175V */
	set_ldo_voltage(LDO_SOC, 1175);	/* Set VDDSOC to 1.175V */

	return 0;
}

#ifdef CONFIG_USB_EHCI_MX6
static iomux_v3_cfg_t const usb_otg_pads[] = {
	/* OGT1 */
	MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
	MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
	/* OTG2 */
	MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
};

static void setup_iomux_usb(void)
{
	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
					 ARRAY_SIZE(usb_otg_pads));
}

int board_usb_phy_mode(int port)
{
	if (port == 1)
		return USB_INIT_HOST;
	else
		return usb_phy_mode(port);
}
#endif

#ifdef CONFIG_PWM_IMX
static int set_pwm_leds(void)
{
	int ret;

	imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
					 ARRAY_SIZE(pwm_led_pads));
	/* enable backlight PWM 2, green LED */
	ret = pwm_init(1, 0, 0);
	if (ret)
		goto error;
	/* duty cycle 200ns, period: 8000ns */
	ret = pwm_config(1, 200, 8000);
	if (ret)
		goto error;
	ret = pwm_enable(1);
	if (ret)
		goto error;

	/* enable backlight PWM 1, blue LED */
	ret = pwm_init(0, 0, 0);
	if (ret)
		goto error;
	/* duty cycle 200ns, period: 8000ns */
	ret = pwm_config(0, 200, 8000);
	if (ret)
		goto error;
	ret = pwm_enable(0);
	if (ret)
		goto error;

	/* enable backlight PWM 6, red LED */
	ret = pwm_init(5, 0, 0);
	if (ret)
		goto error;
	/* duty cycle 200ns, period: 8000ns */
	ret = pwm_config(5, 200, 8000);
	if (ret)
		goto error;
	ret = pwm_enable(5);

error:
	return ret;
}
#else
static int set_pwm_leds(void)
{
	return 0;
}
#endif

#define ADCx_HC0        0x00
#define ADCx_HS         0x08
#define ADCx_HS_C0      BIT(0)
#define ADCx_R0         0x0c
#define ADCx_CFG        0x14
#define ADCx_CFG_SWMODE 0x308
#define ADCx_GC         0x18
#define ADCx_GC_CAL     BIT(7)

static int read_adc(u32 *val)
{
	int ret;
	void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);

	/* use software mode */
	writel(ADCx_CFG_SWMODE, b + ADCx_CFG);

	/* start auto calibration */
	setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
	ret = wait_for_bit_le32(b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
	if (ret)
		goto adc_exit;

	/* start conversion */
	writel(0, b + ADCx_HC0);

	/* wait for conversion */
	ret = wait_for_bit_le32(b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
	if (ret)
		goto adc_exit;

	/* read result */
	*val = readl(b + ADCx_R0);

adc_exit:
	if (ret)
		printf("ADC failure (ret=%i)\n", ret);
	unmap_physmem(b, MAP_NOCACHE);
	return ret;
}

#define VAL_UPPER	2498
#define VAL_LOWER	1550

static int set_pin_state(void)
{
	u32 val;
	int ret;

	ret = read_adc(&val);
	if (ret)
		return ret;

	if (val >= VAL_UPPER)
		env_set("pin_state", "connected");
	else if (val < VAL_UPPER && val > VAL_LOWER)
		env_set("pin_state", "open");
	else
		env_set("pin_state", "button");

	return ret;
}

int board_late_init(void)
{
	int ret;

	ret = set_pwm_leds();
	if (ret)
		return ret;

	ret = set_pin_state();

	return ret;
}

int board_early_init_f(void)
{
	setup_iomux_usb();

	return 0;
}

int board_init(void)
{
	/* Address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

#ifdef CONFIG_SYS_I2C_MXC
	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
#endif

	return board_net_init();
}

int checkboard(void)
{
	puts("Board: VIN|ING 2000\n");

	return 0;
}

#define PCIE_PHY_PUP_REQ		BIT(7)

void board_preboot_os(void)
{
	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
	struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;

	/* Bring the PCI power domain up, so that old vendorkernel works. */
	setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
	setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
	setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
}

#ifdef CONFIG_SPL_BUILD
#include <linux/libfdt.h>
#include <spl.h>
#include <asm/arch/mx6-ddr.h>

static iomux_v3_cfg_t const pcie_pads[] = {
	MX6_PAD_NAND_DATA02__GPIO4_IO_6 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
};

static iomux_v3_cfg_t const uart_pads[] = {
	MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};

static iomux_v3_cfg_t const usdhc4_pads[] = {
	MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};

static void vining2000_spl_setup_iomux_pcie(void)
{
	imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
}

static void vining2000_spl_setup_iomux_uart(void)
{
	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}

static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR };

int board_mmc_init(struct bd_info *bis)
{
	imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));

	usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
	gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
	return fsl_esdhc_initialize(bis, &usdhc_cfg);
}

int board_mmc_getcd(struct mmc *mmc)
{
	return 1;
}

const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
	.dram_dqm0		= 0x00000028,
	.dram_dqm1		= 0x00000028,
	.dram_dqm2		= 0x00000028,
	.dram_dqm3		= 0x00000028,
	.dram_ras		= 0x00000028,
	.dram_cas		= 0x00000028,
	.dram_odt0		= 0x00000028,
	.dram_odt1		= 0x00000028,
	.dram_sdba2		= 0x00000000,
	.dram_sdcke0		= 0x00003000,
	.dram_sdcke1		= 0x00003000,
	.dram_sdclk_0		= 0x00000030,
	.dram_sdqs0		= 0x00000028,
	.dram_sdqs1		= 0x00000028,
	.dram_sdqs2		= 0x00000028,
	.dram_sdqs3		= 0x00000028,
	.dram_reset		= 0x00000028,
};

const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
	.grp_addds		= 0x00000028,
	.grp_b0ds		= 0x00000028,
	.grp_b1ds		= 0x00000028,
	.grp_b2ds		= 0x00000028,
	.grp_b3ds		= 0x00000028,
	.grp_ctlds		= 0x00000028,
	.grp_ddr_type		= 0x000c0000,
	.grp_ddrmode		= 0x00020000,
	.grp_ddrmode_ctl	= 0x00020000,
	.grp_ddrpke		= 0x00000000,
};

const struct mx6_mmdc_calibration mx6_mmcd_calib = {
	.p0_mpwldectrl0		= 0x0022001C,
	.p0_mpwldectrl1		= 0x001F001A,
	.p0_mpdgctrl0		= 0x01380134,
	.p0_mpdgctrl1		= 0x0124011C,
	.p0_mprddlctl		= 0x42404444,
	.p0_mpwrdlctl		= 0x36383C38,
};

static struct mx6_ddr3_cfg mem_ddr = {
	.mem_speed	= 1600,
	.density	= 4,
	.width		= 32,
	.banks		= 8,
	.rowaddr	= 15,
	.coladdr	= 10,
	.pagesz		= 2,
	.trcd		= 1391,
	.trcmin		= 4875,
	.trasmin	= 3500,
};

static void ccgr_init(void)
{
	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	writel(0xF000000F, &ccm->CCGR0);	/* AIPS_TZ{1,2,3} */
	writel(0x303C0000, &ccm->CCGR1);	/* GPT, OCRAM */
	writel(0x00FFFCC0, &ccm->CCGR2);	/* IPMUX, I2C1, I2C3 */
	writel(0x3F300030, &ccm->CCGR3);	/* OCRAM, MMDC, ENET */
	writel(0x0000C003, &ccm->CCGR4);	/* PCI, PL301 */
	writel(0x0F0330C3, &ccm->CCGR5);	/* UART, ROM */
	writel(0x00000F00, &ccm->CCGR6);	/* SDHI4, EIM */
}

static void vining2000_spl_dram_init(void)
{
	struct mx6_ddr_sysinfo sysinfo = {
		.dsize		= mem_ddr.width / 32,
		.cs_density	= 24,
		.ncs		= 1,
		.cs1_mirror	= 0,
		.rtt_wr		= 1,	/* RTT_wr = RZQ/4 */
		.rtt_nom	= 1,	/* RTT_Nom = RZQ/4 */
		.walat		= 1,	/* Write additional latency */
		.ralat		= 5,	/* Read additional latency */
		.mif3_mode	= 3,	/* Command prediction working mode */
		.bi_on		= 1,	/* Bank interleaving enabled */
		.sde_to_rst	= 0x10,	/* 14 cycles, 200us (JEDEC default) */
		.rst_to_cke	= 0x23,	/* 33 cycles, 500us (JEDEC default) */
		.ddr_type	= DDR_TYPE_DDR3,
		.refsel		= 1,	/* Refresh cycles at 32KHz */
		.refr		= 7,	/* 8 refresh commands per refresh cycle */
	};

	mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);

	/* Perform DDR DRAM calibration */
	udelay(100);
	mmdc_do_write_level_calibration(&sysinfo);
	mmdc_do_dqs_calibration(&sysinfo);
}

void board_init_f(ulong dummy)
{
	/* setup AIPS and disable watchdog */
	arch_cpu_init();

	ccgr_init();

	/* iomux setup */
	vining2000_spl_setup_iomux_pcie();
	vining2000_spl_setup_iomux_uart();

	/* setup GP timer */
	timer_init();

	/* reset the PCIe device */
	gpio_set_value(IMX_GPIO_NR(4, 6), 1);
	udelay(50);
	gpio_set_value(IMX_GPIO_NR(4, 6), 0);

	/* UART clocks enabled and gd valid - init serial console */
	preloader_console_init();

	/* DDR initialization */
	vining2000_spl_dram_init();

	/* Clear the BSS. */
	memset(__bss_start, 0, __bss_end - __bss_start);

	/* load/boot image from boot device */
	board_init_r(NULL, 0);
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
730d2544 CF	2	/*
730d2544 CF	3	* Copyright (C) 2016 samtec automotive software & electronics gmbh
4c05e966	4	* Copyright (C) 2017-2019 softing automotive electronics gmbH
730d2544 CF	5	*
730d2544 CF	6	* Author: Christoph Fritz <chf.fritz@googlemail.com>
730d2544 CF	7	*/
730d2544 CF	8
5255932f	9	#include <init.h>
90526e9f	10	#include <net.h>
730d2544 CF	11	#include <asm/arch/clock.h>
	12	#include <asm/arch/crm_regs.h>
	13	#include <asm/arch/iomux.h>
	14	#include <asm/arch/imx-regs.h>
	15	#include <asm/arch/mx6-pins.h>
	16	#include <asm/arch/sys_proto.h>
401d1c4f	17	#include <asm/global_data.h>
730d2544	18	#include <asm/gpio.h>
552a848e	19	#include <asm/mach-imx/iomux-v3.h>
730d2544	20	#include <asm/io.h>
552a848e	21	#include <asm/mach-imx/mxc_i2c.h>
506df9dc	22	#include <asm/sections.h>
9fb625ce	23	#include <env.h>
cd93d625	24	#include <linux/bitops.h>
c05ed00a	25	#include <linux/delay.h>
730d2544	26	#include <linux/sizes.h>
d678a59d	27	#include <common.h>
e37ac717	28	#include <fsl_esdhc_imx.h>
730d2544 CF	29	#include <mmc.h>
	30	#include <i2c.h>
	31	#include <miiphy.h>
	32	#include <netdev.h>
	33	#include <power/pmic.h>
	34	#include <power/pfuze100_pmic.h>
	35	#include <usb.h>
	36	#include <usb/ehci-ci.h>
	37	#include <pwm.h>
	38	#include <wait_bit.h>
	39
	40	DECLARE_GLOBAL_DATA_PTR;
	41
	42	#define UART_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_PUS_100K_UP \| \
	43	PAD_CTL_PKE \| PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| \
	44	PAD_CTL_SRE_FAST)
	45
	46	#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_PKE \| \
	47	PAD_CTL_SPEED_HIGH \| PAD_CTL_DSE_48ohm \| \
	48	PAD_CTL_SRE_FAST)
	49
	50	#define ENET_CLK_PAD_CTRL PAD_CTL_DSE_34ohm
	51
	52	#define ENET_RX_PAD_CTRL (PAD_CTL_PKE \| \
	53	PAD_CTL_PUS_100K_DOWN \| PAD_CTL_SPEED_HIGH \| \
	54	PAD_CTL_SRE_FAST)
	55
	56	#define I2C_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_PUS_100K_UP \| \
	57	PAD_CTL_PKE \| PAD_CTL_ODE \| PAD_CTL_SPEED_MED \| \
	58	PAD_CTL_DSE_40ohm)
	59
	60	#define USDHC_CLK_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_SPEED_MED \| \
	61	PAD_CTL_DSE_80ohm \| PAD_CTL_SRE_FAST)
	62
	63	#define USDHC_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_PUS_47K_UP \| \
	64	PAD_CTL_PKE \| PAD_CTL_SPEED_MED \| PAD_CTL_DSE_80ohm \| \
	65	PAD_CTL_SRE_FAST)
	66
d5786308 CF	67	#define USDHC_RESET_CTRL (PAD_CTL_HYS \| PAD_CTL_PUS_47K_UP \| \
	68	PAD_CTL_PKE \| PAD_CTL_SPEED_MED \| PAD_CTL_DSE_80ohm)
	69
730d2544 CF	70	#define GPIO_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_PUS_100K_UP \| \
	71	PAD_CTL_PKE)
	72
	73	int dram_init(void)
	74	{
	75	gd->ram_size = imx_ddr_size();
	76
	77	return 0;
	78	}
	79
730d2544 CF	80	static iomux_v3_cfg_t const pwm_led_pads[] = {
	81	MX6_PAD_RGMII2_RD2__PWM2_OUT \| MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
	82	MX6_PAD_RGMII2_TD2__PWM6_OUT \| MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
	83	MX6_PAD_RGMII2_RD3__PWM1_OUT \| MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
	84	};
	85
26822fd2	86	static int board_net_init(void)
730d2544 CF	87	{
730d2544 CF	88	struct iomuxc iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
730d2544	89	unsigned char eth1addr[6];
26822fd2	90	int ret;
730d2544	91
26822fd2	92	/* just to get second mac address */
730d2544	93	imx_get_mac_from_fuse(1, eth1addr);
00caae6d	94	if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
fd1e959e	95	eth_env_set_enetaddr("eth1addr", eth1addr);
730d2544	96
730d2544 CF	97	/*
	98	* Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
	99	* ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
	100	* ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
	101	*/
	102	clrsetbits_le32(&iomuxc_regs->gpr[1],
	103	IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK \|
	104	IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
	105	IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK \|
	106	IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
	107
	108	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
	109	if (ret)
	110	goto eth_fail;
	111
26822fd2	112	ret = enable_fec_anatop_clock(1, ENET_50MHZ);
730d2544 CF	113	if (ret)
	114	goto eth_fail;
	115
	116	return ret;
	117
	118	eth_fail:
	119	printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
730d2544 CF	120	return ret;
	121	}
	122
	123	#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
	124	/* I2C1 for PMIC */
	125	static struct i2c_pads_info i2c_pad_info1 = {
	126	.scl = {
	127	.i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL \| PC,
	128	.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 \| PC,
	129	.gp = IMX_GPIO_NR(1, 0),
	130	},
	131	.sda = {
	132	.i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA \| PC,
	133	.gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 \| PC,
	134	.gp = IMX_GPIO_NR(1, 1),
	135	},
	136	};
	137
	138	static struct pmic *pfuze_init(unsigned char i2cbus)
	139	{
	140	struct pmic *p;
	141	int ret;
	142	u32 reg;
	143
	144	ret = power_pfuze100_init(i2cbus);
	145	if (ret)
	146	return NULL;
	147
	148	p = pmic_get("PFUZE100");
	149	ret = pmic_probe(p);
	150	if (ret)
	151	return NULL;
	152
	153	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
f3284e40	154	printf("PMIC: PFUZE%i00 ID=0x%02x\n", (reg & 1) ? 2 : 1, reg);
730d2544 CF	155
	156	/* Set SW1AB stanby volage to 0.975V */
	157	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
	158	reg &= ~SW1x_STBY_MASK;
	159	reg \|= SW1x_0_975V;
	160	pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
	161
	162	/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
	163	pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
	164	reg &= ~SW1xCONF_DVSSPEED_MASK;
	165	reg \|= SW1xCONF_DVSSPEED_4US;
	166	pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
	167
	168	/* Set SW1C standby voltage to 0.975V */
	169	pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
	170	reg &= ~SW1x_STBY_MASK;
	171	reg \|= SW1x_0_975V;
	172	pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
	173
	174	/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
	175	pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
	176	reg &= ~SW1xCONF_DVSSPEED_MASK;
	177	reg \|= SW1xCONF_DVSSPEED_4US;
	178	pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
	179
	180	return p;
	181	}
	182
	183	static int pfuze_mode_init(struct pmic *p, u32 mode)
	184	{
	185	unsigned char offset, i, switch_num;
	186	u32 id;
	187	int ret;
	188
	189	pmic_reg_read(p, PFUZE100_DEVICEID, &id);
	190	id = id & 0xf;
	191
	192	if (id == 0) {
	193	switch_num = 6;
	194	offset = PFUZE100_SW1CMODE;
	195	} else if (id == 1) {
	196	switch_num = 4;
	197	offset = PFUZE100_SW2MODE;
	198	} else {
	199	printf("Not supported, id=%d\n", id);
	200	return -EINVAL;
	201	}
	202
	203	ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
	204	if (ret < 0) {
	205	printf("Set SW1AB mode error!\n");
	206	return ret;
	207	}
	208
	209	for (i = 0; i < switch_num - 1; i++) {
	210	ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
	211	if (ret < 0) {
	212	printf("Set switch 0x%x mode error!\n",
	213	offset + i * SWITCH_SIZE);
	214	return ret;
	215	}
	216	}
	217
	218	return ret;
219	}
220
221	int power_init_board(void)
222	{
223	struct pmic *p;
224	int ret;
225
226	p = pfuze_init(I2C_PMIC);
227	if (!p)
228	return -ENODEV;
229
230	ret = pfuze_mode_init(p, APS_PFM);
231	if (ret < 0)
232	return ret;
233
ed22a883 MV	234	set_ldo_voltage(LDO_ARM, 1175); /* Set VDDARM to 1.175V */
	235	set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
	236
730d2544 CF	237	return 0;
	238	}
	239
	240	#ifdef CONFIG_USB_EHCI_MX6
	241	static iomux_v3_cfg_t const usb_otg_pads[] = {
	242	/* OGT1 */
	243	MX6_PAD_GPIO1_IO09__USB_OTG1_PWR \| MUX_PAD_CTRL(NO_PAD_CTRL),
	244	MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID \| MUX_PAD_CTRL(NO_PAD_CTRL),
	245	/* OTG2 */
	246	MX6_PAD_GPIO1_IO12__USB_OTG2_PWR \| MUX_PAD_CTRL(NO_PAD_CTRL)
	247	};
	248
	249	static void setup_iomux_usb(void)
	250	{
	251	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
	252	ARRAY_SIZE(usb_otg_pads));
	253	}
	254
	255	int board_usb_phy_mode(int port)
	256	{
	257	if (port == 1)
	258	return USB_INIT_HOST;
	259	else
	260	return usb_phy_mode(port);
	261	}
	262	#endif
	263
	264	#ifdef CONFIG_PWM_IMX
	265	static int set_pwm_leds(void)
	266	{
	267	int ret;
	268
	269	imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
	270	ARRAY_SIZE(pwm_led_pads));
	271	/* enable backlight PWM 2, green LED */
	272	ret = pwm_init(1, 0, 0);
	273	if (ret)
	274	goto error;
	275	/* duty cycle 200ns, period: 8000ns */
	276	ret = pwm_config(1, 200, 8000);
	277	if (ret)
	278	goto error;
	279	ret = pwm_enable(1);
	280	if (ret)
	281	goto error;
	282
	283	/* enable backlight PWM 1, blue LED */
	284	ret = pwm_init(0, 0, 0);
	285	if (ret)
	286	goto error;
	287	/* duty cycle 200ns, period: 8000ns */
	288	ret = pwm_config(0, 200, 8000);
	289	if (ret)
	290	goto error;
	291	ret = pwm_enable(0);
	292	if (ret)
	293	goto error;
	294
	295	/* enable backlight PWM 6, red LED */
	296	ret = pwm_init(5, 0, 0);
	297	if (ret)
	298	goto error;
	299	/* duty cycle 200ns, period: 8000ns */
	300	ret = pwm_config(5, 200, 8000);
301	if (ret)
302	goto error;
303	ret = pwm_enable(5);
304
305	error:
306	return ret;
307	}
308	#else
309	static int set_pwm_leds(void)
310	{
311	return 0;
312	}
313	#endif
314
315	#define ADCx_HC0 0x00
316	#define ADCx_HS 0x08
317	#define ADCx_HS_C0 BIT(0)
318	#define ADCx_R0 0x0c
319	#define ADCx_CFG 0x14
320	#define ADCx_CFG_SWMODE 0x308
321	#define ADCx_GC 0x18
322	#define ADCx_GC_CAL BIT(7)
323
324	static int read_adc(u32 *val)
325	{
326	int ret;
327	void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
328
329	/* use software mode */
330	writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
331
332	/* start auto calibration */
333	setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
48263504	334	ret = wait_for_bit_le32(b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
730d2544 CF	335	if (ret)
	336	goto adc_exit;
	337
	338	/* start conversion */
	339	writel(0, b + ADCx_HC0);
	340
	341	/* wait for conversion */
48263504	342	ret = wait_for_bit_le32(b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
730d2544 CF	343	if (ret)
	344	goto adc_exit;
	345
	346	/* read result */
	347	*val = readl(b + ADCx_R0);
	348
	349	adc_exit:
	350	if (ret)
	351	printf("ADC failure (ret=%i)\n", ret);
	352	unmap_physmem(b, MAP_NOCACHE);
	353	return ret;
	354	}
	355
	356	#define VAL_UPPER 2498
	357	#define VAL_LOWER 1550
	358
	359	static int set_pin_state(void)
	360	{
	361	u32 val;
	362	int ret;
	363
	364	ret = read_adc(&val);
	365	if (ret)
	366	return ret;
	367
	368	if (val >= VAL_UPPER)
382bee57	369	env_set("pin_state", "connected");
730d2544	370	else if (val < VAL_UPPER && val > VAL_LOWER)
382bee57	371	env_set("pin_state", "open");
730d2544	372	else
382bee57	373	env_set("pin_state", "button");
730d2544 CF	374
	375	return ret;
	376	}
	377
	378	int board_late_init(void)
	379	{
	380	int ret;
	381
	382	ret = set_pwm_leds();
	383	if (ret)
	384	return ret;
	385
	386	ret = set_pin_state();
	387
	388	return ret;
	389	}
	390
	391	int board_early_init_f(void)
	392	{
730d2544 CF	393	setup_iomux_usb();
	394
	395	return 0;
	396	}
	397
730d2544 CF	398	int board_init(void)
	399	{
	400	/* Address of boot parameters */
	401	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	402
	403	#ifdef CONFIG_SYS_I2C_MXC
	404	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
	405	#endif
	406
26822fd2	407	return board_net_init();
730d2544 CF	408	}
	409
	410	int checkboard(void)
	411	{
	412	puts("Board: VIN\|ING 2000\n");
	413
	414	return 0;
	415	}
7d84f446	416
edaec532 MV	417	#define PCIE_PHY_PUP_REQ BIT(7)
	418
	419	void board_preboot_os(void)
	420	{
	421	struct iomuxc iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
	422	struct gpc gpc_regs = (struct gpc )GPC_BASE_ADDR;
	423
	424	/* Bring the PCI power domain up, so that old vendorkernel works. */
	425	setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
	426	setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
	427	setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
	428	}
	429
7d84f446 MV	430	#ifdef CONFIG_SPL_BUILD
	431	#include <linux/libfdt.h>
	432	#include <spl.h>
	433	#include <asm/arch/mx6-ddr.h>
	434
edaec532 MV	435	static iomux_v3_cfg_t const pcie_pads[] = {
	436	MX6_PAD_NAND_DATA02__GPIO4_IO_6 \| MUX_PAD_CTRL(GPIO_PAD_CTRL),
	437	};
	438
7d84f446 MV	439	static iomux_v3_cfg_t const uart_pads[] = {
	440	MX6_PAD_GPIO1_IO04__UART1_TX \| MUX_PAD_CTRL(UART_PAD_CTRL),
	441	MX6_PAD_GPIO1_IO05__UART1_RX \| MUX_PAD_CTRL(UART_PAD_CTRL),
	442	};
	443
	444	static iomux_v3_cfg_t const usdhc4_pads[] = {
	445	MX6_PAD_SD4_CLK__USDHC4_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	446	MX6_PAD_SD4_CMD__USDHC4_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	447	MX6_PAD_SD4_DATA0__USDHC4_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	448	MX6_PAD_SD4_DATA1__USDHC4_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	449	MX6_PAD_SD4_DATA2__USDHC4_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	450	MX6_PAD_SD4_DATA3__USDHC4_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	451	MX6_PAD_SD4_DATA4__USDHC4_DATA4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	452	MX6_PAD_SD4_DATA5__USDHC4_DATA5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	453	MX6_PAD_SD4_DATA6__USDHC4_DATA6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	454	MX6_PAD_SD4_DATA7__USDHC4_DATA7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	455	};
	456
edaec532 MV	457	static void vining2000_spl_setup_iomux_pcie(void)
	458	{
	459	imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
	460	}
	461
7d84f446 MV	462	static void vining2000_spl_setup_iomux_uart(void)
	463	{
	464	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
	465	}
	466
625bbd38 MV	467	static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR };
625bbd38 MV	468
b75d8dc5	469	int board_mmc_init(struct bd_info *bis)
7d84f446	470	{
625bbd38	471	imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
7d84f446	472
625bbd38	473	usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
7d84f446 MV	474	gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
	475	return fsl_esdhc_initialize(bis, &usdhc_cfg);
	476	}
	477
	478	int board_mmc_getcd(struct mmc *mmc)
	479	{
	480	return 1;
	481	}
	482
	483	const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
	484	.dram_dqm0 = 0x00000028,
	485	.dram_dqm1 = 0x00000028,
	486	.dram_dqm2 = 0x00000028,
	487	.dram_dqm3 = 0x00000028,
	488	.dram_ras = 0x00000028,
	489	.dram_cas = 0x00000028,
	490	.dram_odt0 = 0x00000028,
	491	.dram_odt1 = 0x00000028,
	492	.dram_sdba2 = 0x00000000,
	493	.dram_sdcke0 = 0x00003000,
	494	.dram_sdcke1 = 0x00003000,
	495	.dram_sdclk_0 = 0x00000030,
	496	.dram_sdqs0 = 0x00000028,
	497	.dram_sdqs1 = 0x00000028,
	498	.dram_sdqs2 = 0x00000028,
	499	.dram_sdqs3 = 0x00000028,
	500	.dram_reset = 0x00000028,
	501	};
	502
	503	const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
	504	.grp_addds = 0x00000028,
	505	.grp_b0ds = 0x00000028,
	506	.grp_b1ds = 0x00000028,
	507	.grp_b2ds = 0x00000028,
	508	.grp_b3ds = 0x00000028,
	509	.grp_ctlds = 0x00000028,
	510	.grp_ddr_type = 0x000c0000,
	511	.grp_ddrmode = 0x00020000,
	512	.grp_ddrmode_ctl = 0x00020000,
	513	.grp_ddrpke = 0x00000000,
	514	};
	515
	516	const struct mx6_mmdc_calibration mx6_mmcd_calib = {
	517	.p0_mpwldectrl0 = 0x0022001C,
	518	.p0_mpwldectrl1 = 0x001F001A,
	519	.p0_mpdgctrl0 = 0x01380134,
	520	.p0_mpdgctrl1 = 0x0124011C,
	521	.p0_mprddlctl = 0x42404444,
	522	.p0_mpwrdlctl = 0x36383C38,
	523	};
	524
	525	static struct mx6_ddr3_cfg mem_ddr = {
	526	.mem_speed = 1600,
	527	.density = 4,
	528	.width = 32,
	529	.banks = 8,
	530	.rowaddr = 15,
	531	.coladdr = 10,
	532	.pagesz = 2,
	533	.trcd = 1391,
	534	.trcmin = 4875,
	535	.trasmin = 3500,
	536	};
	537
538	static void ccgr_init(void)
539	{
540	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
541
542	writel(0xF000000F, &ccm->CCGR0); /* AIPS_TZ{1,2,3} */
543	writel(0x303C0000, &ccm->CCGR1); /* GPT, OCRAM */
544	writel(0x00FFFCC0, &ccm->CCGR2); /* IPMUX, I2C1, I2C3 */
545	writel(0x3F300030, &ccm->CCGR3); /* OCRAM, MMDC, ENET */
546	writel(0x0000C003, &ccm->CCGR4); /* PCI, PL301 */
547	writel(0x0F0330C3, &ccm->CCGR5); /* UART, ROM */
548	writel(0x00000F00, &ccm->CCGR6); /* SDHI4, EIM */
549	}
550
551	static void vining2000_spl_dram_init(void)
552	{
553	struct mx6_ddr_sysinfo sysinfo = {
554	.dsize = mem_ddr.width / 32,
555	.cs_density = 24,
556	.ncs = 1,
557	.cs1_mirror = 0,
558	.rtt_wr = 1, /* RTT_wr = RZQ/4 */
559	.rtt_nom = 1, /* RTT_Nom = RZQ/4 */
560	.walat = 1, /* Write additional latency */
561	.ralat = 5, /* Read additional latency */
562	.mif3_mode = 3, /* Command prediction working mode */
563	.bi_on = 1, /* Bank interleaving enabled */
564	.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
565	.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
566	.ddr_type = DDR_TYPE_DDR3,
567	.refsel = 1, /* Refresh cycles at 32KHz */
568	.refr = 7, /* 8 refresh commands per refresh cycle */
569	};
570
571	mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
572	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
5b97abab MV	573
	574	/* Perform DDR DRAM calibration */
	575	udelay(100);
	576	mmdc_do_write_level_calibration(&sysinfo);
	577	mmdc_do_dqs_calibration(&sysinfo);
7d84f446 MV	578	}
	579
	580	void board_init_f(ulong dummy)
	581	{
	582	/* setup AIPS and disable watchdog */
	583	arch_cpu_init();
	584
	585	ccgr_init();
	586
	587	/* iomux setup */
edaec532	588	vining2000_spl_setup_iomux_pcie();
7d84f446 MV	589	vining2000_spl_setup_iomux_uart();
	590
	591	/* setup GP timer */
	592	timer_init();
	593
edaec532 MV	594	/* reset the PCIe device */
	595	gpio_set_value(IMX_GPIO_NR(4, 6), 1);
	596	udelay(50);
	597	gpio_set_value(IMX_GPIO_NR(4, 6), 0);
	598
7d84f446 MV	599	/* UART clocks enabled and gd valid - init serial console */
	600	preloader_console_init();
	601
	602	/* DDR initialization */
	603	vining2000_spl_dram_init();
	604
	605	/* Clear the BSS. */
	606	memset(__bss_start, 0, __bss_end - __bss_start);
	607
	608	/* load/boot image from boot device */
	609	board_init_r(NULL, 0);
	610	}
	611	#endif