[people/ms/u-boot.git] / board / spc1920 / spc1920.c

/*
 * (C) Copyright 2000-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <config.h>
#include <common.h>
#include <mpc8xx.h>
#include "pld.h"
#include "hpi.h"

#define	_NOT_USED_	0xFFFFFFFF

static long int dram_size (long int, long int *, long int);

const uint sdram_table[] = {
	/*
	 * Single Read. (Offset 0 in UPMB RAM)
	 */
	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
	0x1FF77C47, /* last */
	/*
	 * SDRAM Initialization (offset 5 in UPMB RAM)
	 *
	 * This is no UPM entry point. The following definition uses
	 * the remaining space to establish an initialization
	 * sequence, which is executed by a RUN command.
	 *
	 */
	0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
	/*
	 * Burst Read. (Offset 8 in UPMB RAM)
	 */
	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Single Write. (Offset 18 in UPMB RAM)
	 */
	0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Burst Write. (Offset 20 in UPMB RAM)
	 */
	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
	_NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Refresh  (Offset 30 in UPMB RAM)
	 */
	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	0xFFFFFC84, 0xFFFFFC07, /* last */
	_NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Exception. (Offset 3c in UPMB RAM)
	 */
	0x7FFFFC07, /* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_,
};

phys_size_t initdram (int board_type)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immr->im_memctl;
	/* volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; */

	long int size_b0;
	long int size8, size9;
	int i;

	/*
	 * Configure UPMB for SDRAM
	 */
	upmconfig (UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));

	udelay(100);

	memctl->memc_mptpr = CONFIG_SYS_MPTPR;

	/* burst length=4, burst type=sequential, CAS latency=2 */
	memctl->memc_mar = CONFIG_SYS_MAR;

	/*
	 * Map controller bank 1 to the SDRAM bank at preliminary address.
	 */
	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;

	/* initialize memory address register */
	memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; /* refresh not enabled yet */

	/* mode initialization (offset 5) */
	udelay (200);				/* 0x80006105 */
	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x05);

	/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
	udelay (1);				/* 0x80006130 */
	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30);
	udelay (1);				/* 0x80006130 */
	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30);
	udelay (1);				/* 0x80006106 */
	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x06);

	memctl->memc_mbmr |= MBMR_PTBE;	/* refresh enabled */

	udelay (200);

	/* Need at least 10 DRAM accesses to stabilize */
	for (i = 0; i < 10; ++i) {
		volatile unsigned long *addr =
			(volatile unsigned long *) CONFIG_SYS_SDRAM_BASE;
		unsigned long val;

		val = *(addr + i);
		*(addr + i) = val;
	}

	/*
	 * Check Bank 0 Memory Size for re-configuration
	 *
	 * try 8 column mode
	 */
	size8 = dram_size (CONFIG_SYS_MBMR_8COL, (long *)CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE);

	udelay (1000);

	/*
	 * try 9 column mode
	 */
	size9 = dram_size (CONFIG_SYS_MBMR_9COL, (long *)CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE);

	if (size8 < size9) {		/* leave configuration at 9 columns */
		size_b0 = size9;
		memctl->memc_mbmr = CONFIG_SYS_MBMR_9COL | MBMR_PTBE;
		udelay (500);
	} else {			/* back to 8 columns            */
		size_b0 = size8;
		memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE;
		udelay (500);
	}

	/*
	 * Final mapping:
	 */

	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) |
			OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING;
	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V;
	udelay (1000);

	/* initalize the DSP Host Port Interface */
	hpi_init();

	/* FRAM Setup */
	memctl->memc_or4 = CONFIG_SYS_OR4;
	memctl->memc_br4 = CONFIG_SYS_BR4;
	udelay(1000);

	return (size_b0);
}

/*
 * Check memory range for valid RAM. A simple memory test determines
 * the actually available RAM size between addresses `base' and
 * `base + maxsize'. Some (not all) hardware errors are detected:
 * - short between address lines
 * - short between data lines
 */
static long int dram_size (long int mbmr_value, long int *base,
			   long int maxsize)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;

	memctl->memc_mbmr = mbmr_value;

	return (get_ram_size (base, maxsize));
}


/************* other stuff ******************/


int board_early_init_f(void)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;

	/* Set Go/NoGo led (PA15) to color red */
	immap->im_ioport.iop_papar &= ~0x1;
	immap->im_ioport.iop_paodr &= ~0x1;
	immap->im_ioport.iop_padir |= 0x1;
	immap->im_ioport.iop_padat |= 0x1;

#if 0
	/* Turn on LED PD9 */
	immap->im_ioport.iop_pdpar &= ~(0x0040);
	immap->im_ioport.iop_pddir |= 0x0040;
	immap->im_ioport.iop_pddat |= 0x0040;
#endif

	/*
	 * Enable console on SMC1. This requires turning on
	 * the com2_en signal and SMC1_DISABLE
	 */

	/* SMC1_DISABLE: PB17 */
	immap->im_cpm.cp_pbodr &= ~0x4000;
	immap->im_cpm.cp_pbpar &= ~0x4000;
	immap->im_cpm.cp_pbdir |= 0x4000;
	immap->im_cpm.cp_pbdat &= ~0x4000;

	/* COM2_EN: PD10 */
	immap->im_ioport.iop_pdpar &= ~0x0020;
	immap->im_ioport.iop_pddir &= ~0x4000;
	immap->im_ioport.iop_pddir |= 0x0020;
	immap->im_ioport.iop_pddat |= 0x0020;


#ifdef CONFIG_SYS_SMC1_PLD_CLK4 /* SMC1 uses CLK4 from PLD */
	immap->im_cpm.cp_simode |= 0x7000;
	immap->im_cpm.cp_simode &= ~(0x8000);
#endif

	return 0;
}

int last_stage_init(void)
{
#ifdef CONFIG_SPC1920_HPI_TEST
	printf("CMB1920 Host Port Interface Test: %s\n",
	       hpi_test() ? "Failed!" : "OK");
#endif
	return 0;
}

int checkboard (void)
{
	puts("Board: SPC1920\n");
	return 0;
}
Commit	Line	Data
b02d0177 MK	1	/*
	2	* (C) Copyright 2000-2004
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
b02d0177 MK	8	*/
	9
	10	#include <config.h>
	11	#include <common.h>
	12	#include <mpc8xx.h>
	13	#include "pld.h"
d28707db	14	#include "hpi.h"
b02d0177 MK	15
b02d0177 MK	16	#define _NOT_USED_ 0xFFFFFFFF
b02d0177 MK	17
	18	static long int dram_size (long int, long int *, long int);
	19
	20	const uint sdram_table[] = {
	21	/*
	22	* Single Read. (Offset 0 in UPMB RAM)
	23	*/
	24	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
	25	0x1FF77C47, /* last */
	26	/*
	27	* SDRAM Initialization (offset 5 in UPMB RAM)
	28	*
	29	* This is no UPM entry point. The following definition uses
	30	* the remaining space to establish an initialization
	31	* sequence, which is executed by a RUN command.
	32	*
	33	*/
	34	0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
	35	/*
	36	* Burst Read. (Offset 8 in UPMB RAM)
	37	*/
	38	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
	39	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
	40	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	41	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	42	/*
	43	* Single Write. (Offset 18 in UPMB RAM)
	44	*/
	45	0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
	46	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	47	/*
	48	* Burst Write. (Offset 20 in UPMB RAM)
	49	*/
	50	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
	51	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
	52	_NOT_USED_,
	53	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	54	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	55	/*
	56	* Refresh (Offset 30 in UPMB RAM)
	57	*/
	58	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	59	0xFFFFFC84, 0xFFFFFC07, /* last */
	60	_NOT_USED_, _NOT_USED_,
	61	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	62	/*
	63	* Exception. (Offset 3c in UPMB RAM)
	64	*/
	65	0x7FFFFC07, /* last */
	66	_NOT_USED_, _NOT_USED_, _NOT_USED_,
	67	};
	68
9973e3c6	69	phys_size_t initdram (int board_type)
b02d0177	70	{
6d0f6bcf	71	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
b02d0177	72	volatile memctl8xx_t *memctl = &immr->im_memctl;
6d0f6bcf	73	/* volatile spc1920_pld_t pld = (spc1920_pld_t ) CONFIG_SYS_SPC1920_PLD_BASE; */
b02d0177 MK	74
	75	long int size_b0;
	76	long int size8, size9;
	77	int i;
	78
	79	/*
	80	* Configure UPMB for SDRAM
	81	*/
	82	upmconfig (UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
	83
	84	udelay(100);
	85
6d0f6bcf	86	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
b02d0177 MK	87
b02d0177 MK	88	/* burst length=4, burst type=sequential, CAS latency=2 */
6d0f6bcf	89	memctl->memc_mar = CONFIG_SYS_MAR;
b02d0177 MK	90
	91	/*
	92	* Map controller bank 1 to the SDRAM bank at preliminary address.
	93	*/
6d0f6bcf JCPV	94	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
6d0f6bcf JCPV	95	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
b02d0177 MK	96
b02d0177 MK	97	/* initialize memory address register */
6d0f6bcf	98	memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; /* refresh not enabled yet */
b02d0177 MK	99
	100	/* mode initialization (offset 5) */
	101	udelay (200); /* 0x80006105 */
	102	memctl->memc_mcr = MCR_OP_RUN \| MCR_UPM_B \| MCR_MB_CS1 \| MCR_MLCF (1) \| MCR_MAD (0x05);
	103
	104	/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
	105	udelay (1); /* 0x80006130 */
	106	memctl->memc_mcr = MCR_OP_RUN \| MCR_UPM_B \| MCR_MB_CS1 \| MCR_MLCF (1) \| MCR_MAD (0x30);
	107	udelay (1); /* 0x80006130 */
	108	memctl->memc_mcr = MCR_OP_RUN \| MCR_UPM_B \| MCR_MB_CS1 \| MCR_MLCF (1) \| MCR_MAD (0x30);
	109	udelay (1); /* 0x80006106 */
	110	memctl->memc_mcr = MCR_OP_RUN \| MCR_UPM_B \| MCR_MB_CS1 \| MCR_MLCF (1) \| MCR_MAD (0x06);
	111
	112	memctl->memc_mbmr \|= MBMR_PTBE; /* refresh enabled */
	113
	114	udelay (200);
	115
	116	/* Need at least 10 DRAM accesses to stabilize */
	117	for (i = 0; i < 10; ++i) {
	118	volatile unsigned long *addr =
6d0f6bcf	119	(volatile unsigned long *) CONFIG_SYS_SDRAM_BASE;
b02d0177 MK	120	unsigned long val;
	121
	122	val = *(addr + i);
	123	*(addr + i) = val;
	124	}
	125
	126	/*
	127	* Check Bank 0 Memory Size for re-configuration
	128	*
	129	* try 8 column mode
	130	*/
6d0f6bcf	131	size8 = dram_size (CONFIG_SYS_MBMR_8COL, (long *)CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE);
b02d0177 MK	132
	133	udelay (1000);
	134
	135	/*
	136	* try 9 column mode
	137	*/
6d0f6bcf	138	size9 = dram_size (CONFIG_SYS_MBMR_9COL, (long *)CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE);
b02d0177 MK	139
	140	if (size8 < size9) { /* leave configuration at 9 columns */
	141	size_b0 = size9;
6d0f6bcf	142	memctl->memc_mbmr = CONFIG_SYS_MBMR_9COL \| MBMR_PTBE;
b02d0177 MK	143	udelay (500);
	144	} else { /* back to 8 columns */
	145	size_b0 = size8;
6d0f6bcf	146	memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL \| MBMR_PTBE;
b02d0177 MK	147	udelay (500);
	148	}
	149
	150	/*
	151	* Final mapping:
	152	*/
	153
	154	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) \|
	155	OR_CSNT_SAM \| OR_G5LS \| SDRAM_TIMING;
6d0f6bcf	156	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) \| BR_MS_UPMB \| BR_V;
b02d0177 MK	157	udelay (1000);
b02d0177 MK	158
d28707db MK	159	/* initalize the DSP Host Port Interface */
d28707db MK	160	hpi_init();
b02d0177	161
67fea022	162	/* FRAM Setup */
6d0f6bcf JCPV	163	memctl->memc_or4 = CONFIG_SYS_OR4;
6d0f6bcf JCPV	164	memctl->memc_br4 = CONFIG_SYS_BR4;
b02d0177 MK	165	udelay(1000);
	166
	167	return (size_b0);
	168	}
	169
	170	/*
	171	* Check memory range for valid RAM. A simple memory test determines
	172	* the actually available RAM size between addresses `base' and
	173	* `base + maxsize'. Some (not all) hardware errors are detected:
	174	* - short between address lines
	175	* - short between data lines
	176	*/
	177	static long int dram_size (long int mbmr_value, long int *base,
	178	long int maxsize)
	179	{
6d0f6bcf	180	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
b02d0177 MK	181	volatile memctl8xx_t *memctl = &immap->im_memctl;
	182
	183	memctl->memc_mbmr = mbmr_value;
	184
	185	return (get_ram_size (base, maxsize));
	186	}
	187
	188
	189	/*********** other stuff ****************/
	190
	191
	192	int board_early_init_f(void)
	193	{
6d0f6bcf	194	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
b02d0177	195
e4c2d37a MK	196	/* Set Go/NoGo led (PA15) to color red */
	197	immap->im_ioport.iop_papar &= ~0x1;
	198	immap->im_ioport.iop_paodr &= ~0x1;
	199	immap->im_ioport.iop_padir \|= 0x1;
	200	immap->im_ioport.iop_padat \|= 0x1;
b02d0177	201
e4c2d37a	202	#if 0
b02d0177 MK	203	/* Turn on LED PD9 */
	204	immap->im_ioport.iop_pdpar &= ~(0x0040);
	205	immap->im_ioport.iop_pddir \|= 0x0040;
	206	immap->im_ioport.iop_pddat \|= 0x0040;
e4c2d37a MK	207	#endif
e4c2d37a MK	208
5921e531 MK	209	/*
	210	* Enable console on SMC1. This requires turning on
	211	* the com2_en signal and SMC1_DISABLE
	212	*/
	213
	214	/* SMC1_DISABLE: PB17 */
	215	immap->im_cpm.cp_pbodr &= ~0x4000;
	216	immap->im_cpm.cp_pbpar &= ~0x4000;
	217	immap->im_cpm.cp_pbdir \|= 0x4000;
	218	immap->im_cpm.cp_pbdat &= ~0x4000;
	219
	220	/* COM2_EN: PD10 */
b02d0177 MK	221	immap->im_ioport.iop_pdpar &= ~0x0020;
	222	immap->im_ioport.iop_pddir &= ~0x4000;
	223	immap->im_ioport.iop_pddir \|= 0x0020;
	224	immap->im_ioport.iop_pddat \|= 0x0020;
	225
	226
6d0f6bcf	227	#ifdef CONFIG_SYS_SMC1_PLD_CLK4 /* SMC1 uses CLK4 from PLD */
b02d0177 MK	228	immap->im_cpm.cp_simode \|= 0x7000;
	229	immap->im_cpm.cp_simode &= ~(0x8000);
	230	#endif
	231
	232	return 0;
	233	}
	234
d28707db MK	235	int last_stage_init(void)
	236	{
	237	#ifdef CONFIG_SPC1920_HPI_TEST
	238	printf("CMB1920 Host Port Interface Test: %s\n",
	239	hpi_test() ? "Failed!" : "OK");
	240	#endif
	241	return 0;
	242	}
b02d0177 MK	243
	244	int checkboard (void)
	245	{
	246	puts("Board: SPC1920\n");
	247	return 0;
	248	}