[thirdparty/u-boot.git] / board / st / common / stpmic1.c

// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
 * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
 */

#define LOG_CATEGORY LOGC_BOARD

#include <common.h>
#include <dm.h>
#include <log.h>
#include <asm/io.h>
#include <asm/arch/ddr.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <power/pmic.h>
#include <power/stpmic1.h>

int board_ddr_power_init(enum ddr_type ddr_type)
{
	struct udevice *dev;
	bool buck3_at_1800000v = false;
	int ret;
	u32 buck2;

	ret = uclass_get_device_by_driver(UCLASS_PMIC,
					  DM_DRIVER_GET(pmic_stpmic1), &dev);
	if (ret)
		/* No PMIC on board */
		return 0;

	switch (ddr_type) {
	case STM32MP_DDR3:
		/* VTT = Set LDO3 to sync mode */
		ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
		if (ret < 0)
			return ret;

		ret &= ~STPMIC1_LDO3_MODE;
		ret &= ~STPMIC1_LDO12356_VOUT_MASK;
		ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);

		ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
				     ret);
		if (ret < 0)
			return ret;

		/* VDD_DDR = Set BUCK2 to 1.35V */
		ret = pmic_clrsetbits(dev,
				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
				      STPMIC1_BUCK_VOUT_MASK,
				      STPMIC1_BUCK2_1350000V);
		if (ret < 0)
			return ret;

		/* Enable VDD_DDR = BUCK2 */
		ret = pmic_clrsetbits(dev,
				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
				      STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
		if (ret < 0)
			return ret;

		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);

		/* Enable VREF */
		ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
				      STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
		if (ret < 0)
			return ret;

		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);

		/* Enable VTT = LDO3 */
		ret = pmic_clrsetbits(dev,
				      STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
				      STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
		if (ret < 0)
			return ret;

		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);

		break;

	case STM32MP_LPDDR2_16:
	case STM32MP_LPDDR2_32:
	case STM32MP_LPDDR3_16:
	case STM32MP_LPDDR3_32:
		/*
		 * configure VDD_DDR1 = LDO3
		 * Set LDO3 to 1.8V
		 * + bypass mode if BUCK3 = 1.8V
		 * + normal mode if BUCK3 != 1.8V
		 */
		ret = pmic_reg_read(dev,
				    STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK3));
		if (ret < 0)
			return ret;

		if ((ret & STPMIC1_BUCK3_1800000V) == STPMIC1_BUCK3_1800000V)
			buck3_at_1800000v = true;

		ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
		if (ret < 0)
			return ret;

		ret &= ~STPMIC1_LDO3_MODE;
		ret &= ~STPMIC1_LDO12356_VOUT_MASK;
		ret |= STPMIC1_LDO3_1800000;
		if (buck3_at_1800000v)
			ret |= STPMIC1_LDO3_MODE;

		ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
				     ret);
		if (ret < 0)
			return ret;

		/* VDD_DDR2 : Set BUCK2 to 1.2V (16bits) or 1.25V (32 bits)*/
		switch (ddr_type) {
		case STM32MP_LPDDR2_32:
		case STM32MP_LPDDR3_32:
			buck2 = STPMIC1_BUCK2_1250000V;
			break;
		default:
		case STM32MP_LPDDR2_16:
		case STM32MP_LPDDR3_16:
			buck2 = STPMIC1_BUCK2_1200000V;
			break;
		}

		ret = pmic_clrsetbits(dev,
				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
				      STPMIC1_BUCK_VOUT_MASK,
				      buck2);
		if (ret < 0)
			return ret;

		/* Enable VDD_DDR1 = LDO3 */
		ret = pmic_clrsetbits(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
				      STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
		if (ret < 0)
			return ret;

		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);

		/* Enable VDD_DDR2 =BUCK2 */
		ret = pmic_clrsetbits(dev,
				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
				      STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
		if (ret < 0)
			return ret;

		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);

		/* Enable VREF */
		ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
				      STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
		if (ret < 0)
			return ret;

		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);

		break;

	default:
		break;
	};

	return 0;
}

static int stmpic_buck1_set(struct udevice *dev, u32 voltage_mv)
{
	u32 value;

	/* VDDCORE= STMPCI1 BUCK1 ramp=+25mV, 5 => 725mV, 36 => 1500mV */
	value = ((voltage_mv - 725) / 25) + 5;
	if (value < 5)
		value = 5;
	if (value > 36)
		value = 36;

	return pmic_clrsetbits(dev,
			       STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK1),
			       STPMIC1_BUCK_VOUT_MASK,
			       STPMIC1_BUCK_VOUT(value));
}

/* early init of PMIC */
struct udevice *stpmic1_init(u32 voltage_mv)
{
	struct udevice *dev;

	if (uclass_get_device_by_driver(UCLASS_PMIC,
					DM_DRIVER_GET(pmic_stpmic1), &dev))
		return NULL;

	/* update VDDCORE = BUCK1 */
	if (voltage_mv)
		stmpic_buck1_set(dev, voltage_mv);

	return dev;
}
Commit	Line	Data
918e9c3d PD	1	// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
	2	/*
	3	* Copyright (C) 2020, STMicroelectronics - All Rights Reserved
	4	*/
	5
705b5bf9 PD	6	#define LOG_CATEGORY LOGC_BOARD
705b5bf9 PD	7
d678a59d	8	#include <common.h>
918e9c3d	9	#include <dm.h>
705b5bf9	10	#include <log.h>
d1a4b09d	11	#include <asm/io.h>
918e9c3d PD	12	#include <asm/arch/ddr.h>
	13	#include <linux/bitops.h>
	14	#include <linux/delay.h>
	15	#include <power/pmic.h>
	16	#include <power/stpmic1.h>
	17
	18	int board_ddr_power_init(enum ddr_type ddr_type)
	19	{
	20	struct udevice *dev;
	21	bool buck3_at_1800000v = false;
	22	int ret;
	23	u32 buck2;
	24
	25	ret = uclass_get_device_by_driver(UCLASS_PMIC,
65e25bea	26	DM_DRIVER_GET(pmic_stpmic1), &dev);
918e9c3d PD	27	if (ret)
	28	/* No PMIC on board */
	29	return 0;
	30
	31	switch (ddr_type) {
	32	case STM32MP_DDR3:
	33	/* VTT = Set LDO3 to sync mode */
	34	ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
	35	if (ret < 0)
	36	return ret;
	37
	38	ret &= ~STPMIC1_LDO3_MODE;
	39	ret &= ~STPMIC1_LDO12356_VOUT_MASK;
	40	ret \|= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
	41
	42	ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
	43	ret);
	44	if (ret < 0)
	45	return ret;
	46
	47	/* VDD_DDR = Set BUCK2 to 1.35V */
	48	ret = pmic_clrsetbits(dev,
	49	STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
	50	STPMIC1_BUCK_VOUT_MASK,
	51	STPMIC1_BUCK2_1350000V);
	52	if (ret < 0)
	53	return ret;
	54
	55	/* Enable VDD_DDR = BUCK2 */
	56	ret = pmic_clrsetbits(dev,
	57	STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
	58	STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
	59	if (ret < 0)
	60	return ret;
	61
	62	mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
	63
	64	/* Enable VREF */
	65	ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
	66	STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
	67	if (ret < 0)
	68	return ret;
	69
	70	mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
	71
	72	/* Enable VTT = LDO3 */
	73	ret = pmic_clrsetbits(dev,
	74	STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
	75	STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
	76	if (ret < 0)
	77	return ret;
	78
	79	mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
	80
	81	break;
	82
	83	case STM32MP_LPDDR2_16:
	84	case STM32MP_LPDDR2_32:
	85	case STM32MP_LPDDR3_16:
	86	case STM32MP_LPDDR3_32:
	87	/*
	88	* configure VDD_DDR1 = LDO3
	89	* Set LDO3 to 1.8V
	90	* + bypass mode if BUCK3 = 1.8V
91	* + normal mode if BUCK3 != 1.8V
92	*/
93	ret = pmic_reg_read(dev,
94	STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK3));
95	if (ret < 0)
96	return ret;
97
98	if ((ret & STPMIC1_BUCK3_1800000V) == STPMIC1_BUCK3_1800000V)
99	buck3_at_1800000v = true;
100
101	ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
102	if (ret < 0)
103	return ret;
104
105	ret &= ~STPMIC1_LDO3_MODE;
106	ret &= ~STPMIC1_LDO12356_VOUT_MASK;
107	ret \|= STPMIC1_LDO3_1800000;
108	if (buck3_at_1800000v)
109	ret \|= STPMIC1_LDO3_MODE;
110
111	ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
112	ret);
113	if (ret < 0)
114	return ret;
115
116	/* VDD_DDR2 : Set BUCK2 to 1.2V (16bits) or 1.25V (32 bits)*/
117	switch (ddr_type) {
118	case STM32MP_LPDDR2_32:
119	case STM32MP_LPDDR3_32:
120	buck2 = STPMIC1_BUCK2_1250000V;
121	break;
122	default:
123	case STM32MP_LPDDR2_16:
124	case STM32MP_LPDDR3_16:
125	buck2 = STPMIC1_BUCK2_1200000V;
126	break;
127	}
128
129	ret = pmic_clrsetbits(dev,
130	STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
131	STPMIC1_BUCK_VOUT_MASK,
132	buck2);
133	if (ret < 0)
134	return ret;
135
136	/* Enable VDD_DDR1 = LDO3 */
137	ret = pmic_clrsetbits(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
138	STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
139	if (ret < 0)
140	return ret;
141
142	mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
143
144	/* Enable VDD_DDR2 =BUCK2 */
145	ret = pmic_clrsetbits(dev,
146	STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
147	STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
148	if (ret < 0)
149	return ret;
150
151	mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
152
153	/* Enable VREF */
154	ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
155	STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
156	if (ret < 0)
157	return ret;
158
159	mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
160
161	break;
162
163	default:
164	break;
165	};
166
167	return 0;
168	}
d1a4b09d	169
2f238327 PD	170	static int stmpic_buck1_set(struct udevice *dev, u32 voltage_mv)
	171	{
	172	u32 value;
	173
	174	/* VDDCORE= STMPCI1 BUCK1 ramp=+25mV, 5 => 725mV, 36 => 1500mV */
	175	value = ((voltage_mv - 725) / 25) + 5;
	176	if (value < 5)
	177	value = 5;
	178	if (value > 36)
	179	value = 36;
	180
	181	return pmic_clrsetbits(dev,
	182	STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK1),
	183	STPMIC1_BUCK_VOUT_MASK,
	184	STPMIC1_BUCK_VOUT(value));
	185	}
	186
d1a4b09d	187	/* early init of PMIC */
b3d97f8c	188	struct udevice *stpmic1_init(u32 voltage_mv)
d1a4b09d PD	189	{
	190	struct udevice *dev;
	191
	192	if (uclass_get_device_by_driver(UCLASS_PMIC,
65e25bea	193	DM_DRIVER_GET(pmic_stpmic1), &dev))
b3d97f8c	194	return NULL;
d1a4b09d	195
2f238327 PD	196	/* update VDDCORE = BUCK1 */
	197	if (voltage_mv)
	198	stmpic_buck1_set(dev, voltage_mv);
	199
b3d97f8c	200	return dev;
d1a4b09d	201	}