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7abf0c58 WD |
1 | /* |
2 | * (C) Copyright 2003, Embedded Edge, LLC | |
3 | * Dan Malek, <dan@embeddededge.com> | |
4 | * Copied from ADS85xx. | |
5 | * Updates for Silicon Tx GP3 8560 | |
6 | * | |
7 | * (C) Copyright 2003,Motorola Inc. | |
8 | * Xianghua Xiao, (X.Xiao@motorola.com) | |
9 | * | |
10 | * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> | |
11 | * | |
12 | * See file CREDITS for list of people who contributed to this | |
13 | * project. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License as | |
17 | * published by the Free Software Foundation; either version 2 of | |
18 | * the License, or (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
28 | * MA 02111-1307 USA | |
29 | */ | |
30 | ||
31 | ||
7abf0c58 | 32 | #include <common.h> |
9aea9530 | 33 | #include <pci.h> |
7abf0c58 | 34 | #include <asm/processor.h> |
c360d9b9 | 35 | #include <asm/mmu.h> |
7abf0c58 | 36 | #include <asm/immap_85xx.h> |
c360d9b9 | 37 | #include <asm/fsl_ddr_sdram.h> |
7abf0c58 WD |
38 | #include <ioports.h> |
39 | #include <asm/io.h> | |
a30a549a | 40 | #include <spd_sdram.h> |
7abf0c58 WD |
41 | #include <miiphy.h> |
42 | ||
43 | long int fixed_sdram (void); | |
44 | ||
45 | /* | |
46 | * I/O Port configuration table | |
47 | * | |
48 | * if conf is 1, then that port pin will be configured at boot time | |
49 | * according to the five values podr/pdir/ppar/psor/pdat for that entry | |
50 | */ | |
51 | ||
52 | const iop_conf_t iop_conf_tab[4][32] = { | |
53 | ||
54 | /* Port A configuration */ | |
55 | { /* conf ppar psor pdir podr pdat */ | |
56 | /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ | |
57 | /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ | |
58 | /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ | |
59 | /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ | |
60 | /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ | |
61 | /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ | |
62 | /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ | |
63 | /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ | |
64 | /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ | |
65 | /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ | |
66 | /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ | |
67 | /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ | |
68 | /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ | |
69 | /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ | |
70 | /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ | |
71 | /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ | |
72 | /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ | |
73 | /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ | |
74 | /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ | |
75 | /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ | |
76 | /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ | |
77 | /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ | |
78 | /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ | |
79 | /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ | |
80 | /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ | |
81 | /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ | |
82 | /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ | |
83 | /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ | |
84 | /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ | |
85 | /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ | |
86 | /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ | |
87 | /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ | |
88 | }, | |
89 | ||
90 | /* Port B configuration */ | |
91 | { /* conf ppar psor pdir podr pdat */ | |
92 | /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ | |
93 | /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ | |
94 | /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ | |
95 | /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ | |
96 | /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ | |
97 | /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ | |
98 | /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ | |
99 | /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ | |
100 | /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ | |
101 | /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ | |
102 | /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ | |
103 | /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ | |
104 | /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ | |
105 | /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ | |
106 | /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ | |
107 | /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ | |
108 | /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ | |
109 | /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ | |
110 | /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ | |
111 | /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ | |
112 | /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ | |
113 | /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ | |
114 | /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ | |
115 | /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ | |
116 | /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ | |
117 | /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ | |
118 | /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ | |
119 | /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ | |
120 | /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
121 | /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
122 | /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
123 | /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ | |
124 | }, | |
125 | ||
126 | /* Port C */ | |
127 | { /* conf ppar psor pdir podr pdat */ | |
128 | /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ | |
129 | /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ | |
130 | /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ | |
131 | /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ | |
132 | /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ | |
133 | /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ | |
134 | /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ | |
135 | /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ | |
136 | /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ | |
137 | /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ | |
138 | /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ | |
139 | /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ | |
140 | /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ | |
141 | /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ | |
142 | /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ | |
143 | /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ | |
144 | /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */ | |
145 | /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ | |
146 | /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ | |
147 | /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ | |
148 | /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ | |
149 | /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */ | |
150 | /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */ | |
151 | /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ | |
152 | /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ | |
153 | /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ | |
154 | /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ | |
155 | /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ | |
156 | /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ | |
157 | /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ | |
158 | /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ | |
159 | /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ | |
160 | }, | |
161 | ||
162 | /* Port D */ | |
163 | { /* conf ppar psor pdir podr pdat */ | |
164 | /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ | |
165 | /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ | |
166 | /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ | |
167 | /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */ | |
168 | /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */ | |
169 | /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ | |
170 | /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ | |
171 | /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ | |
172 | /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ | |
173 | /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ | |
174 | /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ | |
175 | /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ | |
176 | /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ | |
177 | /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ | |
178 | /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ | |
179 | /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ | |
180 | /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ | |
181 | /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */ | |
182 | /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ | |
183 | /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ | |
184 | /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ | |
185 | /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ | |
186 | /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ | |
187 | /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ | |
188 | /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ | |
189 | /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ | |
190 | /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ | |
191 | /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ | |
192 | /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
193 | /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
194 | /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
195 | /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ | |
196 | } | |
197 | }; | |
198 | ||
7abf0c58 WD |
199 | static uint64_t next_led_update; |
200 | static uint led_bit; | |
201 | ||
9aea9530 WD |
202 | int |
203 | board_early_init_f(void) | |
7abf0c58 WD |
204 | { |
205 | #if defined(CONFIG_PCI) | |
6d0f6bcf | 206 | volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR); |
7abf0c58 WD |
207 | |
208 | pci->peer &= 0xfffffffdf; /* disable master abort */ | |
209 | #endif | |
210 | return 0; | |
211 | } | |
212 | ||
9aea9530 WD |
213 | void |
214 | reset_phy(void) | |
7abf0c58 WD |
215 | { |
216 | volatile uint *blatch; | |
217 | ||
6d0f6bcf | 218 | blatch = (volatile uint *)CONFIG_SYS_LBC_LCLDEVS_BASE; |
7abf0c58 WD |
219 | |
220 | /* reset Giga bit Ethernet port if needed here */ | |
221 | ||
222 | *blatch &= ~0x000000c0; | |
223 | udelay(100); | |
224 | *blatch = 0x000000c1; /* Light one led, too */ | |
225 | udelay(1000); | |
226 | ||
227 | #if 0 /* This is the port we really want to use for debugging. */ | |
228 | /* reset the CPM FEC port */ | |
229 | #if (CONFIG_ETHER_INDEX == 2) | |
230 | bcsr->bcsr2 &= ~FETH2_RST; | |
231 | udelay(2); | |
232 | bcsr->bcsr2 |= FETH2_RST; | |
233 | udelay(1000); | |
234 | #elif (CONFIG_ETHER_INDEX == 3) | |
235 | bcsr->bcsr3 &= ~FETH3_RST; | |
236 | udelay(2); | |
237 | bcsr->bcsr3 |= FETH3_RST; | |
238 | udelay(1000); | |
239 | #endif | |
240 | #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) | |
63ff004c MB |
241 | /* reset PHY */ |
242 | miiphy_reset("FCC1 ETHERNET", 0x0); | |
243 | ||
244 | /* change PHY address to 0x02 */ | |
245 | bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028); | |
246 | ||
247 | bb_miiphy_write(NULL, 0x02, PHY_BMCR, | |
248 | PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); | |
7abf0c58 WD |
249 | #endif /* CONFIG_MII */ |
250 | #endif | |
251 | } | |
252 | ||
9aea9530 WD |
253 | int |
254 | checkboard(void) | |
7abf0c58 | 255 | { |
7abf0c58 | 256 | printf ("Board: Silicon Tx GPPP 8560 Board\n"); |
7abf0c58 WD |
257 | return (0); |
258 | } | |
259 | ||
260 | /* Blinkin' LEDS for Robert. | |
261 | */ | |
262 | void | |
263 | show_activity(int flag) | |
264 | { | |
265 | volatile uint *blatch; | |
266 | ||
267 | if (next_led_update > get_ticks()) | |
268 | return; | |
269 | ||
6d0f6bcf | 270 | blatch = (volatile uint *)CONFIG_SYS_LBC_LCLDEVS_BASE; |
7abf0c58 WD |
271 | |
272 | led_bit >>= 1; | |
273 | if (led_bit == 0) | |
274 | led_bit = 0x08; | |
275 | *blatch = (0xc0 | led_bit); | |
276 | eieio(); | |
277 | next_led_update += (get_tbclk() / 4); | |
278 | } | |
279 | ||
9973e3c6 | 280 | phys_size_t |
9aea9530 | 281 | initdram (int board_type) |
7abf0c58 WD |
282 | { |
283 | long dram_size = 0; | |
7abf0c58 WD |
284 | |
285 | #if defined(CONFIG_DDR_DLL) | |
9aea9530 | 286 | { |
6d0f6bcf | 287 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
9aea9530 | 288 | uint temp_ddrdll = 0; |
7abf0c58 | 289 | |
9aea9530 WD |
290 | /* Work around to stabilize DDR DLL */ |
291 | temp_ddrdll = gur->ddrdllcr; | |
292 | gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; | |
293 | asm("sync;isync;msync"); | |
294 | } | |
7abf0c58 WD |
295 | #endif |
296 | ||
c360d9b9 KG |
297 | dram_size = fsl_ddr_sdram(); |
298 | dram_size = setup_ddr_tlbs(dram_size / 0x100000); | |
299 | dram_size *= 0x100000; | |
7abf0c58 WD |
300 | |
301 | #if defined(CONFIG_DDR_ECC) | |
9aea9530 WD |
302 | /* Initialize and enable DDR ECC. |
303 | */ | |
304 | ddr_enable_ecc(dram_size); | |
7abf0c58 WD |
305 | #endif |
306 | ||
307 | return dram_size; | |
308 | } | |
309 | ||
310 | ||
6d0f6bcf | 311 | #if defined(CONFIG_SYS_DRAM_TEST) |
7abf0c58 WD |
312 | int testdram (void) |
313 | { | |
6d0f6bcf JCPV |
314 | uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; |
315 | uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; | |
7abf0c58 WD |
316 | uint *p; |
317 | ||
318 | printf("SDRAM test phase 1:\n"); | |
319 | for (p = pstart; p < pend; p++) | |
320 | *p = 0xaaaaaaaa; | |
321 | ||
322 | for (p = pstart; p < pend; p++) { | |
323 | if (*p != 0xaaaaaaaa) { | |
324 | printf ("SDRAM test fails at: %08x\n", (uint) p); | |
325 | return 1; | |
326 | } | |
327 | } | |
328 | ||
329 | printf("SDRAM test phase 2:\n"); | |
330 | for (p = pstart; p < pend; p++) | |
331 | *p = 0x55555555; | |
332 | ||
333 | for (p = pstart; p < pend; p++) { | |
334 | if (*p != 0x55555555) { | |
335 | printf ("SDRAM test fails at: %08x\n", (uint) p); | |
336 | return 1; | |
337 | } | |
338 | } | |
339 | ||
340 | printf("SDRAM test passed.\n"); | |
341 | return 0; | |
342 | } | |
343 | #endif | |
344 | ||
9aea9530 WD |
345 | #if defined(CONFIG_PCI) |
346 | ||
347 | /* | |
348 | * Initialize PCI Devices, report devices found. | |
349 | */ | |
350 | ||
351 | #ifndef CONFIG_PCI_PNP | |
352 | static struct pci_config_table pci_stxgp3_config_table[] = { | |
353 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
354 | PCI_IDSEL_NUMBER, PCI_ANY_ID, | |
355 | pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, | |
356 | PCI_ENET0_MEMADDR, | |
357 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | |
358 | } }, | |
359 | { } | |
360 | }; | |
361 | #endif | |
362 | ||
363 | ||
364 | static struct pci_controller hose = { | |
365 | #ifndef CONFIG_PCI_PNP | |
366 | config_table: pci_stxgp3_config_table, | |
367 | #endif | |
368 | }; | |
369 | ||
370 | #endif /* CONFIG_PCI */ | |
371 | ||
372 | ||
373 | void | |
374 | pci_init_board(void) | |
7abf0c58 | 375 | { |
9aea9530 | 376 | #ifdef CONFIG_PCI |
9aea9530 WD |
377 | pci_mpc85xx_init(&hose); |
378 | #endif /* CONFIG_PCI */ | |
7abf0c58 | 379 | } |