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Commit | Line | Data |
---|---|---|
2c7e3b90 IC |
1 | if ARCH_SUNXI |
2 | ||
53b5bf3c SG |
3 | config SPL_GPIO_SUPPORT |
4 | default y | |
5 | ||
77d2f7f5 SG |
6 | config SPL_LIBCOMMON_SUPPORT |
7 | default y | |
8 | ||
1646eba8 SG |
9 | config SPL_LIBDISK_SUPPORT |
10 | default y | |
11 | ||
cc4288ef SG |
12 | config SPL_LIBGENERIC_SUPPORT |
13 | default y | |
14 | ||
1fdf7c64 SG |
15 | config SPL_MMC_SUPPORT |
16 | default y | |
17 | ||
2253797d SG |
18 | config SPL_POWER_SUPPORT |
19 | default y | |
20 | ||
e00f76ce SG |
21 | config SPL_SERIAL_SUPPORT |
22 | default y | |
23 | ||
44d8ae5b HG |
24 | # Note only one of these may be selected at a time! But hidden choices are |
25 | # not supported by Kconfig | |
26 | config SUNXI_GEN_SUN4I | |
27 | bool | |
28 | ---help--- | |
29 | Select this for sunxi SoCs which have resets and clocks set up | |
30 | as the original A10 (mach-sun4i). | |
31 | ||
32 | config SUNXI_GEN_SUN6I | |
33 | bool | |
34 | ---help--- | |
35 | Select this for sunxi SoCs which have sun6i like periphery, like | |
36 | separate ahb reset control registers, custom pmic bus, new style | |
37 | watchdog, etc. | |
38 | ||
39 | ||
2c7e3b90 IC |
40 | choice |
41 | prompt "Sunxi SoC Variant" | |
3da9536e | 42 | optional |
2c7e3b90 | 43 | |
c3be2793 | 44 | config MACH_SUN4I |
2c7e3b90 IC |
45 | bool "sun4i (Allwinner A10)" |
46 | select CPU_V7 | |
44d8ae5b | 47 | select SUNXI_GEN_SUN4I |
2c7e3b90 IC |
48 | select SUPPORT_SPL |
49 | ||
c3be2793 | 50 | config MACH_SUN5I |
2c7e3b90 IC |
51 | bool "sun5i (Allwinner A13)" |
52 | select CPU_V7 | |
44d8ae5b | 53 | select SUNXI_GEN_SUN4I |
2c7e3b90 IC |
54 | select SUPPORT_SPL |
55 | ||
c3be2793 | 56 | config MACH_SUN6I |
2c7e3b90 IC |
57 | bool "sun6i (Allwinner A31)" |
58 | select CPU_V7 | |
cc08ea4c CYT |
59 | select CPU_V7_HAS_NONSEC |
60 | select CPU_V7_HAS_VIRT | |
217f92bb | 61 | select ARCH_SUPPORT_PSCI |
44d8ae5b | 62 | select SUNXI_GEN_SUN6I |
8c2c9cfa | 63 | select SUPPORT_SPL |
cc08ea4c | 64 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
2c7e3b90 | 65 | |
c3be2793 | 66 | config MACH_SUN7I |
2c7e3b90 IC |
67 | bool "sun7i (Allwinner A20)" |
68 | select CPU_V7 | |
ea624e19 HG |
69 | select CPU_V7_HAS_NONSEC |
70 | select CPU_V7_HAS_VIRT | |
217f92bb | 71 | select ARCH_SUPPORT_PSCI |
44d8ae5b | 72 | select SUNXI_GEN_SUN4I |
2c7e3b90 | 73 | select SUPPORT_SPL |
b366fb92 | 74 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
2c7e3b90 | 75 | |
5e6bacdb | 76 | config MACH_SUN8I_A23 |
2c7e3b90 IC |
77 | bool "sun8i (Allwinner A23)" |
78 | select CPU_V7 | |
014414f5 CYT |
79 | select CPU_V7_HAS_NONSEC |
80 | select CPU_V7_HAS_VIRT | |
217f92bb | 81 | select ARCH_SUPPORT_PSCI |
44d8ae5b | 82 | select SUNXI_GEN_SUN6I |
08fd1479 | 83 | select SUPPORT_SPL |
014414f5 | 84 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
2c7e3b90 | 85 | |
8c3dacff VP |
86 | config MACH_SUN8I_A33 |
87 | bool "sun8i (Allwinner A33)" | |
88 | select CPU_V7 | |
014414f5 CYT |
89 | select CPU_V7_HAS_NONSEC |
90 | select CPU_V7_HAS_VIRT | |
217f92bb | 91 | select ARCH_SUPPORT_PSCI |
8c3dacff VP |
92 | select SUNXI_GEN_SUN6I |
93 | select SUPPORT_SPL | |
014414f5 | 94 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
8c3dacff | 95 | |
a81b7995 CYT |
96 | config MACH_SUN8I_A83T |
97 | bool "sun8i (Allwinner A83T)" | |
98 | select CPU_V7 | |
99 | select SUNXI_GEN_SUN6I | |
100 | select SUPPORT_SPL | |
101 | ||
1c27b7dc JK |
102 | config MACH_SUN8I_H3 |
103 | bool "sun8i (Allwinner H3)" | |
104 | select CPU_V7 | |
853f6d1e CYT |
105 | select CPU_V7_HAS_NONSEC |
106 | select CPU_V7_HAS_VIRT | |
217f92bb | 107 | select ARCH_SUPPORT_PSCI |
1c27b7dc | 108 | select SUNXI_GEN_SUN6I |
0404d53f | 109 | select SUPPORT_SPL |
853f6d1e | 110 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
1c27b7dc | 111 | |
1871a8ca HG |
112 | config MACH_SUN9I |
113 | bool "sun9i (Allwinner A80)" | |
114 | select CPU_V7 | |
115 | select SUNXI_GEN_SUN6I | |
116 | ||
a81b7995 CYT |
117 | config MACH_SUN50I |
118 | bool "sun50i (Allwinner A64)" | |
119 | select ARM64 | |
120 | select SUNXI_GEN_SUN6I | |
121 | ||
2c7e3b90 | 122 | endchoice |
8a6564da | 123 | |
5e6bacdb HG |
124 | # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" |
125 | config MACH_SUN8I | |
126 | bool | |
762e24a0 | 127 | default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T |
5e6bacdb | 128 | |
f5fd8caf VP |
129 | config DRAM_TYPE |
130 | int "sunxi dram type" | |
131 | depends on MACH_SUN8I_A83T | |
132 | default 3 | |
133 | ---help--- | |
134 | Set the dram type, 3: DDR3, 7: LPDDR3 | |
5e6bacdb | 135 | |
37781a1a | 136 | config DRAM_CLK |
8ffc487c HG |
137 | int "sunxi dram clock speed" |
138 | default 312 if MACH_SUN6I || MACH_SUN8I | |
139 | default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I | |
37781a1a HG |
140 | ---help--- |
141 | Set the dram clock speed, valid range 240 - 480, must be a multiple | |
e1a0888e | 142 | of 24. |
37781a1a | 143 | |
47e3501a SS |
144 | if MACH_SUN5I || MACH_SUN7I |
145 | config DRAM_MBUS_CLK | |
146 | int "sunxi mbus clock speed" | |
147 | default 300 | |
148 | ---help--- | |
149 | Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. | |
150 | ||
151 | endif | |
152 | ||
37781a1a | 153 | config DRAM_ZQ |
8ffc487c HG |
154 | int "sunxi dram zq value" |
155 | default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I | |
156 | default 127 if MACH_SUN7I | |
37781a1a | 157 | ---help--- |
e1a0888e | 158 | Set the dram zq value. |
8ffc487c | 159 | |
8975cdf4 HG |
160 | config DRAM_ODT_EN |
161 | bool "sunxi dram odt enable" | |
162 | default n if !MACH_SUN8I_A23 | |
163 | default y if MACH_SUN8I_A23 | |
164 | ---help--- | |
165 | Select this to enable dram odt (on die termination). | |
166 | ||
8ffc487c HG |
167 | if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I |
168 | config DRAM_EMR1 | |
169 | int "sunxi dram emr1 value" | |
170 | default 0 if MACH_SUN4I | |
171 | default 4 if MACH_SUN5I || MACH_SUN7I | |
172 | ---help--- | |
e1a0888e | 173 | Set the dram controller emr1 value. |
d133647a | 174 | |
47e3501a SS |
175 | config DRAM_TPR3 |
176 | hex "sunxi dram tpr3 value" | |
177 | default 0 | |
178 | ---help--- | |
179 | Set the dram controller tpr3 parameter. This parameter configures | |
180 | the delay on the command lane and also phase shifts, which are | |
181 | applied for sampling incoming read data. The default value 0 | |
182 | means that no phase/delay adjustments are necessary. Properly | |
183 | configuring this parameter increases reliability at high DRAM | |
184 | clock speeds. | |
185 | ||
186 | config DRAM_DQS_GATING_DELAY | |
187 | hex "sunxi dram dqs_gating_delay value" | |
188 | default 0 | |
189 | ---help--- | |
190 | Set the dram controller dqs_gating_delay parmeter. Each byte | |
191 | encodes the DQS gating delay for each byte lane. The delay | |
192 | granularity is 1/4 cycle. For example, the value 0x05060606 | |
193 | means that the delay is 5 quarter-cycles for one lane (1.25 | |
194 | cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. | |
195 | The default value 0 means autodetection. The results of hardware | |
196 | autodetection are not very reliable and depend on the chip | |
197 | temperature (sometimes producing different results on cold start | |
198 | and warm reboot). But the accuracy of hardware autodetection | |
199 | is usually good enough, unless running at really high DRAM | |
200 | clocks speeds (up to 600MHz). If unsure, keep as 0. | |
201 | ||
d133647a SS |
202 | choice |
203 | prompt "sunxi dram timings" | |
204 | default DRAM_TIMINGS_VENDOR_MAGIC | |
205 | ---help--- | |
206 | Select the timings of the DDR3 chips. | |
207 | ||
208 | config DRAM_TIMINGS_VENDOR_MAGIC | |
209 | bool "Magic vendor timings from Android" | |
210 | ---help--- | |
211 | The same DRAM timings as in the Allwinner boot0 bootloader. | |
212 | ||
213 | config DRAM_TIMINGS_DDR3_1066F_1333H | |
214 | bool "JEDEC DDR3-1333H with down binning to DDR3-1066F" | |
215 | ---help--- | |
216 | Use the timings of the standard JEDEC DDR3-1066F speed bin for | |
217 | DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin | |
218 | for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips | |
219 | used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 | |
220 | or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm | |
221 | that down binning to DDR3-1066F is supported (because DDR3-1066F | |
222 | uses a bit faster timings than DDR3-1333H). | |
223 | ||
224 | config DRAM_TIMINGS_DDR3_800E_1066G_1333J | |
225 | bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J" | |
226 | ---help--- | |
227 | Use the timings of the slowest possible JEDEC speed bin for the | |
228 | selected DRAM_CLK. Depending on the DRAM_CLK value, it may be | |
229 | DDR3-800E, DDR3-1066G or DDR3-1333J. | |
230 | ||
231 | endchoice | |
232 | ||
37781a1a HG |
233 | endif |
234 | ||
8975cdf4 HG |
235 | if MACH_SUN8I_A23 |
236 | config DRAM_ODT_CORRECTION | |
237 | int "sunxi dram odt correction value" | |
238 | default 0 | |
239 | ---help--- | |
240 | Set the dram odt correction value (range -255 - 255). In allwinner | |
241 | fex files, this option is found in bits 8-15 of the u32 odt_en variable | |
242 | in the [dram] section. When bit 31 of the odt_en variable is set | |
243 | then the correction is negative. Usually the value for this is 0. | |
244 | endif | |
245 | ||
e71b422b | 246 | config SYS_CLK_FREQ |
d96ebc46 | 247 | default 816000000 if MACH_SUN50I |
e71b422b IP |
248 | default 912000000 if MACH_SUN7I |
249 | default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I | |
250 | ||
8a6564da | 251 | config SYS_CONFIG_NAME |
c3be2793 IC |
252 | default "sun4i" if MACH_SUN4I |
253 | default "sun5i" if MACH_SUN5I | |
254 | default "sun6i" if MACH_SUN6I | |
255 | default "sun7i" if MACH_SUN7I | |
256 | default "sun8i" if MACH_SUN8I | |
1871a8ca | 257 | default "sun9i" if MACH_SUN9I |
d96ebc46 | 258 | default "sun50i" if MACH_SUN50I |
dd84058d | 259 | |
dd84058d | 260 | config SYS_BOARD |
dd84058d MY |
261 | default "sunxi" |
262 | ||
263 | config SYS_SOC | |
dd84058d MY |
264 | default "sunxi" |
265 | ||
f0ce28e9 SS |
266 | config UART0_PORT_F |
267 | bool "UART0 on MicroSD breakout board" | |
f0ce28e9 SS |
268 | default n |
269 | ---help--- | |
270 | Repurpose the SD card slot for getting access to the UART0 serial | |
271 | console. Primarily useful only for low level u-boot debugging on | |
272 | tablets, where normal UART0 is difficult to access and requires | |
273 | device disassembly and/or soldering. As the SD card can't be used | |
274 | at the same time, the system can be only booted in the FEL mode. | |
275 | Only enable this if you really know what you are doing. | |
276 | ||
accc9e44 | 277 | config OLD_SUNXI_KERNEL_COMPAT |
ab65006b | 278 | bool "Enable workarounds for booting old kernels" |
accc9e44 HG |
279 | default n |
280 | ---help--- | |
281 | Set this to enable various workarounds for old kernels, this results in | |
282 | sub-optimal settings for newer kernels, only enable if needed. | |
283 | ||
44c79879 MR |
284 | config MMC |
285 | depends on !UART0_PORT_F | |
286 | default y if ARCH_SUNXI | |
287 | ||
cd82113a HG |
288 | config MMC0_CD_PIN |
289 | string "Card detect pin for mmc0" | |
acdab175 | 290 | default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I |
cd82113a HG |
291 | default "" |
292 | ---help--- | |
293 | Set the card detect pin for mmc0, leave empty to not use cd. This | |
294 | takes a string in the format understood by sunxi_name_to_gpio, e.g. | |
295 | PH1 for pin 1 of port H. | |
296 | ||
297 | config MMC1_CD_PIN | |
298 | string "Card detect pin for mmc1" | |
299 | default "" | |
300 | ---help--- | |
301 | See MMC0_CD_PIN help text. | |
302 | ||
303 | config MMC2_CD_PIN | |
304 | string "Card detect pin for mmc2" | |
305 | default "" | |
306 | ---help--- | |
307 | See MMC0_CD_PIN help text. | |
308 | ||
309 | config MMC3_CD_PIN | |
310 | string "Card detect pin for mmc3" | |
311 | default "" | |
312 | ---help--- | |
313 | See MMC0_CD_PIN help text. | |
314 | ||
8deacca9 PK |
315 | config MMC1_PINS |
316 | string "Pins for mmc1" | |
317 | default "" | |
318 | ---help--- | |
319 | Set the pins used for mmc1, when applicable. This takes a string in the | |
320 | format understood by sunxi_name_to_gpio_bank, e.g. PH for port H. | |
321 | ||
322 | config MMC2_PINS | |
323 | string "Pins for mmc2" | |
324 | default "" | |
325 | ---help--- | |
326 | See MMC1_PINS help text. | |
327 | ||
328 | config MMC3_PINS | |
329 | string "Pins for mmc3" | |
330 | default "" | |
331 | ---help--- | |
332 | See MMC1_PINS help text. | |
333 | ||
2ccfac01 HG |
334 | config MMC_SUNXI_SLOT_EXTRA |
335 | int "mmc extra slot number" | |
336 | default -1 | |
337 | ---help--- | |
338 | sunxi builds always enable mmc0, some boards also have a second sdcard | |
339 | slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable | |
340 | support for this. | |
341 | ||
2c3c3ecb HG |
342 | config INITIAL_USB_SCAN_DELAY |
343 | int "delay initial usb scan by x ms to allow builtin devices to init" | |
344 | default 0 | |
345 | ---help--- | |
346 | Some boards have on board usb devices which need longer than the | |
347 | USB spec's 1 second to connect from board powerup. Set this config | |
348 | option to a non 0 value to add an extra delay before the first usb | |
349 | bus scan. | |
350 | ||
4458b7a6 HG |
351 | config USB0_VBUS_PIN |
352 | string "Vbus enable pin for usb0 (otg)" | |
353 | default "" | |
354 | ---help--- | |
355 | Set the Vbus enable pin for usb0 (otg). This takes a string in the | |
356 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
357 | ||
52defe8f HG |
358 | config USB0_VBUS_DET |
359 | string "Vbus detect pin for usb0 (otg)" | |
52defe8f HG |
360 | default "" |
361 | ---help--- | |
362 | Set the Vbus detect pin for usb0 (otg). This takes a string in the | |
363 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
364 | ||
48c06c98 HG |
365 | config USB0_ID_DET |
366 | string "ID detect pin for usb0 (otg)" | |
367 | default "" | |
368 | ---help--- | |
369 | Set the ID detect pin for usb0 (otg). This takes a string in the | |
370 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
371 | ||
115200ce HG |
372 | config USB1_VBUS_PIN |
373 | string "Vbus enable pin for usb1 (ehci0)" | |
374 | default "PH6" if MACH_SUN4I || MACH_SUN7I | |
76946dfe | 375 | default "PH27" if MACH_SUN6I |
115200ce HG |
376 | ---help--- |
377 | Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes | |
378 | a string in the format understood by sunxi_name_to_gpio, e.g. | |
379 | PH1 for pin 1 of port H. | |
380 | ||
381 | config USB2_VBUS_PIN | |
382 | string "Vbus enable pin for usb2 (ehci1)" | |
383 | default "PH3" if MACH_SUN4I || MACH_SUN7I | |
76946dfe | 384 | default "PH24" if MACH_SUN6I |
115200ce HG |
385 | ---help--- |
386 | See USB1_VBUS_PIN help text. | |
387 | ||
60fa6301 HG |
388 | config USB3_VBUS_PIN |
389 | string "Vbus enable pin for usb3 (ehci2)" | |
390 | default "" | |
391 | ---help--- | |
392 | See USB1_VBUS_PIN help text. | |
393 | ||
6c739c5d PK |
394 | config I2C0_ENABLE |
395 | bool "Enable I2C/TWI controller 0" | |
396 | default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I | |
397 | default n if MACH_SUN6I || MACH_SUN8I | |
0878a8a7 | 398 | select CMD_I2C |
6c739c5d PK |
399 | ---help--- |
400 | This allows enabling I2C/TWI controller 0 by muxing its pins, enabling | |
401 | its clock and setting up the bus. This is especially useful on devices | |
402 | with slaves connected to the bus or with pins exposed through e.g. an | |
403 | expansion port/header. | |
404 | ||
405 | config I2C1_ENABLE | |
406 | bool "Enable I2C/TWI controller 1" | |
407 | default n | |
0878a8a7 | 408 | select CMD_I2C |
6c739c5d PK |
409 | ---help--- |
410 | See I2C0_ENABLE help text. | |
411 | ||
412 | config I2C2_ENABLE | |
413 | bool "Enable I2C/TWI controller 2" | |
414 | default n | |
0878a8a7 | 415 | select CMD_I2C |
6c739c5d PK |
416 | ---help--- |
417 | See I2C0_ENABLE help text. | |
418 | ||
419 | if MACH_SUN6I || MACH_SUN7I | |
420 | config I2C3_ENABLE | |
421 | bool "Enable I2C/TWI controller 3" | |
422 | default n | |
0878a8a7 | 423 | select CMD_I2C |
6c739c5d PK |
424 | ---help--- |
425 | See I2C0_ENABLE help text. | |
426 | endif | |
427 | ||
0d8382ae | 428 | if SUNXI_GEN_SUN6I |
9d082687 JW |
429 | config R_I2C_ENABLE |
430 | bool "Enable the PRCM I2C/TWI controller" | |
0d8382ae JW |
431 | # This is used for the pmic on H3 |
432 | default y if SY8106A_POWER | |
0878a8a7 | 433 | select CMD_I2C |
9d082687 JW |
434 | ---help--- |
435 | Set this to y to enable the I2C controller which is part of the PRCM. | |
0d8382ae | 436 | endif |
9d082687 | 437 | |
6c739c5d PK |
438 | if MACH_SUN7I |
439 | config I2C4_ENABLE | |
440 | bool "Enable I2C/TWI controller 4" | |
441 | default n | |
0878a8a7 | 442 | select CMD_I2C |
6c739c5d PK |
443 | ---help--- |
444 | See I2C0_ENABLE help text. | |
445 | endif | |
446 | ||
2fcf033d | 447 | config AXP_GPIO |
ab65006b | 448 | bool "Enable support for gpio-s on axp PMICs" |
2fcf033d HG |
449 | default n |
450 | ---help--- | |
451 | Say Y here to enable support for the gpio pins of the axp PMIC ICs. | |
452 | ||
7f2c521f | 453 | config VIDEO |
ab65006b | 454 | bool "Enable graphical uboot console on HDMI, LCD or VGA" |
fa855d3d | 455 | depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I |
7f2c521f LV |
456 | default y |
457 | ---help--- | |
2dae800f HG |
458 | Say Y here to add support for using a cfb console on the HDMI, LCD |
459 | or VGA output found on most sunxi devices. See doc/README.video for | |
460 | info on how to select the video output and mode. | |
461 | ||
2fbf091a | 462 | config VIDEO_HDMI |
ab65006b | 463 | bool "HDMI output support" |
2fbf091a HG |
464 | depends on VIDEO && !MACH_SUN8I |
465 | default y | |
466 | ---help--- | |
467 | Say Y here to add support for outputting video over HDMI. | |
468 | ||
d9786d23 | 469 | config VIDEO_VGA |
ab65006b | 470 | bool "VGA output support" |
d9786d23 HG |
471 | depends on VIDEO && (MACH_SUN4I || MACH_SUN7I) |
472 | default n | |
473 | ---help--- | |
474 | Say Y here to add support for outputting video over VGA. | |
475 | ||
e2bbdfb1 | 476 | config VIDEO_VGA_VIA_LCD |
ab65006b | 477 | bool "VGA via LCD controller support" |
2583d5b1 | 478 | depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) |
e2bbdfb1 HG |
479 | default n |
480 | ---help--- | |
481 | Say Y here to add support for external DACs connected to the parallel | |
482 | LCD interface driving a VGA connector, such as found on the | |
483 | Olimex A13 boards. | |
484 | ||
fb75d972 | 485 | config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH |
ab65006b | 486 | bool "Force sync active high for VGA via LCD controller support" |
fb75d972 HG |
487 | depends on VIDEO_VGA_VIA_LCD |
488 | default n | |
489 | ---help--- | |
490 | Say Y here if you've a board which uses opendrain drivers for the vga | |
491 | hsync and vsync signals. Opendrain drivers cannot generate steep enough | |
492 | positive edges for a stable video output, so on boards with opendrain | |
493 | drivers the sync signals must always be active high. | |
494 | ||
507e27df CYT |
495 | config VIDEO_VGA_EXTERNAL_DAC_EN |
496 | string "LCD panel power enable pin" | |
497 | depends on VIDEO_VGA_VIA_LCD | |
498 | default "" | |
499 | ---help--- | |
500 | Set the enable pin for the external VGA DAC. This takes a string in the | |
501 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
502 | ||
39920c81 | 503 | config VIDEO_COMPOSITE |
ab65006b | 504 | bool "Composite video output support" |
39920c81 HG |
505 | depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) |
506 | default n | |
507 | ---help--- | |
508 | Say Y here to add support for outputting composite video. | |
509 | ||
2dae800f HG |
510 | config VIDEO_LCD_MODE |
511 | string "LCD panel timing details" | |
512 | depends on VIDEO | |
513 | default "" | |
514 | ---help--- | |
515 | LCD panel timing details string, leave empty if there is no LCD panel. | |
516 | This is in drivers/video/videomodes.c: video_get_params() format, e.g. | |
517 | x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0 | |
8addd3ed | 518 | Also see: http://linux-sunxi.org/LCD |
2dae800f | 519 | |
6515032e HG |
520 | config VIDEO_LCD_DCLK_PHASE |
521 | int "LCD panel display clock phase" | |
522 | depends on VIDEO | |
523 | default 1 | |
524 | ---help--- | |
525 | Select LCD panel display clock phase shift, range 0-3. | |
526 | ||
2dae800f HG |
527 | config VIDEO_LCD_POWER |
528 | string "LCD panel power enable pin" | |
529 | depends on VIDEO | |
530 | default "" | |
531 | ---help--- | |
532 | Set the power enable pin for the LCD panel. This takes a string in the | |
533 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
534 | ||
242e3d89 HG |
535 | config VIDEO_LCD_RESET |
536 | string "LCD panel reset pin" | |
537 | depends on VIDEO | |
538 | default "" | |
539 | ---help--- | |
540 | Set the reset pin for the LCD panel. This takes a string in the format | |
541 | understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
542 | ||
2dae800f HG |
543 | config VIDEO_LCD_BL_EN |
544 | string "LCD panel backlight enable pin" | |
545 | depends on VIDEO | |
546 | default "" | |
547 | ---help--- | |
548 | Set the backlight enable pin for the LCD panel. This takes a string in the | |
549 | the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of | |
550 | port H. | |
551 | ||
552 | config VIDEO_LCD_BL_PWM | |
553 | string "LCD panel backlight pwm pin" | |
554 | depends on VIDEO | |
555 | default "" | |
556 | ---help--- | |
557 | Set the backlight pwm pin for the LCD panel. This takes a string in the | |
558 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
7f2c521f | 559 | |
a7403ae8 HG |
560 | config VIDEO_LCD_BL_PWM_ACTIVE_LOW |
561 | bool "LCD panel backlight pwm is inverted" | |
562 | depends on VIDEO | |
563 | default y | |
564 | ---help--- | |
565 | Set this if the backlight pwm output is active low. | |
566 | ||
55410089 HG |
567 | config VIDEO_LCD_PANEL_I2C |
568 | bool "LCD panel needs to be configured via i2c" | |
569 | depends on VIDEO | |
1fc42018 | 570 | default n |
0878a8a7 | 571 | select CMD_I2C |
55410089 HG |
572 | ---help--- |
573 | Say y here if the LCD panel needs to be configured via i2c. This | |
574 | will add a bitbang i2c controller using gpios to talk to the LCD. | |
575 | ||
576 | config VIDEO_LCD_PANEL_I2C_SDA | |
577 | string "LCD panel i2c interface SDA pin" | |
578 | depends on VIDEO_LCD_PANEL_I2C | |
579 | default "PG12" | |
580 | ---help--- | |
581 | Set the SDA pin for the LCD i2c interface. This takes a string in the | |
582 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
583 | ||
584 | config VIDEO_LCD_PANEL_I2C_SCL | |
585 | string "LCD panel i2c interface SCL pin" | |
586 | depends on VIDEO_LCD_PANEL_I2C | |
587 | default "PG10" | |
588 | ---help--- | |
589 | Set the SCL pin for the LCD i2c interface. This takes a string in the | |
590 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
591 | ||
213480e1 HG |
592 | |
593 | # Note only one of these may be selected at a time! But hidden choices are | |
594 | # not supported by Kconfig | |
595 | config VIDEO_LCD_IF_PARALLEL | |
596 | bool | |
597 | ||
598 | config VIDEO_LCD_IF_LVDS | |
599 | bool | |
600 | ||
601 | ||
602 | choice | |
603 | prompt "LCD panel support" | |
604 | depends on VIDEO | |
605 | ---help--- | |
606 | Select which type of LCD panel to support. | |
607 | ||
608 | config VIDEO_LCD_PANEL_PARALLEL | |
609 | bool "Generic parallel interface LCD panel" | |
610 | select VIDEO_LCD_IF_PARALLEL | |
611 | ||
612 | config VIDEO_LCD_PANEL_LVDS | |
613 | bool "Generic lvds interface LCD panel" | |
614 | select VIDEO_LCD_IF_LVDS | |
615 | ||
97ece830 SS |
616 | config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 |
617 | bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip" | |
618 | select VIDEO_LCD_SSD2828 | |
619 | select VIDEO_LCD_IF_PARALLEL | |
620 | ---help--- | |
c1cfd519 HG |
621 | 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 |
622 | ||
623 | config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 | |
624 | bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip" | |
625 | select VIDEO_LCD_ANX9804 | |
626 | select VIDEO_LCD_IF_PARALLEL | |
627 | select VIDEO_LCD_PANEL_I2C | |
628 | ---help--- | |
629 | Select this for eDP LCD panels with 4 lanes running at 1.62G, | |
630 | connected via an ANX9804 bridge chip. | |
97ece830 | 631 | |
27515b20 HG |
632 | config VIDEO_LCD_PANEL_HITACHI_TX18D42VM |
633 | bool "Hitachi tx18d42vm LCD panel" | |
634 | select VIDEO_LCD_HITACHI_TX18D42VM | |
635 | select VIDEO_LCD_IF_LVDS | |
636 | ---help--- | |
637 | 7.85" 1024x768 Hitachi tx18d42vm LCD panel support | |
638 | ||
aad2ac24 HG |
639 | config VIDEO_LCD_TL059WV5C0 |
640 | bool "tl059wv5c0 LCD panel" | |
641 | select VIDEO_LCD_PANEL_I2C | |
642 | select VIDEO_LCD_IF_PARALLEL | |
643 | ---help--- | |
644 | 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and | |
645 | Aigo M60/M608/M606 tablets. | |
646 | ||
213480e1 HG |
647 | endchoice |
648 | ||
649 | ||
c13f60d9 HG |
650 | config GMAC_TX_DELAY |
651 | int "GMAC Transmit Clock Delay Chain" | |
652 | default 0 | |
653 | ---help--- | |
654 | Set the GMAC Transmit Clock Delay Chain value. | |
655 | ||
ff42d107 | 656 | config SPL_STACK_R_ADDR |
d96ebc46 | 657 | default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I |
ff42d107 HG |
658 | default 0x2fe00000 if MACH_SUN9I |
659 | ||
dd84058d | 660 | endif |