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Commit | Line | Data |
---|---|---|
2c7e3b90 IC |
1 | if ARCH_SUNXI |
2 | ||
44d8ae5b HG |
3 | # Note only one of these may be selected at a time! But hidden choices are |
4 | # not supported by Kconfig | |
5 | config SUNXI_GEN_SUN4I | |
6 | bool | |
7 | ---help--- | |
8 | Select this for sunxi SoCs which have resets and clocks set up | |
9 | as the original A10 (mach-sun4i). | |
10 | ||
11 | config SUNXI_GEN_SUN6I | |
12 | bool | |
13 | ---help--- | |
14 | Select this for sunxi SoCs which have sun6i like periphery, like | |
15 | separate ahb reset control registers, custom pmic bus, new style | |
16 | watchdog, etc. | |
17 | ||
18 | ||
2c7e3b90 IC |
19 | choice |
20 | prompt "Sunxi SoC Variant" | |
21 | ||
c3be2793 | 22 | config MACH_SUN4I |
2c7e3b90 IC |
23 | bool "sun4i (Allwinner A10)" |
24 | select CPU_V7 | |
44d8ae5b | 25 | select SUNXI_GEN_SUN4I |
2c7e3b90 IC |
26 | select SUPPORT_SPL |
27 | ||
c3be2793 | 28 | config MACH_SUN5I |
2c7e3b90 IC |
29 | bool "sun5i (Allwinner A13)" |
30 | select CPU_V7 | |
44d8ae5b | 31 | select SUNXI_GEN_SUN4I |
2c7e3b90 IC |
32 | select SUPPORT_SPL |
33 | ||
c3be2793 | 34 | config MACH_SUN6I |
2c7e3b90 IC |
35 | bool "sun6i (Allwinner A31)" |
36 | select CPU_V7 | |
cc08ea4c CYT |
37 | select CPU_V7_HAS_NONSEC |
38 | select CPU_V7_HAS_VIRT | |
44d8ae5b | 39 | select SUNXI_GEN_SUN6I |
8c2c9cfa | 40 | select SUPPORT_SPL |
cc08ea4c | 41 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
2c7e3b90 | 42 | |
c3be2793 | 43 | config MACH_SUN7I |
2c7e3b90 IC |
44 | bool "sun7i (Allwinner A20)" |
45 | select CPU_V7 | |
ea624e19 HG |
46 | select CPU_V7_HAS_NONSEC |
47 | select CPU_V7_HAS_VIRT | |
44d8ae5b | 48 | select SUNXI_GEN_SUN4I |
2c7e3b90 | 49 | select SUPPORT_SPL |
b366fb92 | 50 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
2c7e3b90 | 51 | |
5e6bacdb | 52 | config MACH_SUN8I_A23 |
2c7e3b90 IC |
53 | bool "sun8i (Allwinner A23)" |
54 | select CPU_V7 | |
014414f5 CYT |
55 | select CPU_V7_HAS_NONSEC |
56 | select CPU_V7_HAS_VIRT | |
44d8ae5b | 57 | select SUNXI_GEN_SUN6I |
08fd1479 | 58 | select SUPPORT_SPL |
014414f5 | 59 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
2c7e3b90 | 60 | |
8c3dacff VP |
61 | config MACH_SUN8I_A33 |
62 | bool "sun8i (Allwinner A33)" | |
63 | select CPU_V7 | |
014414f5 CYT |
64 | select CPU_V7_HAS_NONSEC |
65 | select CPU_V7_HAS_VIRT | |
8c3dacff VP |
66 | select SUNXI_GEN_SUN6I |
67 | select SUPPORT_SPL | |
014414f5 | 68 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
8c3dacff | 69 | |
1c27b7dc JK |
70 | config MACH_SUN8I_H3 |
71 | bool "sun8i (Allwinner H3)" | |
72 | select CPU_V7 | |
853f6d1e CYT |
73 | select CPU_V7_HAS_NONSEC |
74 | select CPU_V7_HAS_VIRT | |
1c27b7dc | 75 | select SUNXI_GEN_SUN6I |
0404d53f | 76 | select SUPPORT_SPL |
853f6d1e | 77 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
1c27b7dc | 78 | |
d96ebc46 SS |
79 | config MACH_SUN50I |
80 | bool "sun50i (Allwinner A64)" | |
81 | select ARM64 | |
82 | select SUNXI_GEN_SUN6I | |
83 | ||
762e24a0 | 84 | config MACH_SUN8I_A83T |
85 | bool "sun8i (Allwinner A83T)" | |
86 | select CPU_V7 | |
87 | select SUNXI_GEN_SUN6I | |
88 | select SUPPORT_SPL | |
89 | ||
1871a8ca HG |
90 | config MACH_SUN9I |
91 | bool "sun9i (Allwinner A80)" | |
92 | select CPU_V7 | |
93 | select SUNXI_GEN_SUN6I | |
94 | ||
2c7e3b90 | 95 | endchoice |
8a6564da | 96 | |
5e6bacdb HG |
97 | # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" |
98 | config MACH_SUN8I | |
99 | bool | |
762e24a0 | 100 | default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T |
5e6bacdb | 101 | |
f5fd8caf VP |
102 | config DRAM_TYPE |
103 | int "sunxi dram type" | |
104 | depends on MACH_SUN8I_A83T | |
105 | default 3 | |
106 | ---help--- | |
107 | Set the dram type, 3: DDR3, 7: LPDDR3 | |
5e6bacdb | 108 | |
37781a1a | 109 | config DRAM_CLK |
8ffc487c HG |
110 | int "sunxi dram clock speed" |
111 | default 312 if MACH_SUN6I || MACH_SUN8I | |
112 | default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I | |
37781a1a HG |
113 | ---help--- |
114 | Set the dram clock speed, valid range 240 - 480, must be a multiple | |
e1a0888e | 115 | of 24. |
37781a1a | 116 | |
47e3501a SS |
117 | if MACH_SUN5I || MACH_SUN7I |
118 | config DRAM_MBUS_CLK | |
119 | int "sunxi mbus clock speed" | |
120 | default 300 | |
121 | ---help--- | |
122 | Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. | |
123 | ||
124 | endif | |
125 | ||
37781a1a | 126 | config DRAM_ZQ |
8ffc487c HG |
127 | int "sunxi dram zq value" |
128 | default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I | |
129 | default 127 if MACH_SUN7I | |
37781a1a | 130 | ---help--- |
e1a0888e | 131 | Set the dram zq value. |
8ffc487c | 132 | |
8975cdf4 HG |
133 | config DRAM_ODT_EN |
134 | bool "sunxi dram odt enable" | |
135 | default n if !MACH_SUN8I_A23 | |
136 | default y if MACH_SUN8I_A23 | |
137 | ---help--- | |
138 | Select this to enable dram odt (on die termination). | |
139 | ||
8ffc487c HG |
140 | if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I |
141 | config DRAM_EMR1 | |
142 | int "sunxi dram emr1 value" | |
143 | default 0 if MACH_SUN4I | |
144 | default 4 if MACH_SUN5I || MACH_SUN7I | |
145 | ---help--- | |
e1a0888e | 146 | Set the dram controller emr1 value. |
d133647a | 147 | |
47e3501a SS |
148 | config DRAM_TPR3 |
149 | hex "sunxi dram tpr3 value" | |
150 | default 0 | |
151 | ---help--- | |
152 | Set the dram controller tpr3 parameter. This parameter configures | |
153 | the delay on the command lane and also phase shifts, which are | |
154 | applied for sampling incoming read data. The default value 0 | |
155 | means that no phase/delay adjustments are necessary. Properly | |
156 | configuring this parameter increases reliability at high DRAM | |
157 | clock speeds. | |
158 | ||
159 | config DRAM_DQS_GATING_DELAY | |
160 | hex "sunxi dram dqs_gating_delay value" | |
161 | default 0 | |
162 | ---help--- | |
163 | Set the dram controller dqs_gating_delay parmeter. Each byte | |
164 | encodes the DQS gating delay for each byte lane. The delay | |
165 | granularity is 1/4 cycle. For example, the value 0x05060606 | |
166 | means that the delay is 5 quarter-cycles for one lane (1.25 | |
167 | cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. | |
168 | The default value 0 means autodetection. The results of hardware | |
169 | autodetection are not very reliable and depend on the chip | |
170 | temperature (sometimes producing different results on cold start | |
171 | and warm reboot). But the accuracy of hardware autodetection | |
172 | is usually good enough, unless running at really high DRAM | |
173 | clocks speeds (up to 600MHz). If unsure, keep as 0. | |
174 | ||
d133647a SS |
175 | choice |
176 | prompt "sunxi dram timings" | |
177 | default DRAM_TIMINGS_VENDOR_MAGIC | |
178 | ---help--- | |
179 | Select the timings of the DDR3 chips. | |
180 | ||
181 | config DRAM_TIMINGS_VENDOR_MAGIC | |
182 | bool "Magic vendor timings from Android" | |
183 | ---help--- | |
184 | The same DRAM timings as in the Allwinner boot0 bootloader. | |
185 | ||
186 | config DRAM_TIMINGS_DDR3_1066F_1333H | |
187 | bool "JEDEC DDR3-1333H with down binning to DDR3-1066F" | |
188 | ---help--- | |
189 | Use the timings of the standard JEDEC DDR3-1066F speed bin for | |
190 | DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin | |
191 | for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips | |
192 | used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 | |
193 | or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm | |
194 | that down binning to DDR3-1066F is supported (because DDR3-1066F | |
195 | uses a bit faster timings than DDR3-1333H). | |
196 | ||
197 | config DRAM_TIMINGS_DDR3_800E_1066G_1333J | |
198 | bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J" | |
199 | ---help--- | |
200 | Use the timings of the slowest possible JEDEC speed bin for the | |
201 | selected DRAM_CLK. Depending on the DRAM_CLK value, it may be | |
202 | DDR3-800E, DDR3-1066G or DDR3-1333J. | |
203 | ||
204 | endchoice | |
205 | ||
37781a1a HG |
206 | endif |
207 | ||
8975cdf4 HG |
208 | if MACH_SUN8I_A23 |
209 | config DRAM_ODT_CORRECTION | |
210 | int "sunxi dram odt correction value" | |
211 | default 0 | |
212 | ---help--- | |
213 | Set the dram odt correction value (range -255 - 255). In allwinner | |
214 | fex files, this option is found in bits 8-15 of the u32 odt_en variable | |
215 | in the [dram] section. When bit 31 of the odt_en variable is set | |
216 | then the correction is negative. Usually the value for this is 0. | |
217 | endif | |
218 | ||
e71b422b | 219 | config SYS_CLK_FREQ |
d96ebc46 | 220 | default 816000000 if MACH_SUN50I |
e71b422b IP |
221 | default 912000000 if MACH_SUN7I |
222 | default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I | |
223 | ||
8a6564da | 224 | config SYS_CONFIG_NAME |
c3be2793 IC |
225 | default "sun4i" if MACH_SUN4I |
226 | default "sun5i" if MACH_SUN5I | |
227 | default "sun6i" if MACH_SUN6I | |
228 | default "sun7i" if MACH_SUN7I | |
229 | default "sun8i" if MACH_SUN8I | |
1871a8ca | 230 | default "sun9i" if MACH_SUN9I |
d96ebc46 | 231 | default "sun50i" if MACH_SUN50I |
dd84058d | 232 | |
dd84058d | 233 | config SYS_BOARD |
dd84058d MY |
234 | default "sunxi" |
235 | ||
236 | config SYS_SOC | |
dd84058d MY |
237 | default "sunxi" |
238 | ||
f0ce28e9 SS |
239 | config UART0_PORT_F |
240 | bool "UART0 on MicroSD breakout board" | |
f0ce28e9 SS |
241 | default n |
242 | ---help--- | |
243 | Repurpose the SD card slot for getting access to the UART0 serial | |
244 | console. Primarily useful only for low level u-boot debugging on | |
245 | tablets, where normal UART0 is difficult to access and requires | |
246 | device disassembly and/or soldering. As the SD card can't be used | |
247 | at the same time, the system can be only booted in the FEL mode. | |
248 | Only enable this if you really know what you are doing. | |
249 | ||
accc9e44 HG |
250 | config OLD_SUNXI_KERNEL_COMPAT |
251 | boolean "Enable workarounds for booting old kernels" | |
252 | default n | |
253 | ---help--- | |
254 | Set this to enable various workarounds for old kernels, this results in | |
255 | sub-optimal settings for newer kernels, only enable if needed. | |
256 | ||
44c79879 MR |
257 | config MMC |
258 | depends on !UART0_PORT_F | |
259 | default y if ARCH_SUNXI | |
260 | ||
cd82113a HG |
261 | config MMC0_CD_PIN |
262 | string "Card detect pin for mmc0" | |
263 | default "" | |
264 | ---help--- | |
265 | Set the card detect pin for mmc0, leave empty to not use cd. This | |
266 | takes a string in the format understood by sunxi_name_to_gpio, e.g. | |
267 | PH1 for pin 1 of port H. | |
268 | ||
269 | config MMC1_CD_PIN | |
270 | string "Card detect pin for mmc1" | |
271 | default "" | |
272 | ---help--- | |
273 | See MMC0_CD_PIN help text. | |
274 | ||
275 | config MMC2_CD_PIN | |
276 | string "Card detect pin for mmc2" | |
277 | default "" | |
278 | ---help--- | |
279 | See MMC0_CD_PIN help text. | |
280 | ||
281 | config MMC3_CD_PIN | |
282 | string "Card detect pin for mmc3" | |
283 | default "" | |
284 | ---help--- | |
285 | See MMC0_CD_PIN help text. | |
286 | ||
8deacca9 PK |
287 | config MMC1_PINS |
288 | string "Pins for mmc1" | |
289 | default "" | |
290 | ---help--- | |
291 | Set the pins used for mmc1, when applicable. This takes a string in the | |
292 | format understood by sunxi_name_to_gpio_bank, e.g. PH for port H. | |
293 | ||
294 | config MMC2_PINS | |
295 | string "Pins for mmc2" | |
296 | default "" | |
297 | ---help--- | |
298 | See MMC1_PINS help text. | |
299 | ||
300 | config MMC3_PINS | |
301 | string "Pins for mmc3" | |
302 | default "" | |
303 | ---help--- | |
304 | See MMC1_PINS help text. | |
305 | ||
2ccfac01 HG |
306 | config MMC_SUNXI_SLOT_EXTRA |
307 | int "mmc extra slot number" | |
308 | default -1 | |
309 | ---help--- | |
310 | sunxi builds always enable mmc0, some boards also have a second sdcard | |
311 | slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable | |
312 | support for this. | |
313 | ||
2c3c3ecb HG |
314 | config INITIAL_USB_SCAN_DELAY |
315 | int "delay initial usb scan by x ms to allow builtin devices to init" | |
316 | default 0 | |
317 | ---help--- | |
318 | Some boards have on board usb devices which need longer than the | |
319 | USB spec's 1 second to connect from board powerup. Set this config | |
320 | option to a non 0 value to add an extra delay before the first usb | |
321 | bus scan. | |
322 | ||
4458b7a6 HG |
323 | config USB0_VBUS_PIN |
324 | string "Vbus enable pin for usb0 (otg)" | |
325 | default "" | |
326 | ---help--- | |
327 | Set the Vbus enable pin for usb0 (otg). This takes a string in the | |
328 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
329 | ||
52defe8f HG |
330 | config USB0_VBUS_DET |
331 | string "Vbus detect pin for usb0 (otg)" | |
52defe8f HG |
332 | default "" |
333 | ---help--- | |
334 | Set the Vbus detect pin for usb0 (otg). This takes a string in the | |
335 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
336 | ||
48c06c98 HG |
337 | config USB0_ID_DET |
338 | string "ID detect pin for usb0 (otg)" | |
339 | default "" | |
340 | ---help--- | |
341 | Set the ID detect pin for usb0 (otg). This takes a string in the | |
342 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
343 | ||
115200ce HG |
344 | config USB1_VBUS_PIN |
345 | string "Vbus enable pin for usb1 (ehci0)" | |
346 | default "PH6" if MACH_SUN4I || MACH_SUN7I | |
76946dfe | 347 | default "PH27" if MACH_SUN6I |
115200ce HG |
348 | ---help--- |
349 | Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes | |
350 | a string in the format understood by sunxi_name_to_gpio, e.g. | |
351 | PH1 for pin 1 of port H. | |
352 | ||
353 | config USB2_VBUS_PIN | |
354 | string "Vbus enable pin for usb2 (ehci1)" | |
355 | default "PH3" if MACH_SUN4I || MACH_SUN7I | |
76946dfe | 356 | default "PH24" if MACH_SUN6I |
115200ce HG |
357 | ---help--- |
358 | See USB1_VBUS_PIN help text. | |
359 | ||
60fa6301 HG |
360 | config USB3_VBUS_PIN |
361 | string "Vbus enable pin for usb3 (ehci2)" | |
362 | default "" | |
363 | ---help--- | |
364 | See USB1_VBUS_PIN help text. | |
365 | ||
6c739c5d PK |
366 | config I2C0_ENABLE |
367 | bool "Enable I2C/TWI controller 0" | |
368 | default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I | |
369 | default n if MACH_SUN6I || MACH_SUN8I | |
370 | ---help--- | |
371 | This allows enabling I2C/TWI controller 0 by muxing its pins, enabling | |
372 | its clock and setting up the bus. This is especially useful on devices | |
373 | with slaves connected to the bus or with pins exposed through e.g. an | |
374 | expansion port/header. | |
375 | ||
376 | config I2C1_ENABLE | |
377 | bool "Enable I2C/TWI controller 1" | |
378 | default n | |
379 | ---help--- | |
380 | See I2C0_ENABLE help text. | |
381 | ||
382 | config I2C2_ENABLE | |
383 | bool "Enable I2C/TWI controller 2" | |
384 | default n | |
385 | ---help--- | |
386 | See I2C0_ENABLE help text. | |
387 | ||
388 | if MACH_SUN6I || MACH_SUN7I | |
389 | config I2C3_ENABLE | |
390 | bool "Enable I2C/TWI controller 3" | |
391 | default n | |
392 | ---help--- | |
393 | See I2C0_ENABLE help text. | |
394 | endif | |
395 | ||
0d8382ae | 396 | if SUNXI_GEN_SUN6I |
9d082687 JW |
397 | config R_I2C_ENABLE |
398 | bool "Enable the PRCM I2C/TWI controller" | |
0d8382ae JW |
399 | # This is used for the pmic on H3 |
400 | default y if SY8106A_POWER | |
9d082687 JW |
401 | ---help--- |
402 | Set this to y to enable the I2C controller which is part of the PRCM. | |
0d8382ae | 403 | endif |
9d082687 | 404 | |
6c739c5d PK |
405 | if MACH_SUN7I |
406 | config I2C4_ENABLE | |
407 | bool "Enable I2C/TWI controller 4" | |
408 | default n | |
409 | ---help--- | |
410 | See I2C0_ENABLE help text. | |
411 | endif | |
412 | ||
2fcf033d HG |
413 | config AXP_GPIO |
414 | boolean "Enable support for gpio-s on axp PMICs" | |
415 | default n | |
416 | ---help--- | |
417 | Say Y here to enable support for the gpio pins of the axp PMIC ICs. | |
418 | ||
7f2c521f | 419 | config VIDEO |
2dae800f | 420 | boolean "Enable graphical uboot console on HDMI, LCD or VGA" |
762e24a0 | 421 | depends on !MACH_SUN8I_A83T |
7f2c521f LV |
422 | default y |
423 | ---help--- | |
2dae800f HG |
424 | Say Y here to add support for using a cfb console on the HDMI, LCD |
425 | or VGA output found on most sunxi devices. See doc/README.video for | |
426 | info on how to select the video output and mode. | |
427 | ||
2fbf091a HG |
428 | config VIDEO_HDMI |
429 | boolean "HDMI output support" | |
430 | depends on VIDEO && !MACH_SUN8I | |
431 | default y | |
432 | ---help--- | |
433 | Say Y here to add support for outputting video over HDMI. | |
434 | ||
d9786d23 HG |
435 | config VIDEO_VGA |
436 | boolean "VGA output support" | |
437 | depends on VIDEO && (MACH_SUN4I || MACH_SUN7I) | |
438 | default n | |
439 | ---help--- | |
440 | Say Y here to add support for outputting video over VGA. | |
441 | ||
e2bbdfb1 HG |
442 | config VIDEO_VGA_VIA_LCD |
443 | boolean "VGA via LCD controller support" | |
2583d5b1 | 444 | depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) |
e2bbdfb1 HG |
445 | default n |
446 | ---help--- | |
447 | Say Y here to add support for external DACs connected to the parallel | |
448 | LCD interface driving a VGA connector, such as found on the | |
449 | Olimex A13 boards. | |
450 | ||
fb75d972 HG |
451 | config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH |
452 | boolean "Force sync active high for VGA via LCD controller support" | |
453 | depends on VIDEO_VGA_VIA_LCD | |
454 | default n | |
455 | ---help--- | |
456 | Say Y here if you've a board which uses opendrain drivers for the vga | |
457 | hsync and vsync signals. Opendrain drivers cannot generate steep enough | |
458 | positive edges for a stable video output, so on boards with opendrain | |
459 | drivers the sync signals must always be active high. | |
460 | ||
507e27df CYT |
461 | config VIDEO_VGA_EXTERNAL_DAC_EN |
462 | string "LCD panel power enable pin" | |
463 | depends on VIDEO_VGA_VIA_LCD | |
464 | default "" | |
465 | ---help--- | |
466 | Set the enable pin for the external VGA DAC. This takes a string in the | |
467 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
468 | ||
39920c81 HG |
469 | config VIDEO_COMPOSITE |
470 | boolean "Composite video output support" | |
471 | depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) | |
472 | default n | |
473 | ---help--- | |
474 | Say Y here to add support for outputting composite video. | |
475 | ||
2dae800f HG |
476 | config VIDEO_LCD_MODE |
477 | string "LCD panel timing details" | |
478 | depends on VIDEO | |
479 | default "" | |
480 | ---help--- | |
481 | LCD panel timing details string, leave empty if there is no LCD panel. | |
482 | This is in drivers/video/videomodes.c: video_get_params() format, e.g. | |
483 | x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0 | |
8addd3ed | 484 | Also see: http://linux-sunxi.org/LCD |
2dae800f | 485 | |
6515032e HG |
486 | config VIDEO_LCD_DCLK_PHASE |
487 | int "LCD panel display clock phase" | |
488 | depends on VIDEO | |
489 | default 1 | |
490 | ---help--- | |
491 | Select LCD panel display clock phase shift, range 0-3. | |
492 | ||
2dae800f HG |
493 | config VIDEO_LCD_POWER |
494 | string "LCD panel power enable pin" | |
495 | depends on VIDEO | |
496 | default "" | |
497 | ---help--- | |
498 | Set the power enable pin for the LCD panel. This takes a string in the | |
499 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
500 | ||
242e3d89 HG |
501 | config VIDEO_LCD_RESET |
502 | string "LCD panel reset pin" | |
503 | depends on VIDEO | |
504 | default "" | |
505 | ---help--- | |
506 | Set the reset pin for the LCD panel. This takes a string in the format | |
507 | understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
508 | ||
2dae800f HG |
509 | config VIDEO_LCD_BL_EN |
510 | string "LCD panel backlight enable pin" | |
511 | depends on VIDEO | |
512 | default "" | |
513 | ---help--- | |
514 | Set the backlight enable pin for the LCD panel. This takes a string in the | |
515 | the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of | |
516 | port H. | |
517 | ||
518 | config VIDEO_LCD_BL_PWM | |
519 | string "LCD panel backlight pwm pin" | |
520 | depends on VIDEO | |
521 | default "" | |
522 | ---help--- | |
523 | Set the backlight pwm pin for the LCD panel. This takes a string in the | |
524 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
7f2c521f | 525 | |
a7403ae8 HG |
526 | config VIDEO_LCD_BL_PWM_ACTIVE_LOW |
527 | bool "LCD panel backlight pwm is inverted" | |
528 | depends on VIDEO | |
529 | default y | |
530 | ---help--- | |
531 | Set this if the backlight pwm output is active low. | |
532 | ||
55410089 HG |
533 | config VIDEO_LCD_PANEL_I2C |
534 | bool "LCD panel needs to be configured via i2c" | |
535 | depends on VIDEO | |
1fc42018 | 536 | default n |
55410089 HG |
537 | ---help--- |
538 | Say y here if the LCD panel needs to be configured via i2c. This | |
539 | will add a bitbang i2c controller using gpios to talk to the LCD. | |
540 | ||
541 | config VIDEO_LCD_PANEL_I2C_SDA | |
542 | string "LCD panel i2c interface SDA pin" | |
543 | depends on VIDEO_LCD_PANEL_I2C | |
544 | default "PG12" | |
545 | ---help--- | |
546 | Set the SDA pin for the LCD i2c interface. This takes a string in the | |
547 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
548 | ||
549 | config VIDEO_LCD_PANEL_I2C_SCL | |
550 | string "LCD panel i2c interface SCL pin" | |
551 | depends on VIDEO_LCD_PANEL_I2C | |
552 | default "PG10" | |
553 | ---help--- | |
554 | Set the SCL pin for the LCD i2c interface. This takes a string in the | |
555 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
556 | ||
213480e1 HG |
557 | |
558 | # Note only one of these may be selected at a time! But hidden choices are | |
559 | # not supported by Kconfig | |
560 | config VIDEO_LCD_IF_PARALLEL | |
561 | bool | |
562 | ||
563 | config VIDEO_LCD_IF_LVDS | |
564 | bool | |
565 | ||
566 | ||
567 | choice | |
568 | prompt "LCD panel support" | |
569 | depends on VIDEO | |
570 | ---help--- | |
571 | Select which type of LCD panel to support. | |
572 | ||
573 | config VIDEO_LCD_PANEL_PARALLEL | |
574 | bool "Generic parallel interface LCD panel" | |
575 | select VIDEO_LCD_IF_PARALLEL | |
576 | ||
577 | config VIDEO_LCD_PANEL_LVDS | |
578 | bool "Generic lvds interface LCD panel" | |
579 | select VIDEO_LCD_IF_LVDS | |
580 | ||
97ece830 SS |
581 | config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 |
582 | bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip" | |
583 | select VIDEO_LCD_SSD2828 | |
584 | select VIDEO_LCD_IF_PARALLEL | |
585 | ---help--- | |
c1cfd519 HG |
586 | 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 |
587 | ||
588 | config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 | |
589 | bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip" | |
590 | select VIDEO_LCD_ANX9804 | |
591 | select VIDEO_LCD_IF_PARALLEL | |
592 | select VIDEO_LCD_PANEL_I2C | |
593 | ---help--- | |
594 | Select this for eDP LCD panels with 4 lanes running at 1.62G, | |
595 | connected via an ANX9804 bridge chip. | |
97ece830 | 596 | |
27515b20 HG |
597 | config VIDEO_LCD_PANEL_HITACHI_TX18D42VM |
598 | bool "Hitachi tx18d42vm LCD panel" | |
599 | select VIDEO_LCD_HITACHI_TX18D42VM | |
600 | select VIDEO_LCD_IF_LVDS | |
601 | ---help--- | |
602 | 7.85" 1024x768 Hitachi tx18d42vm LCD panel support | |
603 | ||
aad2ac24 HG |
604 | config VIDEO_LCD_TL059WV5C0 |
605 | bool "tl059wv5c0 LCD panel" | |
606 | select VIDEO_LCD_PANEL_I2C | |
607 | select VIDEO_LCD_IF_PARALLEL | |
608 | ---help--- | |
609 | 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and | |
610 | Aigo M60/M608/M606 tablets. | |
611 | ||
213480e1 HG |
612 | endchoice |
613 | ||
614 | ||
c13f60d9 HG |
615 | config GMAC_TX_DELAY |
616 | int "GMAC Transmit Clock Delay Chain" | |
617 | default 0 | |
618 | ---help--- | |
619 | Set the GMAC Transmit Clock Delay Chain value. | |
620 | ||
ff42d107 | 621 | config SPL_STACK_R_ADDR |
d96ebc46 | 622 | default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I |
ff42d107 HG |
623 | default 0x2fe00000 if MACH_SUN9I |
624 | ||
dd84058d | 625 | endif |