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sunxi: video: Add support for LCD reset pin
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1if ARCH_SUNXI
2
3choice
4 prompt "Sunxi SoC Variant"
5
c3be2793 6config MACH_SUN4I
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7 bool "sun4i (Allwinner A10)"
8 select CPU_V7
9 select SUPPORT_SPL
10
c3be2793 11config MACH_SUN5I
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12 bool "sun5i (Allwinner A13)"
13 select CPU_V7
14 select SUPPORT_SPL
15
c3be2793 16config MACH_SUN6I
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17 bool "sun6i (Allwinner A31)"
18 select CPU_V7
8c2c9cfa 19 select SUPPORT_SPL
2c7e3b90 20
c3be2793 21config MACH_SUN7I
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22 bool "sun7i (Allwinner A20)"
23 select CPU_V7
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24 select CPU_V7_HAS_NONSEC
25 select CPU_V7_HAS_VIRT
2c7e3b90 26 select SUPPORT_SPL
b366fb92 27 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
2c7e3b90 28
c3be2793 29config MACH_SUN8I
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30 bool "sun8i (Allwinner A23)"
31 select CPU_V7
08fd1479 32 select SUPPORT_SPL
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33
34endchoice
8a6564da 35
37781a1a 36config DRAM_CLK
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37 int "sunxi dram clock speed"
38 default 312 if MACH_SUN6I || MACH_SUN8I
39 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
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40 ---help---
41 Set the dram clock speed, valid range 240 - 480, must be a multiple
e1a0888e 42 of 24.
37781a1a 43
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44if MACH_SUN5I || MACH_SUN7I
45config DRAM_MBUS_CLK
46 int "sunxi mbus clock speed"
47 default 300
48 ---help---
49 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
50
51endif
52
37781a1a 53config DRAM_ZQ
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54 int "sunxi dram zq value"
55 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
56 default 127 if MACH_SUN7I
37781a1a 57 ---help---
e1a0888e 58 Set the dram zq value.
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59
60if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
61config DRAM_EMR1
62 int "sunxi dram emr1 value"
63 default 0 if MACH_SUN4I
64 default 4 if MACH_SUN5I || MACH_SUN7I
65 ---help---
e1a0888e 66 Set the dram controller emr1 value.
d133647a 67
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68config DRAM_ODT_EN
69 int "sunxi dram odt_en value"
70 default 0
71 ---help---
72 Set the dram controller odt_en parameter. This can be used to
73 enable/disable the ODT feature.
74
75config DRAM_TPR3
76 hex "sunxi dram tpr3 value"
77 default 0
78 ---help---
79 Set the dram controller tpr3 parameter. This parameter configures
80 the delay on the command lane and also phase shifts, which are
81 applied for sampling incoming read data. The default value 0
82 means that no phase/delay adjustments are necessary. Properly
83 configuring this parameter increases reliability at high DRAM
84 clock speeds.
85
86config DRAM_DQS_GATING_DELAY
87 hex "sunxi dram dqs_gating_delay value"
88 default 0
89 ---help---
90 Set the dram controller dqs_gating_delay parmeter. Each byte
91 encodes the DQS gating delay for each byte lane. The delay
92 granularity is 1/4 cycle. For example, the value 0x05060606
93 means that the delay is 5 quarter-cycles for one lane (1.25
94 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
95 The default value 0 means autodetection. The results of hardware
96 autodetection are not very reliable and depend on the chip
97 temperature (sometimes producing different results on cold start
98 and warm reboot). But the accuracy of hardware autodetection
99 is usually good enough, unless running at really high DRAM
100 clocks speeds (up to 600MHz). If unsure, keep as 0.
101
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102choice
103 prompt "sunxi dram timings"
104 default DRAM_TIMINGS_VENDOR_MAGIC
105 ---help---
106 Select the timings of the DDR3 chips.
107
108config DRAM_TIMINGS_VENDOR_MAGIC
109 bool "Magic vendor timings from Android"
110 ---help---
111 The same DRAM timings as in the Allwinner boot0 bootloader.
112
113config DRAM_TIMINGS_DDR3_1066F_1333H
114 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
115 ---help---
116 Use the timings of the standard JEDEC DDR3-1066F speed bin for
117 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
118 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
119 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
120 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
121 that down binning to DDR3-1066F is supported (because DDR3-1066F
122 uses a bit faster timings than DDR3-1333H).
123
124config DRAM_TIMINGS_DDR3_800E_1066G_1333J
125 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
126 ---help---
127 Use the timings of the slowest possible JEDEC speed bin for the
128 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
129 DDR3-800E, DDR3-1066G or DDR3-1333J.
130
131endchoice
132
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133endif
134
8a6564da 135config SYS_CONFIG_NAME
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136 default "sun4i" if MACH_SUN4I
137 default "sun5i" if MACH_SUN5I
138 default "sun6i" if MACH_SUN6I
139 default "sun7i" if MACH_SUN7I
140 default "sun8i" if MACH_SUN8I
dd84058d 141
dd84058d 142config SYS_BOARD
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MY
143 default "sunxi"
144
145config SYS_SOC
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MY
146 default "sunxi"
147
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148config SPL_FEL
149 bool "SPL/FEL mode support"
150 depends on SPL
151 default n
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152 help
153 This enables support for Fast Early Loader (FEL) mode. This
154 allows U-Boot to be loaded to the board over USB by the on-chip
155 boot rom. U-Boot should be sent in two parts: SPL first, with
156 'fel write 0x2000 u-boot-spl.bin; fel exe 0x2000' then U-Boot with
157 'fel write 0x4a000000 u-boot.bin; fel exe 0x4a000000'. This option
158 shrinks the amount of SRAM available to SPL, so only enable it if
159 you need FEL. Note that enabling this option only allows FEL to be
160 used; it is still possible to boot U-Boot from boot media. U-Boot
161 SPL detects when it is being loaded using FEL.
4ce9941d 162
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163config UART0_PORT_F
164 bool "UART0 on MicroSD breakout board"
165 depends on SPL_FEL
166 default n
167 ---help---
168 Repurpose the SD card slot for getting access to the UART0 serial
169 console. Primarily useful only for low level u-boot debugging on
170 tablets, where normal UART0 is difficult to access and requires
171 device disassembly and/or soldering. As the SD card can't be used
172 at the same time, the system can be only booted in the FEL mode.
173 Only enable this if you really know what you are doing.
174
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175config FDTFILE
176 string "Default fdtfile env setting for this board"
846e3254 177
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178config OLD_SUNXI_KERNEL_COMPAT
179 boolean "Enable workarounds for booting old kernels"
180 default n
181 ---help---
182 Set this to enable various workarounds for old kernels, this results in
183 sub-optimal settings for newer kernels, only enable if needed.
184
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185config MMC0_CD_PIN
186 string "Card detect pin for mmc0"
187 default ""
188 ---help---
189 Set the card detect pin for mmc0, leave empty to not use cd. This
190 takes a string in the format understood by sunxi_name_to_gpio, e.g.
191 PH1 for pin 1 of port H.
192
193config MMC1_CD_PIN
194 string "Card detect pin for mmc1"
195 default ""
196 ---help---
197 See MMC0_CD_PIN help text.
198
199config MMC2_CD_PIN
200 string "Card detect pin for mmc2"
201 default ""
202 ---help---
203 See MMC0_CD_PIN help text.
204
205config MMC3_CD_PIN
206 string "Card detect pin for mmc3"
207 default ""
208 ---help---
209 See MMC0_CD_PIN help text.
210
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211config MMC_SUNXI_SLOT_EXTRA
212 int "mmc extra slot number"
213 default -1
214 ---help---
215 sunxi builds always enable mmc0, some boards also have a second sdcard
216 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
217 support for this.
218
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219config USB0_VBUS_PIN
220 string "Vbus enable pin for usb0 (otg)"
221 default ""
222 ---help---
223 Set the Vbus enable pin for usb0 (otg). This takes a string in the
224 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
225
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226config USB1_VBUS_PIN
227 string "Vbus enable pin for usb1 (ehci0)"
228 default "PH6" if MACH_SUN4I || MACH_SUN7I
76946dfe 229 default "PH27" if MACH_SUN6I
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230 ---help---
231 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
232 a string in the format understood by sunxi_name_to_gpio, e.g.
233 PH1 for pin 1 of port H.
234
235config USB2_VBUS_PIN
236 string "Vbus enable pin for usb2 (ehci1)"
237 default "PH3" if MACH_SUN4I || MACH_SUN7I
76946dfe 238 default "PH24" if MACH_SUN6I
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239 ---help---
240 See USB1_VBUS_PIN help text.
241
7f2c521f 242config VIDEO
2dae800f 243 boolean "Enable graphical uboot console on HDMI, LCD or VGA"
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LV
244 default y
245 ---help---
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HG
246 Say Y here to add support for using a cfb console on the HDMI, LCD
247 or VGA output found on most sunxi devices. See doc/README.video for
248 info on how to select the video output and mode.
249
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250config VIDEO_HDMI
251 boolean "HDMI output support"
252 depends on VIDEO && !MACH_SUN8I
253 default y
254 ---help---
255 Say Y here to add support for outputting video over HDMI.
256
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257config VIDEO_VGA
258 boolean "VGA output support"
259 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
260 default n
261 ---help---
262 Say Y here to add support for outputting video over VGA.
263
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264config VIDEO_VGA_VIA_LCD
265 boolean "VGA via LCD controller support"
2583d5b1 266 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
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267 default n
268 ---help---
269 Say Y here to add support for external DACs connected to the parallel
270 LCD interface driving a VGA connector, such as found on the
271 Olimex A13 boards.
272
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273config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
274 boolean "Force sync active high for VGA via LCD controller support"
275 depends on VIDEO_VGA_VIA_LCD
276 default n
277 ---help---
278 Say Y here if you've a board which uses opendrain drivers for the vga
279 hsync and vsync signals. Opendrain drivers cannot generate steep enough
280 positive edges for a stable video output, so on boards with opendrain
281 drivers the sync signals must always be active high.
282
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283config VIDEO_VGA_EXTERNAL_DAC_EN
284 string "LCD panel power enable pin"
285 depends on VIDEO_VGA_VIA_LCD
286 default ""
287 ---help---
288 Set the enable pin for the external VGA DAC. This takes a string in the
289 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
290
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291config VIDEO_LCD_MODE
292 string "LCD panel timing details"
293 depends on VIDEO
294 default ""
295 ---help---
296 LCD panel timing details string, leave empty if there is no LCD panel.
297 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
298 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
299
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300config VIDEO_LCD_DCLK_PHASE
301 int "LCD panel display clock phase"
302 depends on VIDEO
303 default 1
304 ---help---
305 Select LCD panel display clock phase shift, range 0-3.
306
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307config VIDEO_LCD_POWER
308 string "LCD panel power enable pin"
309 depends on VIDEO
310 default ""
311 ---help---
312 Set the power enable pin for the LCD panel. This takes a string in the
313 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
314
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315config VIDEO_LCD_RESET
316 string "LCD panel reset pin"
317 depends on VIDEO
318 default ""
319 ---help---
320 Set the reset pin for the LCD panel. This takes a string in the format
321 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
322
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323config VIDEO_LCD_BL_EN
324 string "LCD panel backlight enable pin"
325 depends on VIDEO
326 default ""
327 ---help---
328 Set the backlight enable pin for the LCD panel. This takes a string in the
329 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
330 port H.
331
332config VIDEO_LCD_BL_PWM
333 string "LCD panel backlight pwm pin"
334 depends on VIDEO
335 default ""
336 ---help---
337 Set the backlight pwm pin for the LCD panel. This takes a string in the
338 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
7f2c521f 339
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340config VIDEO_LCD_BL_PWM_ACTIVE_LOW
341 bool "LCD panel backlight pwm is inverted"
342 depends on VIDEO
343 default y
344 ---help---
345 Set this if the backlight pwm output is active low.
346
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347
348# Note only one of these may be selected at a time! But hidden choices are
349# not supported by Kconfig
350config VIDEO_LCD_IF_PARALLEL
351 bool
352
353config VIDEO_LCD_IF_LVDS
354 bool
355
356
357choice
358 prompt "LCD panel support"
359 depends on VIDEO
360 ---help---
361 Select which type of LCD panel to support.
362
363config VIDEO_LCD_PANEL_PARALLEL
364 bool "Generic parallel interface LCD panel"
365 select VIDEO_LCD_IF_PARALLEL
366
367config VIDEO_LCD_PANEL_LVDS
368 bool "Generic lvds interface LCD panel"
369 select VIDEO_LCD_IF_LVDS
370
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371config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
372 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
373 select VIDEO_LCD_SSD2828
374 select VIDEO_LCD_IF_PARALLEL
375 ---help---
376 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
377
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HG
378config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
379 bool "Hitachi tx18d42vm LCD panel"
380 select VIDEO_LCD_HITACHI_TX18D42VM
381 select VIDEO_LCD_IF_LVDS
382 ---help---
383 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
384
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385endchoice
386
387
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388config USB_MUSB_SUNXI
389 bool "Enable sunxi OTG / DRC USB controller in host mode"
390 default n
391 ---help---
392 Say y here to enable support for the sunxi OTG / DRC USB controller
393 used on almost all sunxi boards. Note currently u-boot can only have
394 one usb host controller enabled at a time, so enabling this on boards
395 which also use the ehci host controller will result in build errors.
396
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397config USB_KEYBOARD
398 boolean "Enable USB keyboard support"
399 default y
400 ---help---
401 Say Y here to add support for using a USB keyboard (typically used
2dae800f 402 in combination with a graphical console).
86b49093 403
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404config GMAC_TX_DELAY
405 int "GMAC Transmit Clock Delay Chain"
406 default 0
407 ---help---
408 Set the GMAC Transmit Clock Delay Chain value.
409
dd84058d 410endif