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Commit | Line | Data |
---|---|---|
2c7e3b90 IC |
1 | if ARCH_SUNXI |
2 | ||
a4d88920 SDPP |
3 | config IDENT_STRING |
4 | default " Allwinner Technology" | |
5 | ||
8f925584 SG |
6 | config PRE_CONSOLE_BUFFER |
7 | default y | |
8 | ||
53b5bf3c SG |
9 | config SPL_GPIO_SUPPORT |
10 | default y | |
11 | ||
77d2f7f5 SG |
12 | config SPL_LIBCOMMON_SUPPORT |
13 | default y | |
14 | ||
1646eba8 SG |
15 | config SPL_LIBDISK_SUPPORT |
16 | default y | |
17 | ||
cc4288ef SG |
18 | config SPL_LIBGENERIC_SUPPORT |
19 | default y | |
20 | ||
1fdf7c64 SG |
21 | config SPL_MMC_SUPPORT |
22 | default y | |
23 | ||
2253797d SG |
24 | config SPL_POWER_SUPPORT |
25 | default y | |
26 | ||
e00f76ce SG |
27 | config SPL_SERIAL_SUPPORT |
28 | default y | |
29 | ||
bc613d85 AP |
30 | config SUNXI_HIGH_SRAM |
31 | bool | |
32 | default n | |
33 | ---help--- | |
34 | Older Allwinner SoCs have their mask boot ROM mapped just below 4GB, | |
35 | with the first SRAM region being located at address 0. | |
36 | Some newer SoCs map the boot ROM at address 0 instead and move the | |
37 | SRAM to 64KB, just behind the mask ROM. | |
38 | Chips using the latter setup are supposed to select this option to | |
39 | adjust the addresses accordingly. | |
40 | ||
44d8ae5b HG |
41 | # Note only one of these may be selected at a time! But hidden choices are |
42 | # not supported by Kconfig | |
43 | config SUNXI_GEN_SUN4I | |
44 | bool | |
45 | ---help--- | |
46 | Select this for sunxi SoCs which have resets and clocks set up | |
47 | as the original A10 (mach-sun4i). | |
48 | ||
49 | config SUNXI_GEN_SUN6I | |
50 | bool | |
51 | ---help--- | |
52 | Select this for sunxi SoCs which have sun6i like periphery, like | |
53 | separate ahb reset control registers, custom pmic bus, new style | |
54 | watchdog, etc. | |
55 | ||
56 | ||
7b82a229 AP |
57 | config MACH_SUNXI_H3_H5 |
58 | bool | |
59 | select SUNXI_GEN_SUN6I | |
60 | select SUPPORT_SPL | |
61 | ||
2c7e3b90 IC |
62 | choice |
63 | prompt "Sunxi SoC Variant" | |
3da9536e | 64 | optional |
2c7e3b90 | 65 | |
c3be2793 | 66 | config MACH_SUN4I |
2c7e3b90 IC |
67 | bool "sun4i (Allwinner A10)" |
68 | select CPU_V7 | |
85db5831 | 69 | select ARM_CORTEX_CPU_IS_UP |
44d8ae5b | 70 | select SUNXI_GEN_SUN4I |
2c7e3b90 IC |
71 | select SUPPORT_SPL |
72 | ||
c3be2793 | 73 | config MACH_SUN5I |
2c7e3b90 IC |
74 | bool "sun5i (Allwinner A13)" |
75 | select CPU_V7 | |
85db5831 | 76 | select ARM_CORTEX_CPU_IS_UP |
44d8ae5b | 77 | select SUNXI_GEN_SUN4I |
2c7e3b90 IC |
78 | select SUPPORT_SPL |
79 | ||
c3be2793 | 80 | config MACH_SUN6I |
2c7e3b90 IC |
81 | bool "sun6i (Allwinner A31)" |
82 | select CPU_V7 | |
cc08ea4c CYT |
83 | select CPU_V7_HAS_NONSEC |
84 | select CPU_V7_HAS_VIRT | |
217f92bb | 85 | select ARCH_SUPPORT_PSCI |
44d8ae5b | 86 | select SUNXI_GEN_SUN6I |
8c2c9cfa | 87 | select SUPPORT_SPL |
cc08ea4c | 88 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
2c7e3b90 | 89 | |
c3be2793 | 90 | config MACH_SUN7I |
2c7e3b90 IC |
91 | bool "sun7i (Allwinner A20)" |
92 | select CPU_V7 | |
ea624e19 HG |
93 | select CPU_V7_HAS_NONSEC |
94 | select CPU_V7_HAS_VIRT | |
217f92bb | 95 | select ARCH_SUPPORT_PSCI |
44d8ae5b | 96 | select SUNXI_GEN_SUN4I |
2c7e3b90 | 97 | select SUPPORT_SPL |
b366fb92 | 98 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
2c7e3b90 | 99 | |
5e6bacdb | 100 | config MACH_SUN8I_A23 |
2c7e3b90 IC |
101 | bool "sun8i (Allwinner A23)" |
102 | select CPU_V7 | |
014414f5 CYT |
103 | select CPU_V7_HAS_NONSEC |
104 | select CPU_V7_HAS_VIRT | |
217f92bb | 105 | select ARCH_SUPPORT_PSCI |
44d8ae5b | 106 | select SUNXI_GEN_SUN6I |
08fd1479 | 107 | select SUPPORT_SPL |
014414f5 | 108 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
2c7e3b90 | 109 | |
8c3dacff VP |
110 | config MACH_SUN8I_A33 |
111 | bool "sun8i (Allwinner A33)" | |
112 | select CPU_V7 | |
014414f5 CYT |
113 | select CPU_V7_HAS_NONSEC |
114 | select CPU_V7_HAS_VIRT | |
217f92bb | 115 | select ARCH_SUPPORT_PSCI |
8c3dacff VP |
116 | select SUNXI_GEN_SUN6I |
117 | select SUPPORT_SPL | |
014414f5 | 118 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
8c3dacff | 119 | |
a81b7995 CYT |
120 | config MACH_SUN8I_A83T |
121 | bool "sun8i (Allwinner A83T)" | |
122 | select CPU_V7 | |
123 | select SUNXI_GEN_SUN6I | |
124 | select SUPPORT_SPL | |
125 | ||
1c27b7dc JK |
126 | config MACH_SUN8I_H3 |
127 | bool "sun8i (Allwinner H3)" | |
128 | select CPU_V7 | |
853f6d1e CYT |
129 | select CPU_V7_HAS_NONSEC |
130 | select CPU_V7_HAS_VIRT | |
217f92bb | 131 | select ARCH_SUPPORT_PSCI |
7b82a229 | 132 | select MACH_SUNXI_H3_H5 |
853f6d1e | 133 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
1c27b7dc | 134 | |
1871a8ca HG |
135 | config MACH_SUN9I |
136 | bool "sun9i (Allwinner A80)" | |
137 | select CPU_V7 | |
bc613d85 | 138 | select SUNXI_HIGH_SRAM |
1871a8ca | 139 | select SUNXI_GEN_SUN6I |
a98c296a | 140 | select SUPPORT_SPL |
1871a8ca | 141 | |
a81b7995 CYT |
142 | config MACH_SUN50I |
143 | bool "sun50i (Allwinner A64)" | |
144 | select ARM64 | |
145 | select SUNXI_GEN_SUN6I | |
bc613d85 | 146 | select SUNXI_HIGH_SRAM |
eb77f5c9 | 147 | select SUPPORT_SPL |
a81b7995 | 148 | |
2c7e3b90 | 149 | endchoice |
8a6564da | 150 | |
5e6bacdb HG |
151 | # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" |
152 | config MACH_SUN8I | |
153 | bool | |
7b82a229 | 154 | default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUNXI_H3_H5 || MACH_SUN8I_A83T |
5e6bacdb | 155 | |
b5402d13 AP |
156 | config RESERVE_ALLWINNER_BOOT0_HEADER |
157 | bool "reserve space for Allwinner boot0 header" | |
158 | select ENABLE_ARM_SOC_BOOT0_HOOK | |
159 | ---help--- | |
160 | Prepend a 1536 byte (empty) header to the U-Boot image file, to be | |
161 | filled with magic values post build. The Allwinner provided boot0 | |
162 | blob relies on this information to load and execute U-Boot. | |
163 | Only needed on 64-bit Allwinner boards so far when using boot0. | |
164 | ||
83843c9b AP |
165 | config ARM_BOOT_HOOK_RMR |
166 | bool | |
167 | depends on ARM64 | |
168 | default y | |
169 | select ENABLE_ARM_SOC_BOOT0_HOOK | |
170 | ---help--- | |
171 | Insert some ARM32 code at the very beginning of the U-Boot binary | |
172 | which uses an RMR register write to bring the core into AArch64 mode. | |
173 | The very first instruction acts as a switch, since it's carefully | |
174 | chosen to be a NOP in one mode and a branch in the other, so the | |
175 | code would only be executed if not already in AArch64. | |
176 | This allows both the SPL and the U-Boot proper to be entered in | |
177 | either mode and switch to AArch64 if needed. | |
178 | ||
f5fd8caf VP |
179 | config DRAM_TYPE |
180 | int "sunxi dram type" | |
181 | depends on MACH_SUN8I_A83T | |
182 | default 3 | |
183 | ---help--- | |
184 | Set the dram type, 3: DDR3, 7: LPDDR3 | |
5e6bacdb | 185 | |
37781a1a | 186 | config DRAM_CLK |
8ffc487c | 187 | int "sunxi dram clock speed" |
297bb9e0 | 188 | default 792 if MACH_SUN9I |
8ffc487c HG |
189 | default 312 if MACH_SUN6I || MACH_SUN8I |
190 | default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I | |
52e3182b | 191 | default 672 if MACH_SUN50I |
37781a1a | 192 | ---help--- |
297bb9e0 PT |
193 | Set the dram clock speed, valid range 240 - 480 (prior to sun9i), |
194 | must be a multiple of 24. For the sun9i (A80), the tested values | |
195 | (for DDR3-1600) are 312 to 792. | |
37781a1a | 196 | |
47e3501a SS |
197 | if MACH_SUN5I || MACH_SUN7I |
198 | config DRAM_MBUS_CLK | |
199 | int "sunxi mbus clock speed" | |
200 | default 300 | |
201 | ---help--- | |
202 | Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. | |
203 | ||
204 | endif | |
205 | ||
37781a1a | 206 | config DRAM_ZQ |
8ffc487c HG |
207 | int "sunxi dram zq value" |
208 | default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I | |
209 | default 127 if MACH_SUN7I | |
58b628ed | 210 | default 4145117 if MACH_SUN9I |
52e3182b | 211 | default 3881915 if MACH_SUN50I |
37781a1a | 212 | ---help--- |
e1a0888e | 213 | Set the dram zq value. |
8ffc487c | 214 | |
8975cdf4 HG |
215 | config DRAM_ODT_EN |
216 | bool "sunxi dram odt enable" | |
217 | default n if !MACH_SUN8I_A23 | |
218 | default y if MACH_SUN8I_A23 | |
eb77f5c9 | 219 | default y if MACH_SUN50I |
8975cdf4 HG |
220 | ---help--- |
221 | Select this to enable dram odt (on die termination). | |
222 | ||
8ffc487c HG |
223 | if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I |
224 | config DRAM_EMR1 | |
225 | int "sunxi dram emr1 value" | |
226 | default 0 if MACH_SUN4I | |
227 | default 4 if MACH_SUN5I || MACH_SUN7I | |
228 | ---help--- | |
e1a0888e | 229 | Set the dram controller emr1 value. |
d133647a | 230 | |
47e3501a SS |
231 | config DRAM_TPR3 |
232 | hex "sunxi dram tpr3 value" | |
233 | default 0 | |
234 | ---help--- | |
235 | Set the dram controller tpr3 parameter. This parameter configures | |
236 | the delay on the command lane and also phase shifts, which are | |
237 | applied for sampling incoming read data. The default value 0 | |
238 | means that no phase/delay adjustments are necessary. Properly | |
239 | configuring this parameter increases reliability at high DRAM | |
240 | clock speeds. | |
241 | ||
242 | config DRAM_DQS_GATING_DELAY | |
243 | hex "sunxi dram dqs_gating_delay value" | |
244 | default 0 | |
245 | ---help--- | |
246 | Set the dram controller dqs_gating_delay parmeter. Each byte | |
247 | encodes the DQS gating delay for each byte lane. The delay | |
248 | granularity is 1/4 cycle. For example, the value 0x05060606 | |
249 | means that the delay is 5 quarter-cycles for one lane (1.25 | |
250 | cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. | |
251 | The default value 0 means autodetection. The results of hardware | |
252 | autodetection are not very reliable and depend on the chip | |
253 | temperature (sometimes producing different results on cold start | |
254 | and warm reboot). But the accuracy of hardware autodetection | |
255 | is usually good enough, unless running at really high DRAM | |
256 | clocks speeds (up to 600MHz). If unsure, keep as 0. | |
257 | ||
d133647a SS |
258 | choice |
259 | prompt "sunxi dram timings" | |
260 | default DRAM_TIMINGS_VENDOR_MAGIC | |
261 | ---help--- | |
262 | Select the timings of the DDR3 chips. | |
263 | ||
264 | config DRAM_TIMINGS_VENDOR_MAGIC | |
265 | bool "Magic vendor timings from Android" | |
266 | ---help--- | |
267 | The same DRAM timings as in the Allwinner boot0 bootloader. | |
268 | ||
269 | config DRAM_TIMINGS_DDR3_1066F_1333H | |
270 | bool "JEDEC DDR3-1333H with down binning to DDR3-1066F" | |
271 | ---help--- | |
272 | Use the timings of the standard JEDEC DDR3-1066F speed bin for | |
273 | DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin | |
274 | for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips | |
275 | used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 | |
276 | or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm | |
277 | that down binning to DDR3-1066F is supported (because DDR3-1066F | |
278 | uses a bit faster timings than DDR3-1333H). | |
279 | ||
280 | config DRAM_TIMINGS_DDR3_800E_1066G_1333J | |
281 | bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J" | |
282 | ---help--- | |
283 | Use the timings of the slowest possible JEDEC speed bin for the | |
284 | selected DRAM_CLK. Depending on the DRAM_CLK value, it may be | |
285 | DDR3-800E, DDR3-1066G or DDR3-1333J. | |
286 | ||
287 | endchoice | |
288 | ||
37781a1a HG |
289 | endif |
290 | ||
8975cdf4 HG |
291 | if MACH_SUN8I_A23 |
292 | config DRAM_ODT_CORRECTION | |
293 | int "sunxi dram odt correction value" | |
294 | default 0 | |
295 | ---help--- | |
296 | Set the dram odt correction value (range -255 - 255). In allwinner | |
297 | fex files, this option is found in bits 8-15 of the u32 odt_en variable | |
298 | in the [dram] section. When bit 31 of the odt_en variable is set | |
299 | then the correction is negative. Usually the value for this is 0. | |
300 | endif | |
301 | ||
e71b422b | 302 | config SYS_CLK_FREQ |
d96ebc46 | 303 | default 816000000 if MACH_SUN50I |
e71b422b | 304 | default 912000000 if MACH_SUN7I |
c53344ad | 305 | default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I || MACH_SUN9I |
e71b422b | 306 | |
8a6564da | 307 | config SYS_CONFIG_NAME |
c3be2793 IC |
308 | default "sun4i" if MACH_SUN4I |
309 | default "sun5i" if MACH_SUN5I | |
310 | default "sun6i" if MACH_SUN6I | |
311 | default "sun7i" if MACH_SUN7I | |
312 | default "sun8i" if MACH_SUN8I | |
1871a8ca | 313 | default "sun9i" if MACH_SUN9I |
d96ebc46 | 314 | default "sun50i" if MACH_SUN50I |
dd84058d | 315 | |
dd84058d | 316 | config SYS_BOARD |
dd84058d MY |
317 | default "sunxi" |
318 | ||
319 | config SYS_SOC | |
dd84058d MY |
320 | default "sunxi" |
321 | ||
f0ce28e9 SS |
322 | config UART0_PORT_F |
323 | bool "UART0 on MicroSD breakout board" | |
f0ce28e9 SS |
324 | default n |
325 | ---help--- | |
326 | Repurpose the SD card slot for getting access to the UART0 serial | |
327 | console. Primarily useful only for low level u-boot debugging on | |
328 | tablets, where normal UART0 is difficult to access and requires | |
329 | device disassembly and/or soldering. As the SD card can't be used | |
330 | at the same time, the system can be only booted in the FEL mode. | |
331 | Only enable this if you really know what you are doing. | |
332 | ||
accc9e44 | 333 | config OLD_SUNXI_KERNEL_COMPAT |
ab65006b | 334 | bool "Enable workarounds for booting old kernels" |
accc9e44 HG |
335 | default n |
336 | ---help--- | |
337 | Set this to enable various workarounds for old kernels, this results in | |
338 | sub-optimal settings for newer kernels, only enable if needed. | |
339 | ||
cd82113a HG |
340 | config MMC0_CD_PIN |
341 | string "Card detect pin for mmc0" | |
7b82a229 | 342 | default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I |
cd82113a HG |
343 | default "" |
344 | ---help--- | |
345 | Set the card detect pin for mmc0, leave empty to not use cd. This | |
346 | takes a string in the format understood by sunxi_name_to_gpio, e.g. | |
347 | PH1 for pin 1 of port H. | |
348 | ||
349 | config MMC1_CD_PIN | |
350 | string "Card detect pin for mmc1" | |
351 | default "" | |
352 | ---help--- | |
353 | See MMC0_CD_PIN help text. | |
354 | ||
355 | config MMC2_CD_PIN | |
356 | string "Card detect pin for mmc2" | |
357 | default "" | |
358 | ---help--- | |
359 | See MMC0_CD_PIN help text. | |
360 | ||
361 | config MMC3_CD_PIN | |
362 | string "Card detect pin for mmc3" | |
363 | default "" | |
364 | ---help--- | |
365 | See MMC0_CD_PIN help text. | |
366 | ||
8deacca9 PK |
367 | config MMC1_PINS |
368 | string "Pins for mmc1" | |
369 | default "" | |
370 | ---help--- | |
371 | Set the pins used for mmc1, when applicable. This takes a string in the | |
372 | format understood by sunxi_name_to_gpio_bank, e.g. PH for port H. | |
373 | ||
374 | config MMC2_PINS | |
375 | string "Pins for mmc2" | |
376 | default "" | |
377 | ---help--- | |
378 | See MMC1_PINS help text. | |
379 | ||
380 | config MMC3_PINS | |
381 | string "Pins for mmc3" | |
382 | default "" | |
383 | ---help--- | |
384 | See MMC1_PINS help text. | |
385 | ||
2ccfac01 HG |
386 | config MMC_SUNXI_SLOT_EXTRA |
387 | int "mmc extra slot number" | |
388 | default -1 | |
389 | ---help--- | |
390 | sunxi builds always enable mmc0, some boards also have a second sdcard | |
391 | slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable | |
392 | support for this. | |
393 | ||
2c3c3ecb HG |
394 | config INITIAL_USB_SCAN_DELAY |
395 | int "delay initial usb scan by x ms to allow builtin devices to init" | |
396 | default 0 | |
397 | ---help--- | |
398 | Some boards have on board usb devices which need longer than the | |
399 | USB spec's 1 second to connect from board powerup. Set this config | |
400 | option to a non 0 value to add an extra delay before the first usb | |
401 | bus scan. | |
402 | ||
4458b7a6 HG |
403 | config USB0_VBUS_PIN |
404 | string "Vbus enable pin for usb0 (otg)" | |
405 | default "" | |
406 | ---help--- | |
407 | Set the Vbus enable pin for usb0 (otg). This takes a string in the | |
408 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
409 | ||
52defe8f HG |
410 | config USB0_VBUS_DET |
411 | string "Vbus detect pin for usb0 (otg)" | |
52defe8f HG |
412 | default "" |
413 | ---help--- | |
414 | Set the Vbus detect pin for usb0 (otg). This takes a string in the | |
415 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
416 | ||
48c06c98 HG |
417 | config USB0_ID_DET |
418 | string "ID detect pin for usb0 (otg)" | |
419 | default "" | |
420 | ---help--- | |
421 | Set the ID detect pin for usb0 (otg). This takes a string in the | |
422 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
423 | ||
115200ce HG |
424 | config USB1_VBUS_PIN |
425 | string "Vbus enable pin for usb1 (ehci0)" | |
426 | default "PH6" if MACH_SUN4I || MACH_SUN7I | |
76946dfe | 427 | default "PH27" if MACH_SUN6I |
115200ce HG |
428 | ---help--- |
429 | Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes | |
430 | a string in the format understood by sunxi_name_to_gpio, e.g. | |
431 | PH1 for pin 1 of port H. | |
432 | ||
433 | config USB2_VBUS_PIN | |
434 | string "Vbus enable pin for usb2 (ehci1)" | |
435 | default "PH3" if MACH_SUN4I || MACH_SUN7I | |
76946dfe | 436 | default "PH24" if MACH_SUN6I |
115200ce HG |
437 | ---help--- |
438 | See USB1_VBUS_PIN help text. | |
439 | ||
60fa6301 HG |
440 | config USB3_VBUS_PIN |
441 | string "Vbus enable pin for usb3 (ehci2)" | |
442 | default "" | |
443 | ---help--- | |
444 | See USB1_VBUS_PIN help text. | |
445 | ||
6c739c5d PK |
446 | config I2C0_ENABLE |
447 | bool "Enable I2C/TWI controller 0" | |
448 | default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I | |
449 | default n if MACH_SUN6I || MACH_SUN8I | |
0878a8a7 | 450 | select CMD_I2C |
6c739c5d PK |
451 | ---help--- |
452 | This allows enabling I2C/TWI controller 0 by muxing its pins, enabling | |
453 | its clock and setting up the bus. This is especially useful on devices | |
454 | with slaves connected to the bus or with pins exposed through e.g. an | |
455 | expansion port/header. | |
456 | ||
457 | config I2C1_ENABLE | |
458 | bool "Enable I2C/TWI controller 1" | |
459 | default n | |
0878a8a7 | 460 | select CMD_I2C |
6c739c5d PK |
461 | ---help--- |
462 | See I2C0_ENABLE help text. | |
463 | ||
464 | config I2C2_ENABLE | |
465 | bool "Enable I2C/TWI controller 2" | |
466 | default n | |
0878a8a7 | 467 | select CMD_I2C |
6c739c5d PK |
468 | ---help--- |
469 | See I2C0_ENABLE help text. | |
470 | ||
471 | if MACH_SUN6I || MACH_SUN7I | |
472 | config I2C3_ENABLE | |
473 | bool "Enable I2C/TWI controller 3" | |
474 | default n | |
0878a8a7 | 475 | select CMD_I2C |
6c739c5d PK |
476 | ---help--- |
477 | See I2C0_ENABLE help text. | |
478 | endif | |
479 | ||
0d8382ae | 480 | if SUNXI_GEN_SUN6I |
9d082687 JW |
481 | config R_I2C_ENABLE |
482 | bool "Enable the PRCM I2C/TWI controller" | |
0d8382ae JW |
483 | # This is used for the pmic on H3 |
484 | default y if SY8106A_POWER | |
0878a8a7 | 485 | select CMD_I2C |
9d082687 JW |
486 | ---help--- |
487 | Set this to y to enable the I2C controller which is part of the PRCM. | |
0d8382ae | 488 | endif |
9d082687 | 489 | |
6c739c5d PK |
490 | if MACH_SUN7I |
491 | config I2C4_ENABLE | |
492 | bool "Enable I2C/TWI controller 4" | |
493 | default n | |
0878a8a7 | 494 | select CMD_I2C |
6c739c5d PK |
495 | ---help--- |
496 | See I2C0_ENABLE help text. | |
497 | endif | |
498 | ||
2fcf033d | 499 | config AXP_GPIO |
ab65006b | 500 | bool "Enable support for gpio-s on axp PMICs" |
2fcf033d HG |
501 | default n |
502 | ---help--- | |
503 | Say Y here to enable support for the gpio pins of the axp PMIC ICs. | |
504 | ||
7f2c521f | 505 | config VIDEO |
ab65006b | 506 | bool "Enable graphical uboot console on HDMI, LCD or VGA" |
7b82a229 | 507 | depends on !MACH_SUN8I_A83T && !MACH_SUNXI_H3_H5 && !MACH_SUN9I && !MACH_SUN50I |
7f2c521f LV |
508 | default y |
509 | ---help--- | |
2dae800f HG |
510 | Say Y here to add support for using a cfb console on the HDMI, LCD |
511 | or VGA output found on most sunxi devices. See doc/README.video for | |
512 | info on how to select the video output and mode. | |
513 | ||
2fbf091a | 514 | config VIDEO_HDMI |
ab65006b | 515 | bool "HDMI output support" |
2fbf091a HG |
516 | depends on VIDEO && !MACH_SUN8I |
517 | default y | |
518 | ---help--- | |
519 | Say Y here to add support for outputting video over HDMI. | |
520 | ||
d9786d23 | 521 | config VIDEO_VGA |
ab65006b | 522 | bool "VGA output support" |
d9786d23 HG |
523 | depends on VIDEO && (MACH_SUN4I || MACH_SUN7I) |
524 | default n | |
525 | ---help--- | |
526 | Say Y here to add support for outputting video over VGA. | |
527 | ||
e2bbdfb1 | 528 | config VIDEO_VGA_VIA_LCD |
ab65006b | 529 | bool "VGA via LCD controller support" |
2583d5b1 | 530 | depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) |
e2bbdfb1 HG |
531 | default n |
532 | ---help--- | |
533 | Say Y here to add support for external DACs connected to the parallel | |
534 | LCD interface driving a VGA connector, such as found on the | |
535 | Olimex A13 boards. | |
536 | ||
fb75d972 | 537 | config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH |
ab65006b | 538 | bool "Force sync active high for VGA via LCD controller support" |
fb75d972 HG |
539 | depends on VIDEO_VGA_VIA_LCD |
540 | default n | |
541 | ---help--- | |
542 | Say Y here if you've a board which uses opendrain drivers for the vga | |
543 | hsync and vsync signals. Opendrain drivers cannot generate steep enough | |
544 | positive edges for a stable video output, so on boards with opendrain | |
545 | drivers the sync signals must always be active high. | |
546 | ||
507e27df CYT |
547 | config VIDEO_VGA_EXTERNAL_DAC_EN |
548 | string "LCD panel power enable pin" | |
549 | depends on VIDEO_VGA_VIA_LCD | |
550 | default "" | |
551 | ---help--- | |
552 | Set the enable pin for the external VGA DAC. This takes a string in the | |
553 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
554 | ||
39920c81 | 555 | config VIDEO_COMPOSITE |
ab65006b | 556 | bool "Composite video output support" |
39920c81 HG |
557 | depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) |
558 | default n | |
559 | ---help--- | |
560 | Say Y here to add support for outputting composite video. | |
561 | ||
2dae800f HG |
562 | config VIDEO_LCD_MODE |
563 | string "LCD panel timing details" | |
564 | depends on VIDEO | |
565 | default "" | |
566 | ---help--- | |
567 | LCD panel timing details string, leave empty if there is no LCD panel. | |
568 | This is in drivers/video/videomodes.c: video_get_params() format, e.g. | |
569 | x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0 | |
8addd3ed | 570 | Also see: http://linux-sunxi.org/LCD |
2dae800f | 571 | |
6515032e HG |
572 | config VIDEO_LCD_DCLK_PHASE |
573 | int "LCD panel display clock phase" | |
574 | depends on VIDEO | |
575 | default 1 | |
576 | ---help--- | |
577 | Select LCD panel display clock phase shift, range 0-3. | |
578 | ||
2dae800f HG |
579 | config VIDEO_LCD_POWER |
580 | string "LCD panel power enable pin" | |
581 | depends on VIDEO | |
582 | default "" | |
583 | ---help--- | |
584 | Set the power enable pin for the LCD panel. This takes a string in the | |
585 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
586 | ||
242e3d89 HG |
587 | config VIDEO_LCD_RESET |
588 | string "LCD panel reset pin" | |
589 | depends on VIDEO | |
590 | default "" | |
591 | ---help--- | |
592 | Set the reset pin for the LCD panel. This takes a string in the format | |
593 | understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
594 | ||
2dae800f HG |
595 | config VIDEO_LCD_BL_EN |
596 | string "LCD panel backlight enable pin" | |
597 | depends on VIDEO | |
598 | default "" | |
599 | ---help--- | |
600 | Set the backlight enable pin for the LCD panel. This takes a string in the | |
601 | the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of | |
602 | port H. | |
603 | ||
604 | config VIDEO_LCD_BL_PWM | |
605 | string "LCD panel backlight pwm pin" | |
606 | depends on VIDEO | |
607 | default "" | |
608 | ---help--- | |
609 | Set the backlight pwm pin for the LCD panel. This takes a string in the | |
610 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
7f2c521f | 611 | |
a7403ae8 HG |
612 | config VIDEO_LCD_BL_PWM_ACTIVE_LOW |
613 | bool "LCD panel backlight pwm is inverted" | |
614 | depends on VIDEO | |
615 | default y | |
616 | ---help--- | |
617 | Set this if the backlight pwm output is active low. | |
618 | ||
55410089 HG |
619 | config VIDEO_LCD_PANEL_I2C |
620 | bool "LCD panel needs to be configured via i2c" | |
621 | depends on VIDEO | |
1fc42018 | 622 | default n |
0878a8a7 | 623 | select CMD_I2C |
55410089 HG |
624 | ---help--- |
625 | Say y here if the LCD panel needs to be configured via i2c. This | |
626 | will add a bitbang i2c controller using gpios to talk to the LCD. | |
627 | ||
628 | config VIDEO_LCD_PANEL_I2C_SDA | |
629 | string "LCD panel i2c interface SDA pin" | |
630 | depends on VIDEO_LCD_PANEL_I2C | |
631 | default "PG12" | |
632 | ---help--- | |
633 | Set the SDA pin for the LCD i2c interface. This takes a string in the | |
634 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
635 | ||
636 | config VIDEO_LCD_PANEL_I2C_SCL | |
637 | string "LCD panel i2c interface SCL pin" | |
638 | depends on VIDEO_LCD_PANEL_I2C | |
639 | default "PG10" | |
640 | ---help--- | |
641 | Set the SCL pin for the LCD i2c interface. This takes a string in the | |
642 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
643 | ||
213480e1 HG |
644 | |
645 | # Note only one of these may be selected at a time! But hidden choices are | |
646 | # not supported by Kconfig | |
647 | config VIDEO_LCD_IF_PARALLEL | |
648 | bool | |
649 | ||
650 | config VIDEO_LCD_IF_LVDS | |
651 | bool | |
652 | ||
653 | ||
654 | choice | |
655 | prompt "LCD panel support" | |
656 | depends on VIDEO | |
657 | ---help--- | |
658 | Select which type of LCD panel to support. | |
659 | ||
660 | config VIDEO_LCD_PANEL_PARALLEL | |
661 | bool "Generic parallel interface LCD panel" | |
662 | select VIDEO_LCD_IF_PARALLEL | |
663 | ||
664 | config VIDEO_LCD_PANEL_LVDS | |
665 | bool "Generic lvds interface LCD panel" | |
666 | select VIDEO_LCD_IF_LVDS | |
667 | ||
97ece830 SS |
668 | config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 |
669 | bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip" | |
670 | select VIDEO_LCD_SSD2828 | |
671 | select VIDEO_LCD_IF_PARALLEL | |
672 | ---help--- | |
c1cfd519 HG |
673 | 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 |
674 | ||
675 | config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 | |
676 | bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip" | |
677 | select VIDEO_LCD_ANX9804 | |
678 | select VIDEO_LCD_IF_PARALLEL | |
679 | select VIDEO_LCD_PANEL_I2C | |
680 | ---help--- | |
681 | Select this for eDP LCD panels with 4 lanes running at 1.62G, | |
682 | connected via an ANX9804 bridge chip. | |
97ece830 | 683 | |
27515b20 HG |
684 | config VIDEO_LCD_PANEL_HITACHI_TX18D42VM |
685 | bool "Hitachi tx18d42vm LCD panel" | |
686 | select VIDEO_LCD_HITACHI_TX18D42VM | |
687 | select VIDEO_LCD_IF_LVDS | |
688 | ---help--- | |
689 | 7.85" 1024x768 Hitachi tx18d42vm LCD panel support | |
690 | ||
aad2ac24 HG |
691 | config VIDEO_LCD_TL059WV5C0 |
692 | bool "tl059wv5c0 LCD panel" | |
693 | select VIDEO_LCD_PANEL_I2C | |
694 | select VIDEO_LCD_IF_PARALLEL | |
695 | ---help--- | |
696 | 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and | |
697 | Aigo M60/M608/M606 tablets. | |
698 | ||
213480e1 HG |
699 | endchoice |
700 | ||
701 | ||
c13f60d9 HG |
702 | config GMAC_TX_DELAY |
703 | int "GMAC Transmit Clock Delay Chain" | |
704 | default 0 | |
705 | ---help--- | |
706 | Set the GMAC Transmit Clock Delay Chain value. | |
707 | ||
ff42d107 | 708 | config SPL_STACK_R_ADDR |
d96ebc46 | 709 | default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I |
ff42d107 HG |
710 | default 0x2fe00000 if MACH_SUN9I |
711 | ||
dd84058d | 712 | endif |