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Convert CONFIG_SPL_FAT_SUPPORT to Kconfig
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2c7e3b90
IC
1if ARCH_SUNXI
2
44d8ae5b
HG
3# Note only one of these may be selected at a time! But hidden choices are
4# not supported by Kconfig
5config SUNXI_GEN_SUN4I
6 bool
7 ---help---
8 Select this for sunxi SoCs which have resets and clocks set up
9 as the original A10 (mach-sun4i).
10
11config SUNXI_GEN_SUN6I
12 bool
13 ---help---
14 Select this for sunxi SoCs which have sun6i like periphery, like
15 separate ahb reset control registers, custom pmic bus, new style
16 watchdog, etc.
17
18
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19choice
20 prompt "Sunxi SoC Variant"
3da9536e 21 optional
2c7e3b90 22
c3be2793 23config MACH_SUN4I
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24 bool "sun4i (Allwinner A10)"
25 select CPU_V7
44d8ae5b 26 select SUNXI_GEN_SUN4I
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27 select SUPPORT_SPL
28
c3be2793 29config MACH_SUN5I
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30 bool "sun5i (Allwinner A13)"
31 select CPU_V7
44d8ae5b 32 select SUNXI_GEN_SUN4I
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33 select SUPPORT_SPL
34
c3be2793 35config MACH_SUN6I
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36 bool "sun6i (Allwinner A31)"
37 select CPU_V7
cc08ea4c
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38 select CPU_V7_HAS_NONSEC
39 select CPU_V7_HAS_VIRT
217f92bb 40 select ARCH_SUPPORT_PSCI
44d8ae5b 41 select SUNXI_GEN_SUN6I
8c2c9cfa 42 select SUPPORT_SPL
cc08ea4c 43 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
2c7e3b90 44
c3be2793 45config MACH_SUN7I
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46 bool "sun7i (Allwinner A20)"
47 select CPU_V7
ea624e19
HG
48 select CPU_V7_HAS_NONSEC
49 select CPU_V7_HAS_VIRT
217f92bb 50 select ARCH_SUPPORT_PSCI
44d8ae5b 51 select SUNXI_GEN_SUN4I
2c7e3b90 52 select SUPPORT_SPL
b366fb92 53 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
2c7e3b90 54
5e6bacdb 55config MACH_SUN8I_A23
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56 bool "sun8i (Allwinner A23)"
57 select CPU_V7
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58 select CPU_V7_HAS_NONSEC
59 select CPU_V7_HAS_VIRT
217f92bb 60 select ARCH_SUPPORT_PSCI
44d8ae5b 61 select SUNXI_GEN_SUN6I
08fd1479 62 select SUPPORT_SPL
014414f5 63 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
2c7e3b90 64
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65config MACH_SUN8I_A33
66 bool "sun8i (Allwinner A33)"
67 select CPU_V7
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68 select CPU_V7_HAS_NONSEC
69 select CPU_V7_HAS_VIRT
217f92bb 70 select ARCH_SUPPORT_PSCI
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VP
71 select SUNXI_GEN_SUN6I
72 select SUPPORT_SPL
014414f5 73 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
8c3dacff 74
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CYT
75config MACH_SUN8I_A83T
76 bool "sun8i (Allwinner A83T)"
77 select CPU_V7
78 select SUNXI_GEN_SUN6I
79 select SUPPORT_SPL
80
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JK
81config MACH_SUN8I_H3
82 bool "sun8i (Allwinner H3)"
83 select CPU_V7
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CYT
84 select CPU_V7_HAS_NONSEC
85 select CPU_V7_HAS_VIRT
217f92bb 86 select ARCH_SUPPORT_PSCI
1c27b7dc 87 select SUNXI_GEN_SUN6I
0404d53f 88 select SUPPORT_SPL
853f6d1e 89 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
1c27b7dc 90
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HG
91config MACH_SUN9I
92 bool "sun9i (Allwinner A80)"
93 select CPU_V7
94 select SUNXI_GEN_SUN6I
95
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96config MACH_SUN50I
97 bool "sun50i (Allwinner A64)"
98 select ARM64
99 select SUNXI_GEN_SUN6I
100
2c7e3b90 101endchoice
8a6564da 102
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HG
103# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
104config MACH_SUN8I
105 bool
762e24a0 106 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
5e6bacdb 107
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108config DRAM_TYPE
109 int "sunxi dram type"
110 depends on MACH_SUN8I_A83T
111 default 3
112 ---help---
113 Set the dram type, 3: DDR3, 7: LPDDR3
5e6bacdb 114
37781a1a 115config DRAM_CLK
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HG
116 int "sunxi dram clock speed"
117 default 312 if MACH_SUN6I || MACH_SUN8I
118 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
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HG
119 ---help---
120 Set the dram clock speed, valid range 240 - 480, must be a multiple
e1a0888e 121 of 24.
37781a1a 122
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SS
123if MACH_SUN5I || MACH_SUN7I
124config DRAM_MBUS_CLK
125 int "sunxi mbus clock speed"
126 default 300
127 ---help---
128 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
129
130endif
131
37781a1a 132config DRAM_ZQ
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HG
133 int "sunxi dram zq value"
134 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
135 default 127 if MACH_SUN7I
37781a1a 136 ---help---
e1a0888e 137 Set the dram zq value.
8ffc487c 138
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HG
139config DRAM_ODT_EN
140 bool "sunxi dram odt enable"
141 default n if !MACH_SUN8I_A23
142 default y if MACH_SUN8I_A23
143 ---help---
144 Select this to enable dram odt (on die termination).
145
8ffc487c
HG
146if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
147config DRAM_EMR1
148 int "sunxi dram emr1 value"
149 default 0 if MACH_SUN4I
150 default 4 if MACH_SUN5I || MACH_SUN7I
151 ---help---
e1a0888e 152 Set the dram controller emr1 value.
d133647a 153
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SS
154config DRAM_TPR3
155 hex "sunxi dram tpr3 value"
156 default 0
157 ---help---
158 Set the dram controller tpr3 parameter. This parameter configures
159 the delay on the command lane and also phase shifts, which are
160 applied for sampling incoming read data. The default value 0
161 means that no phase/delay adjustments are necessary. Properly
162 configuring this parameter increases reliability at high DRAM
163 clock speeds.
164
165config DRAM_DQS_GATING_DELAY
166 hex "sunxi dram dqs_gating_delay value"
167 default 0
168 ---help---
169 Set the dram controller dqs_gating_delay parmeter. Each byte
170 encodes the DQS gating delay for each byte lane. The delay
171 granularity is 1/4 cycle. For example, the value 0x05060606
172 means that the delay is 5 quarter-cycles for one lane (1.25
173 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
174 The default value 0 means autodetection. The results of hardware
175 autodetection are not very reliable and depend on the chip
176 temperature (sometimes producing different results on cold start
177 and warm reboot). But the accuracy of hardware autodetection
178 is usually good enough, unless running at really high DRAM
179 clocks speeds (up to 600MHz). If unsure, keep as 0.
180
d133647a
SS
181choice
182 prompt "sunxi dram timings"
183 default DRAM_TIMINGS_VENDOR_MAGIC
184 ---help---
185 Select the timings of the DDR3 chips.
186
187config DRAM_TIMINGS_VENDOR_MAGIC
188 bool "Magic vendor timings from Android"
189 ---help---
190 The same DRAM timings as in the Allwinner boot0 bootloader.
191
192config DRAM_TIMINGS_DDR3_1066F_1333H
193 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
194 ---help---
195 Use the timings of the standard JEDEC DDR3-1066F speed bin for
196 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
197 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
198 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
199 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
200 that down binning to DDR3-1066F is supported (because DDR3-1066F
201 uses a bit faster timings than DDR3-1333H).
202
203config DRAM_TIMINGS_DDR3_800E_1066G_1333J
204 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
205 ---help---
206 Use the timings of the slowest possible JEDEC speed bin for the
207 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
208 DDR3-800E, DDR3-1066G or DDR3-1333J.
209
210endchoice
211
37781a1a
HG
212endif
213
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HG
214if MACH_SUN8I_A23
215config DRAM_ODT_CORRECTION
216 int "sunxi dram odt correction value"
217 default 0
218 ---help---
219 Set the dram odt correction value (range -255 - 255). In allwinner
220 fex files, this option is found in bits 8-15 of the u32 odt_en variable
221 in the [dram] section. When bit 31 of the odt_en variable is set
222 then the correction is negative. Usually the value for this is 0.
223endif
224
e71b422b 225config SYS_CLK_FREQ
d96ebc46 226 default 816000000 if MACH_SUN50I
e71b422b
IP
227 default 912000000 if MACH_SUN7I
228 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
229
8a6564da 230config SYS_CONFIG_NAME
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231 default "sun4i" if MACH_SUN4I
232 default "sun5i" if MACH_SUN5I
233 default "sun6i" if MACH_SUN6I
234 default "sun7i" if MACH_SUN7I
235 default "sun8i" if MACH_SUN8I
1871a8ca 236 default "sun9i" if MACH_SUN9I
d96ebc46 237 default "sun50i" if MACH_SUN50I
dd84058d 238
dd84058d 239config SYS_BOARD
dd84058d
MY
240 default "sunxi"
241
242config SYS_SOC
dd84058d
MY
243 default "sunxi"
244
f0ce28e9
SS
245config UART0_PORT_F
246 bool "UART0 on MicroSD breakout board"
f0ce28e9
SS
247 default n
248 ---help---
249 Repurpose the SD card slot for getting access to the UART0 serial
250 console. Primarily useful only for low level u-boot debugging on
251 tablets, where normal UART0 is difficult to access and requires
252 device disassembly and/or soldering. As the SD card can't be used
253 at the same time, the system can be only booted in the FEL mode.
254 Only enable this if you really know what you are doing.
255
accc9e44 256config OLD_SUNXI_KERNEL_COMPAT
ab65006b 257 bool "Enable workarounds for booting old kernels"
accc9e44
HG
258 default n
259 ---help---
260 Set this to enable various workarounds for old kernels, this results in
261 sub-optimal settings for newer kernels, only enable if needed.
262
44c79879
MR
263config MMC
264 depends on !UART0_PORT_F
265 default y if ARCH_SUNXI
266
cd82113a
HG
267config MMC0_CD_PIN
268 string "Card detect pin for mmc0"
acdab175 269 default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
cd82113a
HG
270 default ""
271 ---help---
272 Set the card detect pin for mmc0, leave empty to not use cd. This
273 takes a string in the format understood by sunxi_name_to_gpio, e.g.
274 PH1 for pin 1 of port H.
275
276config MMC1_CD_PIN
277 string "Card detect pin for mmc1"
278 default ""
279 ---help---
280 See MMC0_CD_PIN help text.
281
282config MMC2_CD_PIN
283 string "Card detect pin for mmc2"
284 default ""
285 ---help---
286 See MMC0_CD_PIN help text.
287
288config MMC3_CD_PIN
289 string "Card detect pin for mmc3"
290 default ""
291 ---help---
292 See MMC0_CD_PIN help text.
293
8deacca9
PK
294config MMC1_PINS
295 string "Pins for mmc1"
296 default ""
297 ---help---
298 Set the pins used for mmc1, when applicable. This takes a string in the
299 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
300
301config MMC2_PINS
302 string "Pins for mmc2"
303 default ""
304 ---help---
305 See MMC1_PINS help text.
306
307config MMC3_PINS
308 string "Pins for mmc3"
309 default ""
310 ---help---
311 See MMC1_PINS help text.
312
2ccfac01
HG
313config MMC_SUNXI_SLOT_EXTRA
314 int "mmc extra slot number"
315 default -1
316 ---help---
317 sunxi builds always enable mmc0, some boards also have a second sdcard
318 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
319 support for this.
320
2c3c3ecb
HG
321config INITIAL_USB_SCAN_DELAY
322 int "delay initial usb scan by x ms to allow builtin devices to init"
323 default 0
324 ---help---
325 Some boards have on board usb devices which need longer than the
326 USB spec's 1 second to connect from board powerup. Set this config
327 option to a non 0 value to add an extra delay before the first usb
328 bus scan.
329
4458b7a6
HG
330config USB0_VBUS_PIN
331 string "Vbus enable pin for usb0 (otg)"
332 default ""
333 ---help---
334 Set the Vbus enable pin for usb0 (otg). This takes a string in the
335 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
336
52defe8f
HG
337config USB0_VBUS_DET
338 string "Vbus detect pin for usb0 (otg)"
52defe8f
HG
339 default ""
340 ---help---
341 Set the Vbus detect pin for usb0 (otg). This takes a string in the
342 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
343
48c06c98
HG
344config USB0_ID_DET
345 string "ID detect pin for usb0 (otg)"
346 default ""
347 ---help---
348 Set the ID detect pin for usb0 (otg). This takes a string in the
349 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
350
115200ce
HG
351config USB1_VBUS_PIN
352 string "Vbus enable pin for usb1 (ehci0)"
353 default "PH6" if MACH_SUN4I || MACH_SUN7I
76946dfe 354 default "PH27" if MACH_SUN6I
115200ce
HG
355 ---help---
356 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
357 a string in the format understood by sunxi_name_to_gpio, e.g.
358 PH1 for pin 1 of port H.
359
360config USB2_VBUS_PIN
361 string "Vbus enable pin for usb2 (ehci1)"
362 default "PH3" if MACH_SUN4I || MACH_SUN7I
76946dfe 363 default "PH24" if MACH_SUN6I
115200ce
HG
364 ---help---
365 See USB1_VBUS_PIN help text.
366
60fa6301
HG
367config USB3_VBUS_PIN
368 string "Vbus enable pin for usb3 (ehci2)"
369 default ""
370 ---help---
371 See USB1_VBUS_PIN help text.
372
6c739c5d
PK
373config I2C0_ENABLE
374 bool "Enable I2C/TWI controller 0"
375 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
376 default n if MACH_SUN6I || MACH_SUN8I
0878a8a7 377 select CMD_I2C
6c739c5d
PK
378 ---help---
379 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
380 its clock and setting up the bus. This is especially useful on devices
381 with slaves connected to the bus or with pins exposed through e.g. an
382 expansion port/header.
383
384config I2C1_ENABLE
385 bool "Enable I2C/TWI controller 1"
386 default n
0878a8a7 387 select CMD_I2C
6c739c5d
PK
388 ---help---
389 See I2C0_ENABLE help text.
390
391config I2C2_ENABLE
392 bool "Enable I2C/TWI controller 2"
393 default n
0878a8a7 394 select CMD_I2C
6c739c5d
PK
395 ---help---
396 See I2C0_ENABLE help text.
397
398if MACH_SUN6I || MACH_SUN7I
399config I2C3_ENABLE
400 bool "Enable I2C/TWI controller 3"
401 default n
0878a8a7 402 select CMD_I2C
6c739c5d
PK
403 ---help---
404 See I2C0_ENABLE help text.
405endif
406
0d8382ae 407if SUNXI_GEN_SUN6I
9d082687
JW
408config R_I2C_ENABLE
409 bool "Enable the PRCM I2C/TWI controller"
0d8382ae
JW
410 # This is used for the pmic on H3
411 default y if SY8106A_POWER
0878a8a7 412 select CMD_I2C
9d082687
JW
413 ---help---
414 Set this to y to enable the I2C controller which is part of the PRCM.
0d8382ae 415endif
9d082687 416
6c739c5d
PK
417if MACH_SUN7I
418config I2C4_ENABLE
419 bool "Enable I2C/TWI controller 4"
420 default n
0878a8a7 421 select CMD_I2C
6c739c5d
PK
422 ---help---
423 See I2C0_ENABLE help text.
424endif
425
2fcf033d 426config AXP_GPIO
ab65006b 427 bool "Enable support for gpio-s on axp PMICs"
2fcf033d
HG
428 default n
429 ---help---
430 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
431
7f2c521f 432config VIDEO
ab65006b 433 bool "Enable graphical uboot console on HDMI, LCD or VGA"
fa855d3d 434 depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I
7f2c521f
LV
435 default y
436 ---help---
2dae800f
HG
437 Say Y here to add support for using a cfb console on the HDMI, LCD
438 or VGA output found on most sunxi devices. See doc/README.video for
439 info on how to select the video output and mode.
440
2fbf091a 441config VIDEO_HDMI
ab65006b 442 bool "HDMI output support"
2fbf091a
HG
443 depends on VIDEO && !MACH_SUN8I
444 default y
445 ---help---
446 Say Y here to add support for outputting video over HDMI.
447
d9786d23 448config VIDEO_VGA
ab65006b 449 bool "VGA output support"
d9786d23
HG
450 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
451 default n
452 ---help---
453 Say Y here to add support for outputting video over VGA.
454
e2bbdfb1 455config VIDEO_VGA_VIA_LCD
ab65006b 456 bool "VGA via LCD controller support"
2583d5b1 457 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
e2bbdfb1
HG
458 default n
459 ---help---
460 Say Y here to add support for external DACs connected to the parallel
461 LCD interface driving a VGA connector, such as found on the
462 Olimex A13 boards.
463
fb75d972 464config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
ab65006b 465 bool "Force sync active high for VGA via LCD controller support"
fb75d972
HG
466 depends on VIDEO_VGA_VIA_LCD
467 default n
468 ---help---
469 Say Y here if you've a board which uses opendrain drivers for the vga
470 hsync and vsync signals. Opendrain drivers cannot generate steep enough
471 positive edges for a stable video output, so on boards with opendrain
472 drivers the sync signals must always be active high.
473
507e27df
CYT
474config VIDEO_VGA_EXTERNAL_DAC_EN
475 string "LCD panel power enable pin"
476 depends on VIDEO_VGA_VIA_LCD
477 default ""
478 ---help---
479 Set the enable pin for the external VGA DAC. This takes a string in the
480 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
481
39920c81 482config VIDEO_COMPOSITE
ab65006b 483 bool "Composite video output support"
39920c81
HG
484 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
485 default n
486 ---help---
487 Say Y here to add support for outputting composite video.
488
2dae800f
HG
489config VIDEO_LCD_MODE
490 string "LCD panel timing details"
491 depends on VIDEO
492 default ""
493 ---help---
494 LCD panel timing details string, leave empty if there is no LCD panel.
495 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
496 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
8addd3ed 497 Also see: http://linux-sunxi.org/LCD
2dae800f 498
6515032e
HG
499config VIDEO_LCD_DCLK_PHASE
500 int "LCD panel display clock phase"
501 depends on VIDEO
502 default 1
503 ---help---
504 Select LCD panel display clock phase shift, range 0-3.
505
2dae800f
HG
506config VIDEO_LCD_POWER
507 string "LCD panel power enable pin"
508 depends on VIDEO
509 default ""
510 ---help---
511 Set the power enable pin for the LCD panel. This takes a string in the
512 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
513
242e3d89
HG
514config VIDEO_LCD_RESET
515 string "LCD panel reset pin"
516 depends on VIDEO
517 default ""
518 ---help---
519 Set the reset pin for the LCD panel. This takes a string in the format
520 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
521
2dae800f
HG
522config VIDEO_LCD_BL_EN
523 string "LCD panel backlight enable pin"
524 depends on VIDEO
525 default ""
526 ---help---
527 Set the backlight enable pin for the LCD panel. This takes a string in the
528 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
529 port H.
530
531config VIDEO_LCD_BL_PWM
532 string "LCD panel backlight pwm pin"
533 depends on VIDEO
534 default ""
535 ---help---
536 Set the backlight pwm pin for the LCD panel. This takes a string in the
537 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
7f2c521f 538
a7403ae8
HG
539config VIDEO_LCD_BL_PWM_ACTIVE_LOW
540 bool "LCD panel backlight pwm is inverted"
541 depends on VIDEO
542 default y
543 ---help---
544 Set this if the backlight pwm output is active low.
545
55410089
HG
546config VIDEO_LCD_PANEL_I2C
547 bool "LCD panel needs to be configured via i2c"
548 depends on VIDEO
1fc42018 549 default n
0878a8a7 550 select CMD_I2C
55410089
HG
551 ---help---
552 Say y here if the LCD panel needs to be configured via i2c. This
553 will add a bitbang i2c controller using gpios to talk to the LCD.
554
555config VIDEO_LCD_PANEL_I2C_SDA
556 string "LCD panel i2c interface SDA pin"
557 depends on VIDEO_LCD_PANEL_I2C
558 default "PG12"
559 ---help---
560 Set the SDA pin for the LCD i2c interface. This takes a string in the
561 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
562
563config VIDEO_LCD_PANEL_I2C_SCL
564 string "LCD panel i2c interface SCL pin"
565 depends on VIDEO_LCD_PANEL_I2C
566 default "PG10"
567 ---help---
568 Set the SCL pin for the LCD i2c interface. This takes a string in the
569 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
570
213480e1
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571
572# Note only one of these may be selected at a time! But hidden choices are
573# not supported by Kconfig
574config VIDEO_LCD_IF_PARALLEL
575 bool
576
577config VIDEO_LCD_IF_LVDS
578 bool
579
580
581choice
582 prompt "LCD panel support"
583 depends on VIDEO
584 ---help---
585 Select which type of LCD panel to support.
586
587config VIDEO_LCD_PANEL_PARALLEL
588 bool "Generic parallel interface LCD panel"
589 select VIDEO_LCD_IF_PARALLEL
590
591config VIDEO_LCD_PANEL_LVDS
592 bool "Generic lvds interface LCD panel"
593 select VIDEO_LCD_IF_LVDS
594
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595config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
596 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
597 select VIDEO_LCD_SSD2828
598 select VIDEO_LCD_IF_PARALLEL
599 ---help---
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600 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
601
602config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
603 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
604 select VIDEO_LCD_ANX9804
605 select VIDEO_LCD_IF_PARALLEL
606 select VIDEO_LCD_PANEL_I2C
607 ---help---
608 Select this for eDP LCD panels with 4 lanes running at 1.62G,
609 connected via an ANX9804 bridge chip.
97ece830 610
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611config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
612 bool "Hitachi tx18d42vm LCD panel"
613 select VIDEO_LCD_HITACHI_TX18D42VM
614 select VIDEO_LCD_IF_LVDS
615 ---help---
616 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
617
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618config VIDEO_LCD_TL059WV5C0
619 bool "tl059wv5c0 LCD panel"
620 select VIDEO_LCD_PANEL_I2C
621 select VIDEO_LCD_IF_PARALLEL
622 ---help---
623 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
624 Aigo M60/M608/M606 tablets.
625
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626endchoice
627
628
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629config GMAC_TX_DELAY
630 int "GMAC Transmit Clock Delay Chain"
631 default 0
632 ---help---
633 Set the GMAC Transmit Clock Delay Chain value.
634
ff42d107 635config SPL_STACK_R_ADDR
d96ebc46 636 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
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637 default 0x2fe00000 if MACH_SUN9I
638
dd84058d 639endif