[people/ms/u-boot.git] / board / teejet / mt_ventoux / mt_ventoux.c

/*
 * Copyright (C) 2011
 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
 *
 * Copyright (C) 2009 TechNexion Ltd.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <netdev.h>
#include <malloc.h>
#include <fpga.h>
#include <video_fb.h>
#include <asm/io.h>
#include <asm/arch/mem.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/dss.h>
#include <asm/arch/clock.h>
#include <i2c.h>
#include <spartan3.h>
#include <asm/gpio.h>
#ifdef CONFIG_USB_EHCI
#include <usb.h>
#include <asm/ehci-omap.h>
#endif
#include "mt_ventoux.h"

DECLARE_GLOBAL_DATA_PTR;

#define BUZZER		140
#define SPEAKER		141
#define USB1_PWR	127
#define USB2_PWR	149

#ifndef CONFIG_FPGA
#error "The Teejet mt_ventoux must have CONFIG_FPGA enabled"
#endif

#define FPGA_RESET	62
#define FPGA_PROG	116
#define FPGA_CCLK	117
#define FPGA_DIN	118
#define FPGA_INIT	119
#define FPGA_DONE	154

#define LCD_PWR		138
#define LCD_PON_PIN	139

#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
static struct {
	u32 xres;
	u32 yres;
} panel_resolution[] = {
	{ 480, 272 },
	{ 800, 480 }
};

static struct panel_config lcd_cfg[] = {
	{
	.timing_h       = PANEL_TIMING_H(40, 5, 2),
	.timing_v       = PANEL_TIMING_V(8, 8, 2),
	.pol_freq       = 0x00003000, /* Pol Freq */
	.divisor        = 0x00010033, /* 9 Mhz Pixel Clock */
	.panel_type     = 0x01, /* TFT */
	.data_lines     = 0x03, /* 24 Bit RGB */
	.load_mode      = 0x02, /* Frame Mode */
	.panel_color	= 0,
	.gfx_format	= GFXFORMAT_RGB24_UNPACKED,
	},
	{
	.timing_h       = PANEL_TIMING_H(20, 192, 4),
	.timing_v       = PANEL_TIMING_V(2, 20, 10),
	.pol_freq       = 0x00004000, /* Pol Freq */
	.divisor        = 0x0001000E, /* 36Mhz Pixel Clock */
	.panel_type     = 0x01, /* TFT */
	.data_lines     = 0x03, /* 24 Bit RGB */
	.load_mode      = 0x02, /* Frame Mode */
	.panel_color	= 0,
	.gfx_format	= GFXFORMAT_RGB24_UNPACKED,
	}
};
#endif

/* Timing definitions for FPGA */
static const u32 gpmc_fpga[] = {
	FPGA_GPMC_CONFIG1,
	FPGA_GPMC_CONFIG2,
	FPGA_GPMC_CONFIG3,
	FPGA_GPMC_CONFIG4,
	FPGA_GPMC_CONFIG5,
	FPGA_GPMC_CONFIG6,
};

#ifdef CONFIG_USB_EHCI
static struct omap_usbhs_board_data usbhs_bdata = {
	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
	.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};

int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
	return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
}

int ehci_hcd_stop(int index)
{
	return omap_ehci_hcd_stop();
}
#endif


static inline void fpga_reset(int nassert)
{
	gpio_set_value(FPGA_RESET, !nassert);
}

int fpga_pgm_fn(int nassert, int nflush, int cookie)
{
	debug("%s:%d: FPGA PROGRAM ", __func__, __LINE__);

	gpio_set_value(FPGA_PROG, !nassert);

	return nassert;
}

int fpga_init_fn(int cookie)
{
	return !gpio_get_value(FPGA_INIT);
}

int fpga_done_fn(int cookie)
{
	return gpio_get_value(FPGA_DONE);
}

int fpga_pre_config_fn(int cookie)
{
	debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);

	/* Setting GPIOs for programming Mode */
	gpio_request(FPGA_RESET, "FPGA_RESET");
	gpio_direction_output(FPGA_RESET, 1);
	gpio_request(FPGA_PROG, "FPGA_PROG");
	gpio_direction_output(FPGA_PROG, 1);
	gpio_request(FPGA_CCLK, "FPGA_CCLK");
	gpio_direction_output(FPGA_CCLK, 1);
	gpio_request(FPGA_DIN, "FPGA_DIN");
	gpio_direction_output(FPGA_DIN, 0);
	gpio_request(FPGA_INIT, "FPGA_INIT");
	gpio_direction_input(FPGA_INIT);
	gpio_request(FPGA_DONE, "FPGA_DONE");
	gpio_direction_input(FPGA_DONE);

	/* Be sure that signal are deasserted */
	gpio_set_value(FPGA_RESET, 1);
	gpio_set_value(FPGA_PROG, 1);

	return 0;
}

int fpga_post_config_fn(int cookie)
{
	debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__);

	fpga_reset(true);
	udelay(100);
	fpga_reset(false);

	return 0;
}

/* Write program to the FPGA */
int fpga_wr_fn(int nassert_write, int flush, int cookie)
{
	gpio_set_value(FPGA_DIN, nassert_write);

	return nassert_write;
}

int fpga_clk_fn(int assert_clk, int flush, int cookie)
{
	gpio_set_value(FPGA_CCLK, assert_clk);

	return assert_clk;
}

Xilinx_Spartan3_Slave_Serial_fns mt_ventoux_fpga_fns = {
	fpga_pre_config_fn,
	fpga_pgm_fn,
	fpga_clk_fn,
	fpga_init_fn,
	fpga_done_fn,
	fpga_wr_fn,
	fpga_post_config_fn,
};

Xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
			(void *)&mt_ventoux_fpga_fns, 0);

/* Initialize the FPGA */
static void mt_ventoux_init_fpga(void)
{
	fpga_pre_config_fn(0);

	/* Setting CS1 for FPGA access */
	enable_gpmc_cs_config(gpmc_fpga, &gpmc_cfg->cs[1],
		FPGA_BASE_ADDR, GPMC_SIZE_128M);

	fpga_init();
	fpga_add(fpga_xilinx, &fpga);
}

/*
 * Routine: board_init
 * Description: Early hardware init.
 */
int board_init(void)
{
	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */

	/* boot param addr */
	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);

	mt_ventoux_init_fpga();

	/* GPIO_140: speaker #mute */
	MUX_VAL(CP(MCBSP3_DX),		(IEN | PTU | EN | M4))
	/* GPIO_141: Buzz Hi */
	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTU | EN | M4))

	/* Turning off the buzzer */
	gpio_request(BUZZER, "BUZZER_MUTE");
	gpio_request(SPEAKER, "SPEAKER");
	gpio_direction_output(BUZZER, 0);
	gpio_direction_output(SPEAKER, 0);

	/* Activate USB power */
	gpio_request(USB1_PWR, "USB1_PWR");
	gpio_request(USB2_PWR, "USB2_PWR");
	gpio_direction_output(USB1_PWR, 1);
	gpio_direction_output(USB2_PWR, 1);

	return 0;
}

#ifndef CONFIG_SPL_BUILD
int misc_init_r(void)
{
	char *eth_addr;
	struct tam3517_module_info info;
	int ret;

	TAM3517_READ_EEPROM(&info, ret);
	dieid_num_r();

	if (ret)
		return 0;
	eth_addr = getenv("ethaddr");
	if (!eth_addr)
		TAM3517_READ_MAC_FROM_EEPROM(&info);

	TAM3517_PRINT_SOM_INFO(&info);
	return 0;
}
#endif

/*
 * Routine: set_muxconf_regs
 * Description: Setting up the configuration Mux registers specific to the
 *		hardware. Many pins need to be moved from protect to primary
 *		mode.
 */
void set_muxconf_regs(void)
{
	MUX_MT_VENTOUX();
}

/*
 * Initializes on-chip ethernet controllers.
 * to override, implement board_eth_init()
 */
int board_eth_init(bd_t *bis)
{
	davinci_emac_initialize();
	return 0;
}

#if defined(CONFIG_OMAP_HSMMC) && \
	!defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
	return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif

#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
int board_video_init(void)
{
	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
	struct panel_config *panel = &lcd_cfg[0];
	char *s;
	u32 index = 0;

	void *fb;

	fb = (void *)0x88000000;

	s = getenv("panel");
	if (s) {
		index = simple_strtoul(s, NULL, 10);
		if (index < ARRAY_SIZE(lcd_cfg))
			panel = &lcd_cfg[index];
		else
			return 0;
	}

	panel->frame_buffer = fb;
	printf("Panel: %dx%d\n", panel_resolution[index].xres,
		panel_resolution[index].yres);
	panel->lcd_size = (panel_resolution[index].yres - 1) << 16 |
		(panel_resolution[index].xres - 1);

	gpio_request(LCD_PWR, "LCD Power");
	gpio_request(LCD_PON_PIN, "LCD Pon");
	gpio_direction_output(LCD_PWR, 0);
	gpio_direction_output(LCD_PON_PIN, 1);


	setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
	setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);

	omap3_dss_panel_config(panel);
	omap3_dss_enable();

	return 0;
}
#endif
Commit	Line	Data
1fdabedd SB	1	/*
	2	* Copyright (C) 2011
	3	* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
	4	*
	5	* Copyright (C) 2009 TechNexion Ltd.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
1fdabedd SB	8	*/
	9
	10	#include <common.h>
	11	#include <netdev.h>
62986875	12	#include <malloc.h>
1fdabedd	13	#include <fpga.h>
62986875	14	#include <video_fb.h>
1fdabedd SB	15	#include <asm/io.h>
	16	#include <asm/arch/mem.h>
	17	#include <asm/arch/mux.h>
	18	#include <asm/arch/sys_proto.h>
	19	#include <asm/omap_gpio.h>
	20	#include <asm/arch/mmc_host_def.h>
62986875	21	#include <asm/arch/dss.h>
af1d002f	22	#include <asm/arch/clock.h>
1fdabedd SB	23	#include <i2c.h>
	24	#include <spartan3.h>
	25	#include <asm/gpio.h>
	26	#ifdef CONFIG_USB_EHCI
	27	#include <usb.h>
	28	#include <asm/ehci-omap.h>
	29	#endif
	30	#include "mt_ventoux.h"
	31
	32	DECLARE_GLOBAL_DATA_PTR;
	33
ff530fc7 SB	34	#define BUZZER 140
ff530fc7 SB	35	#define SPEAKER 141
9f670540 SB	36	#define USB1_PWR 127
9f670540 SB	37	#define USB2_PWR 149
ff530fc7	38
1fdabedd SB	39	#ifndef CONFIG_FPGA
	40	#error "The Teejet mt_ventoux must have CONFIG_FPGA enabled"
	41	#endif
	42
	43	#define FPGA_RESET 62
	44	#define FPGA_PROG 116
	45	#define FPGA_CCLK 117
	46	#define FPGA_DIN 118
	47	#define FPGA_INIT 119
	48	#define FPGA_DONE 154
	49
62986875 SB	50	#define LCD_PWR 138
	51	#define LCD_PON_PIN 139
	52
	53	#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
	54	static struct {
	55	u32 xres;
	56	u32 yres;
	57	} panel_resolution[] = {
	58	{ 480, 272 },
	59	{ 800, 480 }
	60	};
	61
	62	static struct panel_config lcd_cfg[] = {
	63	{
fe2d59a1 SB	64	.timing_h = PANEL_TIMING_H(40, 5, 2),
	65	.timing_v = PANEL_TIMING_V(8, 8, 2),
	66	.pol_freq = 0x00003000, /* Pol Freq */
	67	.divisor = 0x00010033, /* 9 Mhz Pixel Clock */
62986875 SB	68	.panel_type = 0x01, /* TFT */
	69	.data_lines = 0x03, /* 24 Bit RGB */
	70	.load_mode = 0x02, /* Frame Mode */
	71	.panel_color = 0,
bcc6cc9b	72	.gfx_format = GFXFORMAT_RGB24_UNPACKED,
62986875 SB	73	},
	74	{
	75	.timing_h = PANEL_TIMING_H(20, 192, 4),
	76	.timing_v = PANEL_TIMING_V(2, 20, 10),
	77	.pol_freq = 0x00004000, /* Pol Freq */
	78	.divisor = 0x0001000E, /* 36Mhz Pixel Clock */
	79	.panel_type = 0x01, /* TFT */
	80	.data_lines = 0x03, /* 24 Bit RGB */
	81	.load_mode = 0x02, /* Frame Mode */
	82	.panel_color = 0,
bcc6cc9b	83	.gfx_format = GFXFORMAT_RGB24_UNPACKED,
62986875 SB	84	}
	85	};
	86	#endif
	87
1fdabedd SB	88	/* Timing definitions for FPGA */
	89	static const u32 gpmc_fpga[] = {
	90	FPGA_GPMC_CONFIG1,
	91	FPGA_GPMC_CONFIG2,
	92	FPGA_GPMC_CONFIG3,
	93	FPGA_GPMC_CONFIG4,
	94	FPGA_GPMC_CONFIG5,
	95	FPGA_GPMC_CONFIG6,
	96	};
	97
	98	#ifdef CONFIG_USB_EHCI
	99	static struct omap_usbhs_board_data usbhs_bdata = {
	100	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
	101	.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
	102	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
	103	};
	104
676ae068	105	int ehci_hcd_init(int index, struct ehci_hccr hccr, struct ehci_hcor hcor)
1fdabedd	106	{
676ae068	107	return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
1fdabedd SB	108	}
1fdabedd SB	109
676ae068	110	int ehci_hcd_stop(int index)
1fdabedd SB	111	{
	112	return omap_ehci_hcd_stop();
	113	}
	114	#endif
	115
	116
	117	static inline void fpga_reset(int nassert)
	118	{
	119	gpio_set_value(FPGA_RESET, !nassert);
	120	}
	121
	122	int fpga_pgm_fn(int nassert, int nflush, int cookie)
	123	{
	124	debug("%s:%d: FPGA PROGRAM ", __func__, __LINE__);
	125
	126	gpio_set_value(FPGA_PROG, !nassert);
	127
	128	return nassert;
	129	}
	130
	131	int fpga_init_fn(int cookie)
	132	{
	133	return !gpio_get_value(FPGA_INIT);
	134	}
	135
	136	int fpga_done_fn(int cookie)
	137	{
	138	return gpio_get_value(FPGA_DONE);
	139	}
	140
	141	int fpga_pre_config_fn(int cookie)
	142	{
	143	debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
	144
	145	/* Setting GPIOs for programming Mode */
	146	gpio_request(FPGA_RESET, "FPGA_RESET");
	147	gpio_direction_output(FPGA_RESET, 1);
	148	gpio_request(FPGA_PROG, "FPGA_PROG");
	149	gpio_direction_output(FPGA_PROG, 1);
	150	gpio_request(FPGA_CCLK, "FPGA_CCLK");
	151	gpio_direction_output(FPGA_CCLK, 1);
	152	gpio_request(FPGA_DIN, "FPGA_DIN");
	153	gpio_direction_output(FPGA_DIN, 0);
	154	gpio_request(FPGA_INIT, "FPGA_INIT");
	155	gpio_direction_input(FPGA_INIT);
	156	gpio_request(FPGA_DONE, "FPGA_DONE");
	157	gpio_direction_input(FPGA_DONE);
	158
	159	/* Be sure that signal are deasserted */
	160	gpio_set_value(FPGA_RESET, 1);
	161	gpio_set_value(FPGA_PROG, 1);
	162
	163	return 0;
	164	}
	165
	166	int fpga_post_config_fn(int cookie)
	167	{
	168	debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__);
	169
472d5460	170	fpga_reset(true);
1fdabedd	171	udelay(100);
472d5460	172	fpga_reset(false);
1fdabedd SB	173
	174	return 0;
	175	}
	176
	177	/* Write program to the FPGA */
	178	int fpga_wr_fn(int nassert_write, int flush, int cookie)
	179	{
	180	gpio_set_value(FPGA_DIN, nassert_write);
	181
	182	return nassert_write;
	183	}
	184
	185	int fpga_clk_fn(int assert_clk, int flush, int cookie)
	186	{
	187	gpio_set_value(FPGA_CCLK, assert_clk);
	188
	189	return assert_clk;
	190	}
	191
	192	Xilinx_Spartan3_Slave_Serial_fns mt_ventoux_fpga_fns = {
	193	fpga_pre_config_fn,
	194	fpga_pgm_fn,
	195	fpga_clk_fn,
	196	fpga_init_fn,
	197	fpga_done_fn,
	198	fpga_wr_fn,
	199	fpga_post_config_fn,
	200	};
	201
	202	Xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
	203	(void *)&mt_ventoux_fpga_fns, 0);
	204
	205	/* Initialize the FPGA */
	206	static void mt_ventoux_init_fpga(void)
	207	{
	208	fpga_pre_config_fn(0);
	209
	210	/* Setting CS1 for FPGA access */
	211	enable_gpmc_cs_config(gpmc_fpga, &gpmc_cfg->cs[1],
	212	FPGA_BASE_ADDR, GPMC_SIZE_128M);
	213
	214	fpga_init();
	215	fpga_add(fpga_xilinx, &fpga);
	216	}
	217
	218	/*
	219	* Routine: board_init
	220	* Description: Early hardware init.
	221	*/
	222	int board_init(void)
	223	{
	224	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
	225
	226	/* boot param addr */
	227	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
	228
	229	mt_ventoux_init_fpga();
	230
ff530fc7 SB	231	/* GPIO_140: speaker #mute */
	232	MUX_VAL(CP(MCBSP3_DX), (IEN \| PTU \| EN \| M4))
	233	/* GPIO_141: Buzz Hi */
	234	MUX_VAL(CP(MCBSP3_DR), (IEN \| PTU \| EN \| M4))
	235
	236	/* Turning off the buzzer */
	237	gpio_request(BUZZER, "BUZZER_MUTE");
	238	gpio_request(SPEAKER, "SPEAKER");
	239	gpio_direction_output(BUZZER, 0);
	240	gpio_direction_output(SPEAKER, 0);
	241
9f670540 SB	242	/* Activate USB power */
	243	gpio_request(USB1_PWR, "USB1_PWR");
	244	gpio_request(USB2_PWR, "USB2_PWR");
	245	gpio_direction_output(USB1_PWR, 1);
	246	gpio_direction_output(USB2_PWR, 1);
	247
1fdabedd SB	248	return 0;
	249	}
	250
31f5b651	251	#ifndef CONFIG_SPL_BUILD
9d5fc239 SB	252	int misc_init_r(void)
	253	{
	254	char *eth_addr;
31f5b651 SB	255	struct tam3517_module_info info;
31f5b651 SB	256	int ret;
9d5fc239	257
31f5b651	258	TAM3517_READ_EEPROM(&info, ret);
9d5fc239 SB	259	dieid_num_r();
9d5fc239 SB	260
31f5b651	261	if (ret)
9d5fc239	262	return 0;
31f5b651 SB	263	eth_addr = getenv("ethaddr");
	264	if (!eth_addr)
	265	TAM3517_READ_MAC_FROM_EEPROM(&info);
9d5fc239	266
31f5b651	267	TAM3517_PRINT_SOM_INFO(&info);
9d5fc239 SB	268	return 0;
9d5fc239 SB	269	}
31f5b651	270	#endif
9d5fc239	271
1fdabedd SB	272	/*
	273	* Routine: set_muxconf_regs
	274	* Description: Setting up the configuration Mux registers specific to the
	275	* hardware. Many pins need to be moved from protect to primary
	276	* mode.
	277	*/
	278	void set_muxconf_regs(void)
	279	{
	280	MUX_MT_VENTOUX();
	281	}
	282
	283	/*
	284	* Initializes on-chip ethernet controllers.
	285	* to override, implement board_eth_init()
	286	*/
	287	int board_eth_init(bd_t *bis)
	288	{
	289	davinci_emac_initialize();
	290	return 0;
	291	}
	292
	293	#if defined(CONFIG_OMAP_HSMMC) && \
	294	!defined(CONFIG_SPL_BUILD)
	295	int board_mmc_init(bd_t *bis)
	296	{
e3913f56	297	return omap_mmc_init(0, 0, 0, -1, -1);
1fdabedd SB	298	}
1fdabedd SB	299	#endif
62986875 SB	300
	301	#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
	302	int board_video_init(void)
	303	{
	304	struct prcm prcm_base = (struct prcm )PRCM_BASE;
	305	struct panel_config *panel = &lcd_cfg[0];
	306	char *s;
	307	u32 index = 0;
	308
	309	void *fb;
	310
	311	fb = (void *)0x88000000;
	312
	313	s = getenv("panel");
	314	if (s) {
	315	index = simple_strtoul(s, NULL, 10);
	316	if (index < ARRAY_SIZE(lcd_cfg))
	317	panel = &lcd_cfg[index];
	318	else
	319	return 0;
	320	}
	321
	322	panel->frame_buffer = fb;
	323	printf("Panel: %dx%d\n", panel_resolution[index].xres,
	324	panel_resolution[index].yres);
	325	panel->lcd_size = (panel_resolution[index].yres - 1) << 16 \|
	326	(panel_resolution[index].xres - 1);
	327
	328	gpio_request(LCD_PWR, "LCD Power");
	329	gpio_request(LCD_PON_PIN, "LCD Pon");
	330	gpio_direction_output(LCD_PWR, 0);
	331	gpio_direction_output(LCD_PON_PIN, 1);
	332
	333
	334	setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
	335	setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
	336
	337	omap3_dss_panel_config(panel);
	338	omap3_dss_enable();
	339
	340	return 0;
	341	}
	342	#endif