]> git.ipfire.org Git - thirdparty/u-boot.git/blame - board/theadorable/theadorable.c
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""
[thirdparty/u-boot.git] / board / theadorable / theadorable.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
b20c38a9 2/*
54055ff7 3 * Copyright (C) 2015-2019 Stefan Roese <sr@denx.de>
b20c38a9
SR
4 */
5
d678a59d 6#include <common.h>
09140113 7#include <command.h>
54055ff7 8#include <console.h>
54504de2 9#include <dm.h>
169a8550 10#include <i2c.h>
5255932f 11#include <init.h>
90526e9f 12#include <net.h>
169a8550 13#include <pci.h>
54055ff7
SR
14#if !defined(CONFIG_SPL_BUILD)
15#include <bootcount.h>
16#endif
401d1c4f 17#include <asm/global_data.h>
ced0d849 18#include <asm/gpio.h>
b20c38a9
SR
19#include <asm/io.h>
20#include <asm/arch/cpu.h>
21#include <asm/arch/soc.h>
c05ed00a 22#include <linux/delay.h>
aea02abe 23#include <linux/mbus.h>
b20c38a9
SR
24#ifdef CONFIG_NET
25#include <netdev.h>
26#endif
c3a4d1c3 27#include <u-boot/crc.h>
aea02abe 28#include "theadorable.h"
b20c38a9
SR
29
30#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
31#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
32
33DECLARE_GLOBAL_DATA_PTR;
34
ced0d849
SR
35#define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
36#define PHY_CHANNEL_RX_CTRL0_REG(port, chan) \
37 (MV_USB_PHY_BASE + ((port) << 12) + ((chan) << 6) + 0x8)
38
b20c38a9
SR
39#define THEADORABLE_GPP_OUT_ENA_LOW 0x00336780
40#define THEADORABLE_GPP_OUT_ENA_MID 0x00003cf0
41#define THEADORABLE_GPP_OUT_ENA_HIGH (~(0x0))
42
43#define THEADORABLE_GPP_OUT_VAL_LOW 0x2c0c983f
44#define THEADORABLE_GPP_OUT_VAL_MID 0x0007000c
45#define THEADORABLE_GPP_OUT_VAL_HIGH 0x00000000
46
ced0d849
SR
47#define GPIO_USB0_PWR_ON 18
48#define GPIO_USB1_PWR_ON 19
49
169a8550
SR
50#define PEX_SWITCH_NOT_FOUNT_LIMIT 3
51
52#define STM_I2C_BUS 1
53#define STM_I2C_ADDR 0x27
54#define REBOOT_DELAY 1000 /* reboot-delay in ms */
54055ff7 55#define ABORT_TIMEOUT 3000 /* 3 seconds reboot abort timeout */
169a8550 56
b20c38a9
SR
57/* DDR3 static configuration */
58static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = {
59 {0x00001400, 0x7301ca28}, /* DDR SDRAM Configuration Register */
60 {0x00001404, 0x30000800}, /* Dunit Control Low Register */
61 {0x00001408, 0x44149887}, /* DDR SDRAM Timing (Low) Register */
62 {0x0000140C, 0x38d93fc7}, /* DDR SDRAM Timing (High) Register */
63 {0x00001410, 0x1b100001}, /* DDR SDRAM Address Control Register */
64 {0x00001424, 0x0000f3ff}, /* Dunit Control High Register */
65 {0x00001428, 0x000f8830}, /* ODT Timing (Low) Register */
66 {0x0000142C, 0x014c50f4}, /* DDR3 Timing Register */
67 {0x0000147C, 0x0000c671}, /* ODT Timing (High) Register */
68
69 {0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */
70 {0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */
71 {0x000014A0, 0x00000001}, /* DRAM FIFO Control Register */
72 {0x000014A8, 0x00000101}, /* AXI Control Register */
73
74 /*
75 * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the
76 * training sequence
77 */
78 {0x000200e8, 0x3fff0e01},
79 {0x00020184, 0x3fffffe0}, /* Close fast path Window to - 2G */
80
81 {0x0001504, 0x7fffffe1}, /* CS0 Size */
82 {0x000150C, 0x00000000}, /* CS1 Size */
83 {0x0001514, 0x00000000}, /* CS2 Size */
84 {0x000151C, 0x00000000}, /* CS3 Size */
85
86 {0x00020220, 0x00000007}, /* Reserved */
87
88 {0x00001538, 0x00000009}, /* Read Data Sample Delays Register */
89 {0x0000153C, 0x00000009}, /* Read Data Ready Delay Register */
90
91 {0x000015D0, 0x00000650}, /* MR0 */
92 {0x000015D4, 0x00000044}, /* MR1 */
93 {0x000015D8, 0x00000010}, /* MR2 */
94 {0x000015DC, 0x00000000}, /* MR3 */
95 {0x000015E0, 0x00000001},
96 {0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */
97 {0x000015EC, 0xf800a225}, /* DDR PHY */
98
99 /* Recommended Settings from Marvell for 4 x 16 bit devices: */
100 {0x000014C0, 0x192424c9}, /* DRAM addr and Ctrl Driving Strenght*/
101 {0x000014C4, 0x0aaa24c9}, /* DRAM Data and DQS Driving Strenght */
102
103 {0x0, 0x0}
104};
105
106static MV_DRAM_MODES board_ddr_modes[MV_DDR3_MODES_NUMBER] = {
107 {"theadorable_1333-667", 0x3, 0x5, 0x0, A0, ddr3_theadorable, NULL},
108};
109
110extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
111
112/*
113 * Lane0 - PCIE0.0 X1 (to WIFI Module)
114 * Lane5 - SATA0
115 * Lane6 - SATA1
116 * Lane7 - SGMII0 (to Ethernet Phy)
117 * Lane8-11 - PCIE2.0 X4 (to PEX Switch)
118 * all other lanes are disabled
119 */
120MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = {
121 { MV_PEX_ROOT_COMPLEX, 0x22200001, 0x00001111,
122 { PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4,
123 PEX_BUS_DISABLED },
124 0x0060, serdes_change_m_phy
125 },
126};
127
1304f4bb
SR
128/*
129 * Define a board-specific detection pulse-width array for the SerDes PCIe
130 * interfaces. If not defined in the board code, the default of currently 2
131 * is used. Values from 0...3 are possible (2 bits).
132 */
133u8 serdes_pex_pulse_width[4] = { 0, 2, 2, 2 };
134
b20c38a9
SR
135MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
136{
137 /* Only one mode supported for this board */
138 return &board_ddr_modes[0];
139}
140
0a590243 141MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
b20c38a9
SR
142{
143 return &theadorable_serdes_cfg[0];
144}
145
9ed00b07
SR
146u8 board_sat_r_get(u8 dev_num, u8 reg)
147{
0a590243
SR
148 /* Bit x enables PCI 2.0 link capabilities instead of PCI 1.x */
149 return 0xe; /* PEX port 0 is PCIe Gen1, PEX port 1..3 PCIe Gen2 */
9ed00b07
SR
150}
151
61b70422
SR
152#define PCIE_LNK_CTRL_STAT_2_OFF 0x0090
153#define PCIE_LNK_CTRL_STAT_2_DEEM_BIT BIT(6)
154
155static void pcie_set_deemphasis(u32 base)
156{
157 u32 reg;
158
159 reg = readl((void *)base + PCIE_LNK_CTRL_STAT_2_OFF);
160 reg |= PCIE_LNK_CTRL_STAT_2_DEEM_BIT;
161 writel(reg, (void *)base + PCIE_LNK_CTRL_STAT_2_OFF);
162}
163
b20c38a9
SR
164int board_early_init_f(void)
165{
166 /* Configure MPP */
167 writel(0x00000000, MVEBU_MPP_BASE + 0x00);
168 writel(0x03300000, MVEBU_MPP_BASE + 0x04);
169 writel(0x00000033, MVEBU_MPP_BASE + 0x08);
170 writel(0x00000000, MVEBU_MPP_BASE + 0x0c);
171 writel(0x11110000, MVEBU_MPP_BASE + 0x10);
172 writel(0x00221100, MVEBU_MPP_BASE + 0x14);
173 writel(0x00000000, MVEBU_MPP_BASE + 0x18);
174 writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
175 writel(0x00000000, MVEBU_MPP_BASE + 0x20);
176
177 /* Configure GPIO */
178 writel(THEADORABLE_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
179 writel(THEADORABLE_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
180 writel(THEADORABLE_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
181 writel(THEADORABLE_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
182 writel(THEADORABLE_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
183 writel(THEADORABLE_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
184
61b70422
SR
185 /*
186 * Set deephasis bit in the PCIe configuration of both PCIe ports
187 * used on this board.
188 *
189 * This needs to be done very early, even before the SERDES setup
190 * code is run. This way, the first link will already be established
191 * with this setup. Testing has shown, that this results in a more
192 * stable PCIe link with better signal quality.
193 */
194 pcie_set_deemphasis(MVEBU_REG_PCIE_BASE); /* Port 0 */
195 pcie_set_deemphasis(MVEBU_REG_PCIE_BASE + 0x2000); /* Port 2 */
196
b20c38a9
SR
197 return 0;
198}
199
200int board_init(void)
201{
ced0d849
SR
202 int ret;
203
b20c38a9
SR
204 /* adress of boot parameters */
205 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
206
aea02abe
SR
207 /*
208 * Map SPI devices via MBUS so that they can be accessed via
209 * the SPI direct access mode
210 */
5692e5b2 211 mbus_dt_setup_win(SPI_BUS0_DEV1_BASE, SPI_BUS0_DEV1_SIZE,
aea02abe 212 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI0_CS1);
5692e5b2 213 mbus_dt_setup_win(SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE,
aea02abe
SR
214 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2);
215
ced0d849
SR
216 /*
217 * Set RX Channel Control 0 Register:
218 * Tests have shown, that setting the LPF_COEF from 0 (1/8)
219 * to 3 (1/1) results in a more stable USB connection.
220 */
221 setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 1), 0xc);
222 setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 2), 0xc);
223 setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 3), 0xc);
224
225 /* Toggle USB power */
226 ret = gpio_request(GPIO_USB0_PWR_ON, "USB0_PWR_ON");
227 if (ret < 0)
228 return ret;
229 gpio_direction_output(GPIO_USB0_PWR_ON, 0);
230 ret = gpio_request(GPIO_USB1_PWR_ON, "USB1_PWR_ON");
231 if (ret < 0)
232 return ret;
233 gpio_direction_output(GPIO_USB1_PWR_ON, 0);
234 mdelay(1);
235 gpio_set_value(GPIO_USB0_PWR_ON, 1);
236 gpio_set_value(GPIO_USB1_PWR_ON, 1);
237
b20c38a9
SR
238 return 0;
239}
240
241int checkboard(void)
242{
aea02abe
SR
243 board_fpga_add();
244
b20c38a9
SR
245 return 0;
246}
247
248#ifdef CONFIG_NET
b75d8dc5 249int board_eth_init(struct bd_info *bis)
b20c38a9
SR
250{
251 cpu_eth_init(bis); /* Built in controller(s) come first */
252 return pci_eth_init(bis);
253}
254#endif
255
54055ff7 256#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_LATE_INIT)
169a8550
SR
257int board_late_init(void)
258{
259 pci_dev_t bdf;
260 ulong bootcount;
261
262 /*
263 * Check if the PEX switch is detected (somtimes its not available
264 * on the PCIe bus). In this case, try to recover by issuing a
265 * soft-reset or even a power-cycle, depending on the bootcounter
266 * value.
267 */
268 bdf = pci_find_device(PCI_VENDOR_ID_PLX, 0x8619, 0);
269 if (bdf == -1) {
54055ff7 270 unsigned long start_time = get_timer(0);
169a8550
SR
271 u8 i2c_buf[8];
272 int ret;
273
274 /* PEX switch not found! */
275 bootcount = bootcount_load();
276 printf("Failed to find PLX PEX-switch (bootcount=%ld)\n",
277 bootcount);
54055ff7
SR
278
279 /*
280 * The user can exit this boot-loop in the error case by
281 * hitting Ctrl-C. So wait some time for this key here.
282 */
283 printf("Continue booting with Ctrl-C, otherwise rebooting\n");
284 do {
285 /* Handle control-c and timeouts */
286 if (ctrlc()) {
287 printf("PEX error boot-loop aborted!\n");
288 return 0;
289 }
290 } while (get_timer(start_time) < ABORT_TIMEOUT);
291
292
293 /*
294 * At this stage the bootcounter has not been incremented
295 * yet. We need to do this manually here to get an actually
296 * working bootcounter in this error case.
297 */
298 bootcount_inc();
299
169a8550 300 if (bootcount > PEX_SWITCH_NOT_FOUNT_LIMIT) {
2f7dae27 301 struct udevice *dev;
169a8550
SR
302
303 printf("Issuing power-switch via uC!\n");
2f7dae27
SR
304 ret = i2c_get_chip_for_busnum(STM_I2C_BUS, STM_I2C_ADDR,
305 1, &dev);
306 if (ret) {
307 printf("Error selecting STM on I2C bus (ret=%d)\n",
308 ret);
309 printf("Issuing soft-reset...\n");
310 /* default handling: SOFT reset */
311 do_reset(NULL, 0, 0, NULL);
312 }
313
169a8550
SR
314 i2c_buf[0] = STM_I2C_ADDR << 1;
315 i2c_buf[1] = 0xc5; /* cmd */
316 i2c_buf[2] = 0x01; /* enable */
317 /* Delay before reboot */
318 i2c_buf[3] = REBOOT_DELAY & 0x00ff;
319 i2c_buf[4] = (REBOOT_DELAY & 0xff00) >> 8;
320 /* Delay before shutdown */
321 i2c_buf[5] = 0x00;
322 i2c_buf[6] = 0x00;
323 i2c_buf[7] = crc8(0x72, &i2c_buf[0], 7);
324
2f7dae27 325 ret = dm_i2c_write(dev, 0, &i2c_buf[1], 7);
169a8550
SR
326 if (ret) {
327 printf("I2C write error (ret=%d)\n", ret);
328 printf("Issuing soft-reset...\n");
329 /* default handling: SOFT reset */
330 do_reset(NULL, 0, 0, NULL);
331 }
332
333 /* Wait for power-cycle to occur... */
334 printf("Waiting for power-cycle via uC...\n");
335 while (1)
336 ;
337 } else {
338 printf("Issuing soft-reset...\n");
339 /* default handling: SOFT reset */
340 do_reset(NULL, 0, 0, NULL);
341 }
342 }
343
344 return 0;
345}
346#endif
1ec2a80b
SR
347
348#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_PCI)
54504de2 349static int pcie_get_link_speed_width(pci_dev_t bdf, int *speed, int *width)
1ec2a80b 350{
54504de2 351 struct udevice *dev;
1ec2a80b 352 u16 ven_id, dev_id;
54504de2
SR
353 u16 lnksta;
354 int ret;
355 int pos;
1ec2a80b 356
54504de2
SR
357 /*
358 * Check if the PCIe device is detected (sometimes its not available
359 * on the PCIe bus)
360 */
361 ret = dm_pci_bus_find_bdf(bdf, &dev);
362 if (ret)
363 return -ENODEV;
364
365 /* PCIe device found */
366 dm_pci_read_config16(dev, PCI_VENDOR_ID, &ven_id);
367 dm_pci_read_config16(dev, PCI_DEVICE_ID, &dev_id);
368 printf("Detected PCIe device: VendorID 0x%04x DeviceId 0x%04x @ BDF %d.%d.%d\n",
369 ven_id, dev_id, PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
370
371 /* Now read EXP_LNKSTA register */
372 pos = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
373 dm_pci_read_config16(dev, pos + PCI_EXP_LNKSTA, &lnksta);
374 *speed = lnksta & PCI_EXP_LNKSTA_CLS;
375 *width = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
1ec2a80b 376
54504de2
SR
377 return 0;
378}
379
380/*
381 * U-Boot cmd to test for the presence of the directly connected PCIe devices
382 * the theadorable board. This cmd can be used by U-Boot scripts for automated
383 * testing, if the PCIe setup is correct. Meaning, that all PCIe devices are
384 * correctly detected and the link speed and width is corrent.
385 *
386 * Here a short script that may be used for an automated test. It results in
387 * an endless reboot loop, if the PCIe devices are detected correctly. If at
388 * any time a problem is detected (PCIe device not available or link is
389 * incorrect), then booting will halt. So just use this "bootcmd" and let the
390 * board run over a longer time (e.g. one night) and if the board still reboots
391 * after this time, then everything is okay.
392 *
393 * bootcmd=echo bootcount=$bootcount; pcie ;if test $? -eq 0;
394 * then echo PCIe status okay, resetting...; reset; else;
395 * echo PCIe status NOT okay, hanging (bootcount=$bootcount); fi;
396 */
397int do_pcie_test(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
398{
399 pci_dev_t bdf;
400 int speed;
401 int width;
402 int ret;
1ec2a80b 403
54504de2
SR
404 if (argc != 1)
405 return cmd_usage(cmdtp);
1ec2a80b
SR
406
407 /*
54504de2 408 * Check if the PCIe device is detected (sometimes its not available
1ec2a80b
SR
409 * on the PCIe bus)
410 */
54504de2
SR
411
412 /* Check for PCIe device on PCIe port/bus 0 */
413 bdf = PCI_BDF(0, 1, 0);
414 ret = pcie_get_link_speed_width(bdf, &speed, &width);
415 if (ret) {
1ec2a80b 416 /* PCIe device not found! */
54504de2
SR
417 printf("Failed to find PCIe device @ BDF %d.%d.%d\n",
418 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
419 return CMD_RET_FAILURE;
420 }
1ec2a80b 421
54504de2
SR
422 printf("Established speed=%d width=%d\n", speed, width);
423 if ((speed != 1 || width != 1)) {
424 printf("Detected incorrect speed/width!!!\n");
425 return CMD_RET_FAILURE;
1ec2a80b
SR
426 }
427
54504de2
SR
428 /* Check for PCIe device on PCIe port/bus 1 */
429 bdf = PCI_BDF(1, 1, 0);
430 ret = pcie_get_link_speed_width(bdf, &speed, &width);
431 if (ret) {
432 /* PCIe device not found! */
433 printf("Failed to find PCIe device @ BDF %d.%d.%d\n",
434 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
435 return CMD_RET_FAILURE;
436 }
437
438 printf("Established speed=%d width=%d\n", speed, width);
439 if ((speed != 2 || width != 4)) {
440 printf("Detected incorrect speed/width!!!\n");
441 return CMD_RET_FAILURE;
442 }
443
444 return CMD_RET_SUCCESS;
1ec2a80b
SR
445}
446
447U_BOOT_CMD(
54504de2
SR
448 pcie, 1, 0, do_pcie_test,
449 "Test for presence of a PCIe devices with correct link",
450 ""
1ec2a80b
SR
451);
452#endif