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Merge branch 'master' of git://git.denx.de/u-boot-arm
[people/ms/u-boot.git] / board / ti / am335x / board.c
CommitLineData
e363426e
PK		 1/*
2 * board.c
3 *
4 * Board functions for TI AM335X based boards
5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 *
1a459660 8 * SPDX-License-Identifier: GPL-2.0+
e363426e
PK		 9 */
10
11#include <common.h>
12#include <errno.h>
13#include <spl.h>
14#include <asm/arch/cpu.h>
15#include <asm/arch/hardware.h>
16#include <asm/arch/omap.h>
17#include <asm/arch/ddr_defs.h>
18#include <asm/arch/clock.h>
19#include <asm/arch/gpio.h>
20#include <asm/arch/mmc_host_def.h>
21#include <asm/arch/sys_proto.h>
cd8845d7 22#include <asm/arch/mem.h>
e363426e
PK		 23#include <asm/io.h>
24#include <asm/emif.h>
25#include <asm/gpio.h>
26#include <i2c.h>
27#include <miiphy.h>
28#include <cpsw.h>
9721027a
TR		 29#include <power/tps65217.h>
30#include <power/tps65910.h>
6843918e
TR		 31#include <environment.h>
32#include <watchdog.h>
e363426e
PK		 33#include "board.h"
34
35DECLARE_GLOBAL_DATA_PTR;
36
e363426e
PK		 37/* GPIO that controls power to DDR on EVM-SK */
38#define GPIO_DDR_VTT_EN 7
39
40static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
41
e363426e
PK		 42/*
43 * Read header information from EEPROM into global structure.
44 */
ace4275e 45static int read_eeprom(struct am335x_baseboard_id *header)
e363426e
PK		 46{
47 /* Check if baseboard eeprom is available */
48 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
49 puts("Could not probe the EEPROM; something fundamentally "
50 "wrong on the I2C bus.\n");
51 return -ENODEV;
52 }
53
54 /* read the eeprom using i2c */
ace4275e
TR		 55 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
56 sizeof(struct am335x_baseboard_id))) {
e363426e
PK		 57 puts("Could not read the EEPROM; something fundamentally"
58 " wrong on the I2C bus.\n");
59 return -EIO;
60 }
61
ace4275e 62 if (header->magic != 0xEE3355AA) {
e363426e
PK		 63 /*
64 * read the eeprom using i2c again,
65 * but use only a 1 byte address
66 */
ace4275e
TR		 67 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
68 sizeof(struct am335x_baseboard_id))) {
e363426e
PK		 69 puts("Could not read the EEPROM; something "
70 "fundamentally wrong on the I2C bus.\n");
71 return -EIO;
72 }
73
ace4275e 74 if (header->magic != 0xEE3355AA) {
e363426e 75 printf("Incorrect magic number (0x%x) in EEPROM\n",
ace4275e 76 header->magic);
e363426e
PK		 77 return -EINVAL;
78 }
79 }
80
81 return 0;
82}
83
c5c7a7c3 84#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
c00f69db 85static const struct ddr_data ddr2_data = {
c7d35bef
PK		 86 .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
87 (MT47H128M16RT25E_RD_DQS<<20) |
88 (MT47H128M16RT25E_RD_DQS<<10) |
89 (MT47H128M16RT25E_RD_DQS<<0)),
90 .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
91 (MT47H128M16RT25E_WR_DQS<<20) |
92 (MT47H128M16RT25E_WR_DQS<<10) |
93 (MT47H128M16RT25E_WR_DQS<<0)),
94 .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
95 (MT47H128M16RT25E_PHY_WRLVL<<20) |
96 (MT47H128M16RT25E_PHY_WRLVL<<10) |
97 (MT47H128M16RT25E_PHY_WRLVL<<0)),
98 .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
99 (MT47H128M16RT25E_PHY_GATELVL<<20) |
100 (MT47H128M16RT25E_PHY_GATELVL<<10) |
101 (MT47H128M16RT25E_PHY_GATELVL<<0)),
102 .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
103 (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
104 (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
105 (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
106 .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
107 (MT47H128M16RT25E_PHY_WR_DATA<<20) |
108 (MT47H128M16RT25E_PHY_WR_DATA<<10) |
109 (MT47H128M16RT25E_PHY_WR_DATA<<0)),
c00f69db 110};
e363426e 111
c00f69db 112static const struct cmd_control ddr2_cmd_ctrl_data = {
c7d35bef 113 .cmd0csratio = MT47H128M16RT25E_RATIO,
c7d35bef 114 .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
c00f69db 115
c7d35bef 116 .cmd1csratio = MT47H128M16RT25E_RATIO,
c7d35bef 117 .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
c00f69db 118
c7d35bef 119 .cmd2csratio = MT47H128M16RT25E_RATIO,
c7d35bef 120 .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
c00f69db
PK		 121};
122
123static const struct emif_regs ddr2_emif_reg_data = {
c7d35bef
PK		 124 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
125 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
126 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
127 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
128 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
129 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
c00f69db
PK		 130};
131
132static const struct ddr_data ddr3_data = {
c7d35bef
PK		 133 .datardsratio0 = MT41J128MJT125_RD_DQS,
134 .datawdsratio0 = MT41J128MJT125_WR_DQS,
135 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
136 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
c00f69db
PK		 137};
138
c7ba18ad
TR		 139static const struct ddr_data ddr3_beagleblack_data = {
140 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
141 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
142 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
143 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
c7ba18ad
TR		 144};
145
13526f71
JL		 146static const struct ddr_data ddr3_evm_data = {
147 .datardsratio0 = MT41J512M8RH125_RD_DQS,
148 .datawdsratio0 = MT41J512M8RH125_WR_DQS,
149 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
150 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
13526f71
JL		 151};
152
c00f69db 153static const struct cmd_control ddr3_cmd_ctrl_data = {
c7d35bef 154 .cmd0csratio = MT41J128MJT125_RATIO,
c7d35bef 155 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
c00f69db 156
c7d35bef 157 .cmd1csratio = MT41J128MJT125_RATIO,
c7d35bef 158 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
c00f69db 159
c7d35bef 160 .cmd2csratio = MT41J128MJT125_RATIO,
c7d35bef 161 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
c00f69db
PK		 162};
163
c7ba18ad
TR		 164static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
165 .cmd0csratio = MT41K256M16HA125E_RATIO,
c7ba18ad
TR		 166 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
167
168 .cmd1csratio = MT41K256M16HA125E_RATIO,
c7ba18ad
TR		 169 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
170
171 .cmd2csratio = MT41K256M16HA125E_RATIO,
c7ba18ad
TR		 172 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
173};
174
13526f71
JL		 175static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
176 .cmd0csratio = MT41J512M8RH125_RATIO,
13526f71
JL		 177 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
178
179 .cmd1csratio = MT41J512M8RH125_RATIO,
13526f71
JL		 180 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
181
182 .cmd2csratio = MT41J512M8RH125_RATIO,
13526f71
JL		 183 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
184};
185
c00f69db 186static struct emif_regs ddr3_emif_reg_data = {
c7d35bef
PK		 187 .sdram_config = MT41J128MJT125_EMIF_SDCFG,
188 .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
189 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
190 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
191 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
192 .zq_config = MT41J128MJT125_ZQ_CFG,
59dcf970
VH		 193 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
194 PHY_EN_DYN_PWRDN,
c00f69db 195};
13526f71 196
c7ba18ad
TR		 197static struct emif_regs ddr3_beagleblack_emif_reg_data = {
198 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
199 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
200 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
201 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
202 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
203 .zq_config = MT41K256M16HA125E_ZQ_CFG,
204 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
205};
206
13526f71
JL		 207static struct emif_regs ddr3_evm_emif_reg_data = {
208 .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
209 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
210 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
211 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
212 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
213 .zq_config = MT41J512M8RH125_ZQ_CFG,
59dcf970
VH		 214 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
215 PHY_EN_DYN_PWRDN,
13526f71 216};
12d7a474
PK		 217
218#ifdef CONFIG_SPL_OS_BOOT
219int spl_start_uboot(void)
220{
221 /* break into full u-boot on 'c' */
222 return (serial_tstc() && serial_getc() == 'c');
223}
224#endif
225
94d77fb6
LV		 226#define OSC (V_OSCK/1000000)
227const struct dpll_params dpll_ddr = {
228 266, OSC-1, 1, -1, -1, -1, -1};
229const struct dpll_params dpll_ddr_evm_sk = {
230 303, OSC-1, 1, -1, -1, -1, -1};
231const struct dpll_params dpll_ddr_bone_black = {
232 400, OSC-1, 1, -1, -1, -1, -1};
233
9721027a
TR		 234void am33xx_spl_board_init(void)
235{
236 struct am335x_baseboard_id header;
9721027a
TR		 237 int mpu_vdd;
238
239 if (read_eeprom(&header) < 0)
240 puts("Could not get board ID.\n");
241
242 /* Get the frequency */
52f7d844 243 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
9721027a
TR		 244
245 if (board_is_bone(&header) || board_is_bone_lt(&header)) {
246 /* BeagleBone PMIC Code */
247 int usb_cur_lim;
248
249 /*
250 * Only perform PMIC configurations if board rev > A1
251 * on Beaglebone White
252 */
253 if (board_is_bone(&header) && !strncmp(header.version,
254 "00A1", 4))
255 return;
256
257 if (i2c_probe(TPS65217_CHIP_PM))
258 return;
259
260 /*
261 * On Beaglebone White we need to ensure we have AC power
262 * before increasing the frequency.
263 */
264 if (board_is_bone(&header)) {
265 uchar pmic_status_reg;
266 if (tps65217_reg_read(TPS65217_STATUS,
267 &pmic_status_reg))
268 return;
269 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
270 puts("No AC power, disabling frequency switch\n");
271 return;
272 }
273 }
274
275 /*
276 * Override what we have detected since we know if we have
277 * a Beaglebone Black it supports 1GHz.
278 */
279 if (board_is_bone_lt(&header))
52f7d844 280 dpll_mpu_opp100.m = MPUPLL_M_1000;
9721027a
TR		 281
282 /*
283 * Increase USB current limit to 1300mA or 1800mA and set
284 * the MPU voltage controller as needed.
285 */
52f7d844 286 if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
9721027a
TR		 287 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
288 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
289 } else {
290 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
291 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
292 }
293
294 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
295 TPS65217_POWER_PATH,
296 usb_cur_lim,
297 TPS65217_USB_INPUT_CUR_LIMIT_MASK))
298 puts("tps65217_reg_write failure\n");
299
52f7d844
SK		 300 /* Set DCDC3 (CORE) voltage to 1.125V */
301 if (tps65217_voltage_update(TPS65217_DEFDCDC3,
302 TPS65217_DCDC_VOLT_SEL_1125MV)) {
303 puts("tps65217_voltage_update failure\n");
304 return;
305 }
306
307 /* Set CORE Frequencies to OPP100 */
308 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
9721027a
TR		 309
310 /* Set DCDC2 (MPU) voltage */
311 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
312 puts("tps65217_voltage_update failure\n");
313 return;
314 }
315
316 /*
317 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
318 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
319 */
320 if (board_is_bone(&header)) {
321 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
322 TPS65217_DEFLS1,
323 TPS65217_LDO_VOLTAGE_OUT_3_3,
324 TPS65217_LDO_MASK))
325 puts("tps65217_reg_write failure\n");
326 } else {
327 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
328 TPS65217_DEFLS1,
329 TPS65217_LDO_VOLTAGE_OUT_1_8,
330 TPS65217_LDO_MASK))
331 puts("tps65217_reg_write failure\n");
332 }
333
334 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
335 TPS65217_DEFLS2,
336 TPS65217_LDO_VOLTAGE_OUT_3_3,
337 TPS65217_LDO_MASK))
338 puts("tps65217_reg_write failure\n");
339 } else {
340 int sil_rev;
341
342 /*
343 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
344 * MPU frequencies we support we use a CORE voltage of
345 * 1.1375V. For MPU voltage we need to switch based on
346 * the frequency we are running at.
347 */
348 if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
349 return;
350
351 /*
352 * Depending on MPU clock and PG we will need a different
353 * VDD to drive at that speed.
354 */
355 sil_rev = readl(&cdev->deviceid) >> 28;
52f7d844
SK		 356 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
357 dpll_mpu_opp100.m);
9721027a
TR		 358
359 /* Tell the TPS65910 to use i2c */
360 tps65910_set_i2c_control();
361
362 /* First update MPU voltage. */
363 if (tps65910_voltage_update(MPU, mpu_vdd))
364 return;
365
366 /* Second, update the CORE voltage. */
367 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
368 return;
52f7d844
SK		 369
370 /* Set CORE Frequencies to OPP100 */
371 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
9721027a
TR		 372 }
373
374 /* Set MPU Frequency to what we detected now that voltages are set */
52f7d844 375 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
9721027a
TR		 376}
377
94d77fb6
LV		 378const struct dpll_params *get_dpll_ddr_params(void)
379{
380 struct am335x_baseboard_id header;
381
382 enable_i2c0_pin_mux();
6789e84e 383 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
94d77fb6
LV		 384 if (read_eeprom(&header) < 0)
385 puts("Could not get board ID.\n");
386
387 if (board_is_evm_sk(&header))
388 return &dpll_ddr_evm_sk;
389 else if (board_is_bone_lt(&header))
390 return &dpll_ddr_bone_black;
391 else if (board_is_evm_15_or_later(&header))
392 return &dpll_ddr_evm_sk;
393 else
394 return &dpll_ddr;
395}
396
0660481a 397void set_uart_mux_conf(void)
e363426e 398{
6422b70b 399#ifdef CONFIG_SERIAL1
e363426e 400 enable_uart0_pin_mux();
6422b70b
AB		 401#endif /* CONFIG_SERIAL1 */
402#ifdef CONFIG_SERIAL2
403 enable_uart1_pin_mux();
404#endif /* CONFIG_SERIAL2 */
405#ifdef CONFIG_SERIAL3
406 enable_uart2_pin_mux();
407#endif /* CONFIG_SERIAL3 */
408#ifdef CONFIG_SERIAL4
409 enable_uart3_pin_mux();
410#endif /* CONFIG_SERIAL4 */
411#ifdef CONFIG_SERIAL5
412 enable_uart4_pin_mux();
413#endif /* CONFIG_SERIAL5 */
414#ifdef CONFIG_SERIAL6
415 enable_uart5_pin_mux();
416#endif /* CONFIG_SERIAL6 */
0660481a 417}
e363426e 418
0660481a
HS		 419void set_mux_conf_regs(void)
420{
421 __maybe_unused struct am335x_baseboard_id header;
e363426e 422
0660481a
HS		 423 if (read_eeprom(&header) < 0)
424 puts("Could not get board ID.\n");
e363426e 425
0660481a
HS		 426 enable_board_pin_mux(&header);
427}
e363426e 428
965de8b9
LV		 429const struct ctrl_ioregs ioregs_evmsk = {
430 .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
431 .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
432 .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
433 .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
434 .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
435};
436
437const struct ctrl_ioregs ioregs_bonelt = {
438 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
439 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
440 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
441 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
442 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
443};
444
445const struct ctrl_ioregs ioregs_evm15 = {
446 .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
447 .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
448 .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
449 .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
450 .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
451};
452
453const struct ctrl_ioregs ioregs = {
454 .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
455 .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
456 .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
457 .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
458 .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
459};
460
0660481a
HS		 461void sdram_init(void)
462{
463 __maybe_unused struct am335x_baseboard_id header;
95cb69fa 464
ace4275e 465 if (read_eeprom(&header) < 0)
e363426e
PK		 466 puts("Could not get board ID.\n");
467
ace4275e 468 if (board_is_evm_sk(&header)) {
e363426e
PK		 469 /*
470 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
471 * This is safe enough to do on older revs.
472 */
473 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
474 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
475 }
476
ace4275e 477 if (board_is_evm_sk(&header))
965de8b9 478 config_ddr(303, &ioregs_evmsk, &ddr3_data,
3ba65f97 479 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
ace4275e 480 else if (board_is_bone_lt(&header))
965de8b9 481 config_ddr(400, &ioregs_bonelt,
c7ba18ad
TR		 482 &ddr3_beagleblack_data,
483 &ddr3_beagleblack_cmd_ctrl_data,
484 &ddr3_beagleblack_emif_reg_data, 0);
ace4275e 485 else if (board_is_evm_15_or_later(&header))
965de8b9 486 config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
3ba65f97 487 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
c00f69db 488 else
965de8b9 489 config_ddr(266, &ioregs, &ddr2_data,
3ba65f97 490 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
e363426e 491}
0660481a 492#endif
e363426e
PK		 493
494/*
495 * Basic board specific setup. Pinmux has been handled already.
496 */
497int board_init(void)
498{
6843918e
TR		 499#if defined(CONFIG_HW_WATCHDOG)
500 hw_watchdog_init();
501#endif
502
73feefdc 503 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
2c17e6d1 504#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
98b5c269 505 gpmc_init();
cd8845d7 506#endif
e363426e
PK		 507 return 0;
508}
509
044fc14b
TR		 510#ifdef CONFIG_BOARD_LATE_INIT
511int board_late_init(void)
512{
513#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
514 char safe_string[HDR_NAME_LEN + 1];
ace4275e
TR		 515 struct am335x_baseboard_id header;
516
517 if (read_eeprom(&header) < 0)
518 puts("Could not get board ID.\n");
044fc14b
TR		 519
520 /* Now set variables based on the header. */
521 strncpy(safe_string, (char *)header.name, sizeof(header.name));
522 safe_string[sizeof(header.name)] = 0;
523 setenv("board_name", safe_string);
524
525 strncpy(safe_string, (char *)header.version, sizeof(header.version));
526 safe_string[sizeof(header.version)] = 0;
527 setenv("board_rev", safe_string);
528#endif
529
530 return 0;
531}
532#endif
533
c0e66793
IY		 534#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
535 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
e363426e
PK		 536static void cpsw_control(int enabled)
537{
538 /* VTP can be added here */
539
540 return;
541}
542
543static struct cpsw_slave_data cpsw_slaves[] = {
544 {
545 .slave_reg_ofs = 0x208,
546 .sliver_reg_ofs = 0xd80,
547 .phy_id = 0,
548 },
549 {
550 .slave_reg_ofs = 0x308,
551 .sliver_reg_ofs = 0xdc0,
552 .phy_id = 1,
553 },
554};
555
556static struct cpsw_platform_data cpsw_data = {
81df2bab
MP		 557 .mdio_base = CPSW_MDIO_BASE,
558 .cpsw_base = CPSW_BASE,
e363426e
PK		 559 .mdio_div = 0xff,
560 .channels = 8,
561 .cpdma_reg_ofs = 0x800,
562 .slaves = 1,
563 .slave_data = cpsw_slaves,
564 .ale_reg_ofs = 0xd00,
565 .ale_entries = 1024,
566 .host_port_reg_ofs = 0x108,
567 .hw_stats_reg_ofs = 0x900,
2bf36ac6 568 .bd_ram_ofs = 0x2000,
e363426e
PK		 569 .mac_control = (1 << 5),
570 .control = cpsw_control,
571 .host_port_num = 0,
572 .version = CPSW_CTRL_VERSION_2,
573};
d2aa1154 574#endif
e363426e 575
d2aa1154
IY		 576#if defined(CONFIG_DRIVER_TI_CPSW) || \
577 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
e363426e
PK		 578int board_eth_init(bd_t *bis)
579{
d2aa1154 580 int rv, n = 0;
e363426e
PK		 581 uint8_t mac_addr[6];
582 uint32_t mac_hi, mac_lo;
ace4275e 583 __maybe_unused struct am335x_baseboard_id header;
e363426e 584
c0e66793
IY		 585 /* try reading mac address from efuse */
586 mac_lo = readl(&cdev->macid0l);
587 mac_hi = readl(&cdev->macid0h);
588 mac_addr[0] = mac_hi & 0xFF;
589 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
590 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
591 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
592 mac_addr[4] = mac_lo & 0xFF;
593 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
594
595#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
596 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
597 if (!getenv("ethaddr")) {
598 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
e363426e
PK		 599
600 if (is_valid_ether_addr(mac_addr))
601 eth_setenv_enetaddr("ethaddr", mac_addr);
e363426e
PK		 602 }
603
a662e0c3 604#ifdef CONFIG_DRIVER_TI_CPSW
ace4275e
TR		 605 if (read_eeprom(&header) < 0)
606 puts("Could not get board ID.\n");
607
608 if (board_is_bone(&header) || board_is_bone_lt(&header) ||
609 board_is_idk(&header)) {
e363426e
PK		 610 writel(MII_MODE_ENABLE, &cdev->miisel);
611 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
612 PHY_INTERFACE_MODE_MII;
613 } else {
dafd4db3 614 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
e363426e
PK		 615 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
616 PHY_INTERFACE_MODE_RGMII;
617 }
618
d2aa1154
IY		 619 rv = cpsw_register(&cpsw_data);
620 if (rv < 0)
621 printf("Error %d registering CPSW switch\n", rv);
622 else
623 n += rv;
a662e0c3 624#endif
1634e969
TR		 625
626 /*
627 *
628 * CPSW RGMII Internal Delay Mode is not supported in all PVT
629 * operating points. So we must set the TX clock delay feature
630 * in the AR8051 PHY. Since we only support a single ethernet
631 * device in U-Boot, we only do this for the first instance.
632 */
633#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
634#define AR8051_PHY_DEBUG_DATA_REG 0x1e
635#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
636#define AR8051_RGMII_TX_CLK_DLY 0x100
637
ace4275e 638 if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) {
1634e969
TR		 639 const char *devname;
640 devname = miiphy_get_current_dev();
641
642 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
643 AR8051_DEBUG_RGMII_CLK_DLY_REG);
644 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
645 AR8051_RGMII_TX_CLK_DLY);
646 }
d2aa1154 647#endif
c0e66793
IY		 648#if defined(CONFIG_USB_ETHER) && \
649 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
650 if (is_valid_ether_addr(mac_addr))
651 eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
652
d2aa1154
IY		 653 rv = usb_eth_initialize(bis);
654 if (rv < 0)
655 printf("Error %d registering USB_ETHER\n", rv);
656 else
657 n += rv;
658#endif
659 return n;
e363426e
PK		 660}
661#endif
"Das U-Boot" Source Tree