[people/ms/u-boot.git] / board / ti / dra7xx / evm.c

/*
 * (C) Copyright 2013
 * Texas Instruments Incorporated, <www.ti.com>
 *
 * Lokesh Vutla <lokeshvutla@ti.com>
 *
 * Based on previous work by:
 * Aneesh V       <aneesh@ti.com>
 * Steve Sakoman  <steve@sakoman.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <palmas.h>
#include <sata.h>
#include <linux/string.h>
#include <asm/gpio.h>
#include <usb.h>
#include <linux/usb/gadget.h>
#include <asm/arch/gpio.h>
#include <asm/arch/dra7xx_iodelay.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sata.h>
#include <environment.h>
#include <dwc3-uboot.h>
#include <dwc3-omap-uboot.h>
#include <ti-usb-phy-uboot.h>

#include "mux_data.h"
#include "../common/board_detect.h"

#define board_is_dra74x_evm()		board_ti_is("5777xCPU")
#define board_is_dra74x_revh_or_later() board_is_dra74x_evm() &&	\
				(strncmp("H", board_ti_get_rev(), 1) <= 0)

#ifdef CONFIG_DRIVER_TI_CPSW
#include <cpsw.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

/* GPIO 7_11 */
#define GPIO_DDR_VTT_EN 203

#define SYSINFO_BOARD_NAME_MAX_LEN	37

const struct omap_sysinfo sysinfo = {
	"Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
};

/**
 * @brief board_init
 *
 * @return 0
 */
int board_init(void)
{
	gpmc_init();
	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */

	return 0;
}

int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	char *name = "unknown";

	if (is_dra72x())
		name = "dra72x";
	else
		name = "dra7xx";

	set_board_info_env(name);

	omap_die_id_serial();
#endif
	return 0;
}

#ifdef CONFIG_SPL_BUILD
void do_board_detect(void)
{
	int rc;

	rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
				    CONFIG_EEPROM_CHIP_ADDRESS);
	if (rc)
		printf("ti_i2c_eeprom_init failed %d\n", rc);
}

#else

void do_board_detect(void)
{
	char *bname = NULL;
	int rc;

	rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
				    CONFIG_EEPROM_CHIP_ADDRESS);
	if (rc)
		printf("ti_i2c_eeprom_init failed %d\n", rc);

	if (board_is_dra74x_evm()) {
		bname = "DRA74x EVM";
	/* If EEPROM is not populated */
	} else {
		if (is_dra72x())
			bname = "DRA72x EVM";
		else
			bname = "DRA74x EVM";
	}

	if (bname)
		snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
			 "Board: %s REV %s\n", bname, board_ti_get_rev());
}
#endif	/* CONFIG_SPL_BUILD */

void set_muxconf_regs_essential(void)
{
	do_set_mux32((*ctrl)->control_padconf_core_base,
		     early_padconf, ARRAY_SIZE(early_padconf));
}

#ifdef CONFIG_IODELAY_RECALIBRATION
void recalibrate_iodelay(void)
{
	struct pad_conf_entry const *pads;
	struct iodelay_cfg_entry const *iodelay;
	int npads, niodelays;

	switch (omap_revision()) {
	case DRA722_ES1_0:
		pads = core_padconf_array_essential;
		npads = ARRAY_SIZE(core_padconf_array_essential);
		iodelay = iodelay_cfg_array;
		niodelays = ARRAY_SIZE(iodelay_cfg_array);
		break;
	case DRA752_ES1_0:
	case DRA752_ES1_1:
		pads = dra74x_core_padconf_array;
		npads = ARRAY_SIZE(dra74x_core_padconf_array);
		iodelay = dra742_es1_1_iodelay_cfg_array;
		niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
		break;
	default:
	case DRA752_ES2_0:
		pads = dra74x_core_padconf_array;
		npads = ARRAY_SIZE(dra74x_core_padconf_array);
		iodelay = dra742_es2_0_iodelay_cfg_array;
		niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
		/* Setup port1 and port2 for rgmii with 'no-id' mode */
		clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
				      RGMII1_ID_MODE_N_MASK);
		break;
	}
	__recalibrate_iodelay(pads, npads, iodelay, niodelays);
}
#endif

#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
int board_mmc_init(bd_t *bis)
{
	omap_mmc_init(0, 0, 0, -1, -1);
	omap_mmc_init(1, 0, 0, -1, -1);
	return 0;
}
#endif

#ifdef CONFIG_USB_DWC3
static struct dwc3_device usb_otg_ss1 = {
	.maximum_speed = USB_SPEED_SUPER,
	.base = DRA7_USB_OTG_SS1_BASE,
	.tx_fifo_resize = false,
	.index = 0,
};

static struct dwc3_omap_device usb_otg_ss1_glue = {
	.base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
	.index = 0,
};

static struct ti_usb_phy_device usb_phy1_device = {
	.pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
	.usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
	.usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
	.index = 0,
};

static struct dwc3_device usb_otg_ss2 = {
	.maximum_speed = USB_SPEED_SUPER,
	.base = DRA7_USB_OTG_SS2_BASE,
	.tx_fifo_resize = false,
	.index = 1,
};

static struct dwc3_omap_device usb_otg_ss2_glue = {
	.base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
	.index = 1,
};

static struct ti_usb_phy_device usb_phy2_device = {
	.usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
	.index = 1,
};

int board_usb_init(int index, enum usb_init_type init)
{
	enable_usb_clocks(index);
	switch (index) {
	case 0:
		if (init == USB_INIT_DEVICE) {
			usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
			usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
		} else {
			usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
			usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
		}

		ti_usb_phy_uboot_init(&usb_phy1_device);
		dwc3_omap_uboot_init(&usb_otg_ss1_glue);
		dwc3_uboot_init(&usb_otg_ss1);
		break;
	case 1:
		if (init == USB_INIT_DEVICE) {
			usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
			usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
		} else {
			usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
			usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
		}

		ti_usb_phy_uboot_init(&usb_phy2_device);
		dwc3_omap_uboot_init(&usb_otg_ss2_glue);
		dwc3_uboot_init(&usb_otg_ss2);
		break;
	default:
		printf("Invalid Controller Index\n");
	}

	return 0;
}

int board_usb_cleanup(int index, enum usb_init_type init)
{
	switch (index) {
	case 0:
	case 1:
		ti_usb_phy_uboot_exit(index);
		dwc3_uboot_exit(index);
		dwc3_omap_uboot_exit(index);
		break;
	default:
		printf("Invalid Controller Index\n");
	}
	disable_usb_clocks(index);
	return 0;
}

int usb_gadget_handle_interrupts(int index)
{
	u32 status;

	status = dwc3_omap_uboot_interrupt_status(index);
	if (status)
		dwc3_uboot_handle_interrupt(index);

	return 0;
}
#endif

#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
int spl_start_uboot(void)
{
	/* break into full u-boot on 'c' */
	if (serial_tstc() && serial_getc() == 'c')
		return 1;

#ifdef CONFIG_SPL_ENV_SUPPORT
	env_init();
	env_relocate_spec();
	if (getenv_yesno("boot_os") != 1)
		return 1;
#endif

	return 0;
}
#endif

#ifdef CONFIG_DRIVER_TI_CPSW
extern u32 *const omap_si_rev;

static void cpsw_control(int enabled)
{
	/* VTP can be added here */

	return;
}

static struct cpsw_slave_data cpsw_slaves[] = {
	{
		.slave_reg_ofs	= 0x208,
		.sliver_reg_ofs	= 0xd80,
		.phy_addr	= 2,
	},
	{
		.slave_reg_ofs	= 0x308,
		.sliver_reg_ofs	= 0xdc0,
		.phy_addr	= 3,
	},
};

static struct cpsw_platform_data cpsw_data = {
	.mdio_base		= CPSW_MDIO_BASE,
	.cpsw_base		= CPSW_BASE,
	.mdio_div		= 0xff,
	.channels		= 8,
	.cpdma_reg_ofs		= 0x800,
	.slaves			= 2,
	.slave_data		= cpsw_slaves,
	.ale_reg_ofs		= 0xd00,
	.ale_entries		= 1024,
	.host_port_reg_ofs	= 0x108,
	.hw_stats_reg_ofs	= 0x900,
	.bd_ram_ofs		= 0x2000,
	.mac_control		= (1 << 5),
	.control		= cpsw_control,
	.host_port_num		= 0,
	.version		= CPSW_CTRL_VERSION_2,
};

int board_eth_init(bd_t *bis)
{
	int ret;
	uint8_t mac_addr[6];
	uint32_t mac_hi, mac_lo;
	uint32_t ctrl_val;

	/* try reading mac address from efuse */
	mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
	mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
	mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	mac_addr[2] = mac_hi & 0xFF;
	mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
	mac_addr[4] = (mac_lo & 0xFF00) >> 8;
	mac_addr[5] = mac_lo & 0xFF;

	if (!getenv("ethaddr")) {
		printf("<ethaddr> not set. Validating first E-fuse MAC\n");

		if (is_valid_ethaddr(mac_addr))
			eth_setenv_enetaddr("ethaddr", mac_addr);
	}

	mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
	mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
	mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	mac_addr[2] = mac_hi & 0xFF;
	mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
	mac_addr[4] = (mac_lo & 0xFF00) >> 8;
	mac_addr[5] = mac_lo & 0xFF;

	if (!getenv("eth1addr")) {
		if (is_valid_ethaddr(mac_addr))
			eth_setenv_enetaddr("eth1addr", mac_addr);
	}

	ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
	ctrl_val |= 0x22;
	writel(ctrl_val, (*ctrl)->control_core_control_io1);

	if (*omap_si_rev == DRA722_ES1_0)
		cpsw_data.active_slave = 1;

	ret = cpsw_register(&cpsw_data);
	if (ret < 0)
		printf("Error %d registering CPSW switch\n", ret);

	return ret;
}
#endif

#ifdef CONFIG_BOARD_EARLY_INIT_F
/* VTT regulator enable */
static inline void vtt_regulator_enable(void)
{
	if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
		return;

	/* Do not enable VTT for DRA722 */
	if (omap_revision() == DRA722_ES1_0)
		return;

	/*
	 * EVM Rev G and later use gpio7_11 for DDR3 termination.
	 * This is safe enough to do on older revs.
	 */
	gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
	gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}

int board_early_init_f(void)
{
	vtt_regulator_enable();
	return 0;
}
#endif
Commit	Line	Data
687054a7 LV	1	/*
	2	* (C) Copyright 2013
	3	* Texas Instruments Incorporated, <www.ti.com>
	4	*
	5	* Lokesh Vutla <lokeshvutla@ti.com>
	6	*
	7	* Based on previous work by:
	8	* Aneesh V <aneesh@ti.com>
	9	* Steve Sakoman <steve@sakoman.com>
	10	*
1a459660	11	* SPDX-License-Identifier: GPL-2.0+
687054a7 LV	12	*/
687054a7 LV	13	#include <common.h>
cb199102	14	#include <palmas.h>
e9024ef2	15	#include <sata.h>
25afe55d	16	#include <linux/string.h>
7b922523	17	#include <asm/gpio.h>
a17188c1 KVA	18	#include <usb.h>
a17188c1 KVA	19	#include <linux/usb/gadget.h>
7b922523	20	#include <asm/arch/gpio.h>
706dd348	21	#include <asm/arch/dra7xx_iodelay.h>
687054a7 LV	22	#include <asm/arch/sys_proto.h>
687054a7 LV	23	#include <asm/arch/mmc_host_def.h>
21914ee6	24	#include <asm/arch/sata.h>
79b079f3	25	#include <environment.h>
a17188c1 KVA	26	#include <dwc3-uboot.h>
	27	#include <dwc3-omap-uboot.h>
	28	#include <ti-usb-phy-uboot.h>
687054a7 LV	29
687054a7 LV	30	#include "mux_data.h"
25afe55d LV	31	#include "../common/board_detect.h"
	32
	33	#define board_is_dra74x_evm() board_ti_is("5777xCPU")
	34	#define board_is_dra74x_revh_or_later() board_is_dra74x_evm() && \
	35	(strncmp("H", board_ti_get_rev(), 1) <= 0)
687054a7	36
b1e26e3b M	37	#ifdef CONFIG_DRIVER_TI_CPSW
	38	#include <cpsw.h>
	39	#endif
	40
687054a7 LV	41	DECLARE_GLOBAL_DATA_PTR;
687054a7 LV	42
7b922523 LV	43	/* GPIO 7_11 */
	44	#define GPIO_DDR_VTT_EN 203
	45
25afe55d LV	46	#define SYSINFO_BOARD_NAME_MAX_LEN 37
25afe55d LV	47
687054a7	48	const struct omap_sysinfo sysinfo = {
25afe55d	49	"Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
687054a7 LV	50	};
	51
	52	/**
	53	* @brief board_init
	54	*
	55	* @return 0
	56	*/
	57	int board_init(void)
	58	{
	59	gpmc_init();
	60	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
	61
	62	return 0;
	63	}
	64
21914ee6 RQ	65	int board_late_init(void)
21914ee6 RQ	66	{
4ec3f6e5	67	#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
25afe55d LV	68	char *name = "unknown";
	69
	70	if (is_dra72x())
	71	name = "dra72x";
4ec3f6e5	72	else
25afe55d LV	73	name = "dra7xx";
	74
	75	set_board_info_env(name);
f12467d1	76
07815eb9	77	omap_die_id_serial();
4ec3f6e5	78	#endif
21914ee6 RQ	79	return 0;
	80	}
	81
25afe55d LV	82	#ifdef CONFIG_SPL_BUILD
	83	void do_board_detect(void)
	84	{
	85	int rc;
	86
	87	rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
	88	CONFIG_EEPROM_CHIP_ADDRESS);
	89	if (rc)
	90	printf("ti_i2c_eeprom_init failed %d\n", rc);
	91	}
	92
	93	#else
	94
	95	void do_board_detect(void)
	96	{
	97	char *bname = NULL;
	98	int rc;
	99
	100	rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
	101	CONFIG_EEPROM_CHIP_ADDRESS);
	102	if (rc)
	103	printf("ti_i2c_eeprom_init failed %d\n", rc);
	104
	105	if (board_is_dra74x_evm()) {
	106	bname = "DRA74x EVM";
	107	/* If EEPROM is not populated */
	108	} else {
	109	if (is_dra72x())
	110	bname = "DRA72x EVM";
	111	else
	112	bname = "DRA74x EVM";
	113	}
	114
	115	if (bname)
	116	snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
	117	"Board: %s REV %s\n", bname, board_ti_get_rev());
	118	}
	119	#endif /* CONFIG_SPL_BUILD */
	120
687054a7 LV	121	void set_muxconf_regs_essential(void)
	122	{
	123	do_set_mux32((*ctrl)->control_padconf_core_base,
706dd348	124	early_padconf, ARRAY_SIZE(early_padconf));
687054a7 LV	125	}
687054a7 LV	126
706dd348 LV	127	#ifdef CONFIG_IODELAY_RECALIBRATION
	128	void recalibrate_iodelay(void)
	129	{
03589234 NM	130	struct pad_conf_entry const *pads;
	131	struct iodelay_cfg_entry const *iodelay;
	132	int npads, niodelays;
	133
	134	switch (omap_revision()) {
	135	case DRA722_ES1_0:
	136	pads = core_padconf_array_essential;
	137	npads = ARRAY_SIZE(core_padconf_array_essential);
	138	iodelay = iodelay_cfg_array;
	139	niodelays = ARRAY_SIZE(iodelay_cfg_array);
	140	break;
	141	case DRA752_ES1_0:
	142	case DRA752_ES1_1:
	143	pads = dra74x_core_padconf_array;
	144	npads = ARRAY_SIZE(dra74x_core_padconf_array);
	145	iodelay = dra742_es1_1_iodelay_cfg_array;
	146	niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
	147	break;
	148	default:
	149	case DRA752_ES2_0:
	150	pads = dra74x_core_padconf_array;
	151	npads = ARRAY_SIZE(dra74x_core_padconf_array);
	152	iodelay = dra742_es2_0_iodelay_cfg_array;
	153	niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
76cff2b1 NM	154	/* Setup port1 and port2 for rgmii with 'no-id' mode */
	155	clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK \|
	156	RGMII1_ID_MODE_N_MASK);
03589234	157	break;
27d170af	158	}
03589234	159	__recalibrate_iodelay(pads, npads, iodelay, niodelays);
706dd348 LV	160	}
	161	#endif
	162
687054a7 LV	163	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
	164	int board_mmc_init(bd_t *bis)
	165	{
	166	omap_mmc_init(0, 0, 0, -1, -1);
	167	omap_mmc_init(1, 0, 0, -1, -1);
	168	return 0;
	169	}
	170	#endif
b1e26e3b	171
a17188c1 KVA	172	#ifdef CONFIG_USB_DWC3
	173	static struct dwc3_device usb_otg_ss1 = {
	174	.maximum_speed = USB_SPEED_SUPER,
	175	.base = DRA7_USB_OTG_SS1_BASE,
	176	.tx_fifo_resize = false,
	177	.index = 0,
	178	};
	179
	180	static struct dwc3_omap_device usb_otg_ss1_glue = {
	181	.base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
	182	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
a17188c1 KVA	183	.index = 0,
	184	};
	185
	186	static struct ti_usb_phy_device usb_phy1_device = {
	187	.pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
	188	.usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
	189	.usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
	190	.index = 0,
	191	};
	192
	193	static struct dwc3_device usb_otg_ss2 = {
	194	.maximum_speed = USB_SPEED_SUPER,
	195	.base = DRA7_USB_OTG_SS2_BASE,
	196	.tx_fifo_resize = false,
	197	.index = 1,
	198	};
	199
	200	static struct dwc3_omap_device usb_otg_ss2_glue = {
	201	.base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
	202	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
a17188c1 KVA	203	.index = 1,
	204	};
	205
	206	static struct ti_usb_phy_device usb_phy2_device = {
	207	.usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
	208	.index = 1,
	209	};
	210
	211	int board_usb_init(int index, enum usb_init_type init)
	212	{
6f1af1e3	213	enable_usb_clocks(index);
a17188c1 KVA	214	switch (index) {
	215	case 0:
	216	if (init == USB_INIT_DEVICE) {
	217	usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
	218	usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
	219	} else {
	220	usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
	221	usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
	222	}
	223
	224	ti_usb_phy_uboot_init(&usb_phy1_device);
	225	dwc3_omap_uboot_init(&usb_otg_ss1_glue);
	226	dwc3_uboot_init(&usb_otg_ss1);
	227	break;
	228	case 1:
	229	if (init == USB_INIT_DEVICE) {
	230	usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
	231	usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
	232	} else {
	233	usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
	234	usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
	235	}
	236
	237	ti_usb_phy_uboot_init(&usb_phy2_device);
	238	dwc3_omap_uboot_init(&usb_otg_ss2_glue);
	239	dwc3_uboot_init(&usb_otg_ss2);
	240	break;
	241	default:
	242	printf("Invalid Controller Index\n");
	243	}
	244
	245	return 0;
	246	}
	247
	248	int board_usb_cleanup(int index, enum usb_init_type init)
	249	{
	250	switch (index) {
	251	case 0:
	252	case 1:
	253	ti_usb_phy_uboot_exit(index);
	254	dwc3_uboot_exit(index);
	255	dwc3_omap_uboot_exit(index);
	256	break;
	257	default:
	258	printf("Invalid Controller Index\n");
	259	}
6f1af1e3	260	disable_usb_clocks(index);
a17188c1 KVA	261	return 0;
	262	}
	263
2d48aa69	264	int usb_gadget_handle_interrupts(int index)
a17188c1 KVA	265	{
	266	u32 status;
	267
2d48aa69	268	status = dwc3_omap_uboot_interrupt_status(index);
a17188c1	269	if (status)
2d48aa69	270	dwc3_uboot_handle_interrupt(index);
a17188c1 KVA	271
	272	return 0;
	273	}
	274	#endif
	275
79b079f3 TR	276	#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
	277	int spl_start_uboot(void)
	278	{
	279	/* break into full u-boot on 'c' */
	280	if (serial_tstc() && serial_getc() == 'c')
	281	return 1;
	282
	283	#ifdef CONFIG_SPL_ENV_SUPPORT
	284	env_init();
	285	env_relocate_spec();
	286	if (getenv_yesno("boot_os") != 1)
	287	return 1;
	288	#endif
	289
	290	return 0;
	291	}
	292	#endif
	293
b1e26e3b	294	#ifdef CONFIG_DRIVER_TI_CPSW
4c8014b9 M	295	extern u32 *const omap_si_rev;
4c8014b9 M	296
b1e26e3b M	297	static void cpsw_control(int enabled)
	298	{
	299	/* VTP can be added here */
	300
	301	return;
	302	}
	303
	304	static struct cpsw_slave_data cpsw_slaves[] = {
	305	{
	306	.slave_reg_ofs = 0x208,
	307	.sliver_reg_ofs = 0xd80,
9c653aad	308	.phy_addr = 2,
b1e26e3b M	309	},
	310	{
	311	.slave_reg_ofs = 0x308,
	312	.sliver_reg_ofs = 0xdc0,
9c653aad	313	.phy_addr = 3,
b1e26e3b M	314	},
	315	};
	316
	317	static struct cpsw_platform_data cpsw_data = {
	318	.mdio_base = CPSW_MDIO_BASE,
	319	.cpsw_base = CPSW_BASE,
	320	.mdio_div = 0xff,
	321	.channels = 8,
	322	.cpdma_reg_ofs = 0x800,
4c8014b9	323	.slaves = 2,
b1e26e3b M	324	.slave_data = cpsw_slaves,
	325	.ale_reg_ofs = 0xd00,
	326	.ale_entries = 1024,
	327	.host_port_reg_ofs = 0x108,
	328	.hw_stats_reg_ofs = 0x900,
	329	.bd_ram_ofs = 0x2000,
	330	.mac_control = (1 << 5),
	331	.control = cpsw_control,
	332	.host_port_num = 0,
	333	.version = CPSW_CTRL_VERSION_2,
	334	};
	335
	336	int board_eth_init(bd_t *bis)
	337	{
	338	int ret;
	339	uint8_t mac_addr[6];
	340	uint32_t mac_hi, mac_lo;
	341	uint32_t ctrl_val;
b1e26e3b M	342
	343	/* try reading mac address from efuse */
	344	mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
	345	mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
e0a1d598	346	mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
b1e26e3b	347	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
e0a1d598 M	348	mac_addr[2] = mac_hi & 0xFF;
e0a1d598 M	349	mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
b1e26e3b	350	mac_addr[4] = (mac_lo & 0xFF00) >> 8;
e0a1d598	351	mac_addr[5] = mac_lo & 0xFF;
b1e26e3b M	352
	353	if (!getenv("ethaddr")) {
	354	printf("<ethaddr> not set. Validating first E-fuse MAC\n");
	355
0adb5b76	356	if (is_valid_ethaddr(mac_addr))
b1e26e3b M	357	eth_setenv_enetaddr("ethaddr", mac_addr);
b1e26e3b M	358	}
8feb37b9 M	359
	360	mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
	361	mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
	362	mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
	363	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	364	mac_addr[2] = mac_hi & 0xFF;
	365	mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
	366	mac_addr[4] = (mac_lo & 0xFF00) >> 8;
	367	mac_addr[5] = mac_lo & 0xFF;
	368
	369	if (!getenv("eth1addr")) {
0adb5b76	370	if (is_valid_ethaddr(mac_addr))
8feb37b9 M	371	eth_setenv_enetaddr("eth1addr", mac_addr);
	372	}
	373
b1e26e3b M	374	ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
	375	ctrl_val \|= 0x22;
	376	writel(ctrl_val, (*ctrl)->control_core_control_io1);
	377
4c8014b9 M	378	if (*omap_si_rev == DRA722_ES1_0)
	379	cpsw_data.active_slave = 1;
	380
b1e26e3b M	381	ret = cpsw_register(&cpsw_data);
	382	if (ret < 0)
	383	printf("Error %d registering CPSW switch\n", ret);
	384
	385	return ret;
	386	}
	387	#endif
7b922523 LV	388
	389	#ifdef CONFIG_BOARD_EARLY_INIT_F
	390	/* VTT regulator enable */
	391	static inline void vtt_regulator_enable(void)
	392	{
	393	if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
	394	return;
	395
	396	/* Do not enable VTT for DRA722 */
	397	if (omap_revision() == DRA722_ES1_0)
	398	return;
	399
	400	/*
	401	* EVM Rev G and later use gpio7_11 for DDR3 termination.
	402	* This is safe enough to do on older revs.
	403	*/
	404	gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
	405	gpio_direction_output(GPIO_DDR_VTT_EN, 1);
	406	}
	407
	408	int board_early_init_f(void)
	409	{
	410	vtt_regulator_enable();
	411	return 0;
	412	}
	413	#endif