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687054a7 LV |
1 | /* |
2 | * (C) Copyright 2013 | |
3 | * Texas Instruments Incorporated, <www.ti.com> | |
4 | * | |
5 | * Sricharan R <r.sricharan@ti.com> | |
6 | * Nishant Kamat <nskamat@ti.com> | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
687054a7 LV |
9 | */ |
10 | #ifndef _MUX_DATA_DRA7XX_H_ | |
11 | #define _MUX_DATA_DRA7XX_H_ | |
12 | ||
13 | #include <asm/arch/mux_dra7xx.h> | |
14 | ||
15 | const struct pad_conf_entry core_padconf_array_essential[] = { | |
7f36c88f LV |
16 | {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */ |
17 | {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */ | |
18 | {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */ | |
19 | {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */ | |
20 | {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */ | |
21 | {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */ | |
22 | {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */ | |
23 | {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */ | |
24 | {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */ | |
25 | {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */ | |
26 | {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */ | |
27 | {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */ | |
28 | {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */ | |
29 | {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */ | |
30 | {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */ | |
31 | {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */ | |
32 | {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */ | |
33 | {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */ | |
34 | {UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */ | |
35 | {UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */ | |
36 | {UART1_CTSN, (IEN | PTU | PDIS | M3)}, /* UART1_CTSN */ | |
37 | {UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */ | |
38 | {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */ | |
39 | {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */ | |
dec7f748 M |
40 | {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */ |
41 | {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */ | |
42 | {RGMII0_TXC, (M0) }, | |
43 | {RGMII0_TXCTL, (M0) }, | |
44 | {RGMII0_TXD3, (M0) }, | |
45 | {RGMII0_TXD2, (M0) }, | |
46 | {RGMII0_TXD1, (M0) }, | |
47 | {RGMII0_TXD0, (M0) }, | |
48 | {RGMII0_RXC, (IEN | M0) }, | |
49 | {RGMII0_RXCTL, (IEN | M0) }, | |
50 | {RGMII0_RXD3, (IEN | M0) }, | |
51 | {RGMII0_RXD2, (IEN | M0) }, | |
52 | {RGMII0_RXD1, (IEN | M0) }, | |
53 | {RGMII0_RXD0, (IEN | M0) }, | |
e5ff845b M |
54 | {VIN2A_D12, (M3) }, |
55 | {VIN2A_D13, (M3) }, | |
56 | {VIN2A_D14, (M3) }, | |
57 | {VIN2A_D15, (M3) }, | |
58 | {VIN2A_D16, (M3) }, | |
59 | {VIN2A_D17, (M3) }, | |
60 | {VIN2A_D18, (IEN | M3)}, | |
61 | {VIN2A_D19, (IEN | M3)}, | |
62 | {VIN2A_D20, (IEN | M3)}, | |
63 | {VIN2A_D21, (IEN | M3)}, | |
64 | {VIN2A_D22, (IEN | M3)}, | |
65 | {VIN2A_D23, (IEN | M3)}, | |
247cdf04 MP |
66 | {GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */ |
67 | {GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */ | |
68 | {GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */ | |
69 | {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[1] */ | |
70 | {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[0] */ | |
71 | {GPMC_A18, (M1)}, /* QSPI1_SCLK */ | |
72 | {GPMC_A3, (IEN | PDIS | M1)}, /* QSPI1_CS2 */ | |
73 | {GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */ | |
74 | {GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */ | |
75 | {GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/ | |
834e91af | 76 | {USB2_DRVVBUS, (M0 | IEN | FSC) }, |
687054a7 LV |
77 | }; |
78 | #endif /* _MUX_DATA_DRA7XX_H_ */ |