[people/ms/u-boot.git] / board / ti / ks2_evm / board_k2g.c

/*
 * K2G EVM : Board initialization
 *
 * (C) Copyright 2015
 *     Texas Instruments Incorporated, <www.ti.com>
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/ti-common/keystone_net.h>
#include <asm/arch/psc_defs.h>
#include <asm/arch/mmc_host_def.h>
#include "mux-k2g.h"

#define SYS_CLK		24000000

unsigned int external_clk[ext_clk_count] = {
	[sys_clk]	=	SYS_CLK,
	[pa_clk]	=	SYS_CLK,
	[tetris_clk]	=	SYS_CLK,
	[ddr3a_clk]	=	SYS_CLK,
	[uart_clk]	=	SYS_CLK,
};

static struct pll_init_data main_pll_config = {MAIN_PLL, 100, 1, 4};
static struct pll_init_data tetris_pll_config = {TETRIS_PLL, 100, 1, 4};
static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4};
static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2};
static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10};

struct pll_init_data *get_pll_init_data(int pll)
{
	struct pll_init_data *data = NULL;

	switch (pll) {
	case MAIN_PLL:
		data = &main_pll_config;
		break;
	case TETRIS_PLL:
		data = &tetris_pll_config;
		break;
	case NSS_PLL:
		data = &nss_pll_config;
		break;
	case UART_PLL:
		data = &uart_pll_config;
		break;
	case DDR3_PLL:
		data = &ddr3_pll_config;
		break;
	default:
		data = NULL;
	}

	return data;
}

s16 divn_val[16] = {
	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
};

#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
int board_mmc_init(bd_t *bis)
{
	if (psc_enable_module(KS2_LPSC_MMC)) {
		printf("%s module enabled failed\n", __func__);
		return -1;
	}

	omap_mmc_init(0, 0, 0, -1, -1);
	omap_mmc_init(1, 0, 0, -1, -1);
	return 0;
}
#endif

#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
	init_plls();

	k2g_mux_config();

	return 0;
}
#endif

#ifdef CONFIG_SPL_BUILD
void spl_init_keystone_plls(void)
{
	init_plls();
}
#endif

#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
struct eth_priv_t eth_priv_cfg[] = {
	{
		.int_name	= "K2G_EMAC",
		.rx_flow	= 0,
		.phy_addr	= 0,
		.slave_port	= 1,
		.sgmii_link_type = SGMII_LINK_MAC_PHY,
		.phy_if          = PHY_INTERFACE_MODE_RGMII,
	},
};

int get_num_eth_ports(void)
{
	return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
}
#endif
Commit	Line	Data
bda920c6 VA	1	/*
	2	* K2G EVM : Board initialization
	3	*
	4	* (C) Copyright 2015
	5	* Texas Instruments Incorporated, <www.ti.com>
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9	#include <common.h>
	10	#include <asm/arch/clock.h>
91266ccb	11	#include <asm/ti-common/keystone_net.h>
3b68939f RQ	12	#include <asm/arch/psc_defs.h>
3b68939f RQ	13	#include <asm/arch/mmc_host_def.h>
dd78b8cf	14	#include "mux-k2g.h"
bda920c6	15
e6d71e1c VA	16	#define SYS_CLK 24000000
	17
	18	unsigned int external_clk[ext_clk_count] = {
	19	[sys_clk] = SYS_CLK,
	20	[pa_clk] = SYS_CLK,
	21	[tetris_clk] = SYS_CLK,
	22	[ddr3a_clk] = SYS_CLK,
	23	[uart_clk] = SYS_CLK,
	24	};
	25
bda920c6 VA	26	static struct pll_init_data main_pll_config = {MAIN_PLL, 100, 1, 4};
	27	static struct pll_init_data tetris_pll_config = {TETRIS_PLL, 100, 1, 4};
	28	static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4};
	29	static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2};
235dd6e8	30	static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10};
bda920c6 VA	31
	32	struct pll_init_data *get_pll_init_data(int pll)
	33	{
	34	struct pll_init_data *data = NULL;
	35
	36	switch (pll) {
	37	case MAIN_PLL:
	38	data = &main_pll_config;
	39	break;
	40	case TETRIS_PLL:
235dd6e8	41	data = &tetris_pll_config;
bda920c6 VA	42	break;
	43	case NSS_PLL:
	44	data = &nss_pll_config;
	45	break;
	46	case UART_PLL:
	47	data = &uart_pll_config;
	48	break;
	49	case DDR3_PLL:
235dd6e8	50	data = &ddr3_pll_config;
bda920c6 VA	51	break;
	52	default:
	53	data = NULL;
	54	}
	55
	56	return data;
	57	}
	58
	59	s16 divn_val[16] = {
	60	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
	61	};
	62
3b68939f RQ	63	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
	64	int board_mmc_init(bd_t *bis)
	65	{
	66	if (psc_enable_module(KS2_LPSC_MMC)) {
	67	printf("%s module enabled failed\n", __func__);
	68	return -1;
	69	}
	70
	71	omap_mmc_init(0, 0, 0, -1, -1);
	72	omap_mmc_init(1, 0, 0, -1, -1);
	73	return 0;
	74	}
	75	#endif
	76
bda920c6 VA	77	#ifdef CONFIG_BOARD_EARLY_INIT_F
	78	int board_early_init_f(void)
	79	{
	80	init_plls();
	81
dd78b8cf VA	82	k2g_mux_config();
dd78b8cf VA	83
bda920c6 VA	84	return 0;
	85	}
	86	#endif
	87
	88	#ifdef CONFIG_SPL_BUILD
	89	void spl_init_keystone_plls(void)
	90	{
	91	init_plls();
	92	}
	93	#endif
91266ccb VA	94
	95	#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
	96	struct eth_priv_t eth_priv_cfg[] = {
	97	{
	98	.int_name = "K2G_EMAC",
	99	.rx_flow = 0,
	100	.phy_addr = 0,
	101	.slave_port = 1,
	102	.sgmii_link_type = SGMII_LINK_MAC_PHY,
	103	.phy_if = PHY_INTERFACE_MODE_RGMII,
	104	},
	105	};
	106
	107	int get_num_eth_ports(void)
	108	{
	109	return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
	110	}
	111	#endif