[thirdparty/u-boot.git] / board / ti / ks2_evm / board_k2g.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * K2G EVM : Board initialization
 *
 * (C) Copyright 2015
 *     Texas Instruments Incorporated, <www.ti.com>
 */
#include <common.h>
#include <eeprom.h>
#include <env.h>
#include <hang.h>
#include <image.h>
#include <init.h>
#include <asm/arch/clock.h>
#include <asm/ti-common/keystone_net.h>
#include <asm/arch/psc_defs.h>
#include <asm/arch/mmc_host_def.h>
#include <fdtdec.h>
#include <i2c.h>
#include <remoteproc.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include "mux-k2g.h"
#include "../common/board_detect.h"

#define K2G_GP_AUDIO_CODEC_ADDRESS	0x1B

const unsigned int sysclk_array[MAX_SYSCLK] = {
	19200000,
	24000000,
	25000000,
	26000000,
};

unsigned int get_external_clk(u32 clk)
{
	unsigned int clk_freq;
	u8 sysclk_index = get_sysclk_index();

	switch (clk) {
	case sys_clk:
		clk_freq = sysclk_array[sysclk_index];
		break;
	case pa_clk:
		clk_freq = sysclk_array[sysclk_index];
		break;
	case tetris_clk:
		clk_freq = sysclk_array[sysclk_index];
		break;
	case ddr3a_clk:
		clk_freq = sysclk_array[sysclk_index];
		break;
	case uart_clk:
		clk_freq = sysclk_array[sysclk_index];
		break;
	default:
		clk_freq = 0;
		break;
	}

	return clk_freq;
}

int speeds[DEVSPEED_NUMSPDS] = {
	SPD400,
	SPD600,
	SPD800,
	SPD900,
	SPD1000,
	SPD900,
	SPD800,
	SPD600,
	SPD400,
	SPD200,
};

static int dev_speeds[DEVSPEED_NUMSPDS] = {
	SPD600,
	SPD800,
	SPD900,
	SPD1000,
	SPD900,
	SPD800,
	SPD600,
	SPD400,
};

static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = {
	[SYSCLK_19MHz] = {
		[SPD400]	= {MAIN_PLL, 125, 3, 2},
		[SPD600]	= {MAIN_PLL, 125, 2, 2},
		[SPD800]	= {MAIN_PLL, 250, 3, 2},
		[SPD900]	= {MAIN_PLL, 187, 2, 2},
		[SPD1000]	= {MAIN_PLL, 104, 1, 2},
	},
	[SYSCLK_24MHz] = {
		[SPD400]	= {MAIN_PLL, 100, 3, 2},
		[SPD600]	= {MAIN_PLL, 300, 6, 2},
		[SPD800]	= {MAIN_PLL, 200, 3, 2},
		[SPD900]	= {MAIN_PLL, 75, 1, 2},
		[SPD1000]	= {MAIN_PLL, 250, 3, 2},
	},
	[SYSCLK_25MHz] = {
		[SPD400]	= {MAIN_PLL, 32, 1, 2},
		[SPD600]	= {MAIN_PLL, 48, 1, 2},
		[SPD800]	= {MAIN_PLL, 64, 1, 2},
		[SPD900]	= {MAIN_PLL, 72, 1, 2},
		[SPD1000]	= {MAIN_PLL, 80, 1, 2},
	},
	[SYSCLK_26MHz] = {
		[SPD400]	= {MAIN_PLL, 400, 13, 2},
		[SPD600]	= {MAIN_PLL, 230, 5, 2},
		[SPD800]	= {MAIN_PLL, 123, 2, 2},
		[SPD900]	= {MAIN_PLL, 69, 1, 2},
		[SPD1000]	= {MAIN_PLL, 384, 5, 2},
	},
};

static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = {
	[SYSCLK_19MHz] = {
		[SPD200]	= {TETRIS_PLL, 625, 6, 10},
		[SPD400]	= {TETRIS_PLL, 125, 1, 6},
		[SPD600]	= {TETRIS_PLL, 125, 1, 4},
		[SPD800]	= {TETRIS_PLL, 333, 2, 4},
		[SPD900]	= {TETRIS_PLL, 187, 2, 2},
		[SPD1000]	= {TETRIS_PLL, 104, 1, 2},
	},
	[SYSCLK_24MHz] = {
		[SPD200]	= {TETRIS_PLL, 250, 3, 10},
		[SPD400]	= {TETRIS_PLL, 100, 1, 6},
		[SPD600]	= {TETRIS_PLL, 100, 1, 4},
		[SPD800]	= {TETRIS_PLL, 400, 3, 4},
		[SPD900]	= {TETRIS_PLL, 75, 1, 2},
		[SPD1000]	= {TETRIS_PLL, 250, 3, 2},
	},
	[SYSCLK_25MHz] = {
		[SPD200]	= {TETRIS_PLL, 80, 1, 10},
		[SPD400]	= {TETRIS_PLL, 96, 1, 6},
		[SPD600]	= {TETRIS_PLL, 96, 1, 4},
		[SPD800]	= {TETRIS_PLL, 128, 1, 4},
		[SPD900]	= {TETRIS_PLL, 72, 1, 2},
		[SPD1000]	= {TETRIS_PLL, 80, 1, 2},
	},
	[SYSCLK_26MHz] = {
		[SPD200]	= {TETRIS_PLL, 307, 4, 10},
		[SPD400]	= {TETRIS_PLL, 369, 4, 6},
		[SPD600]	= {TETRIS_PLL, 369, 4, 4},
		[SPD800]	= {TETRIS_PLL, 123, 1, 4},
		[SPD900]	= {TETRIS_PLL, 69, 1, 2},
		[SPD1000]	= {TETRIS_PLL, 384, 5, 2},
	},
};

static struct pll_init_data uart_pll_config[MAX_SYSCLK] = {
	[SYSCLK_19MHz] = {UART_PLL, 160, 1, 8},
	[SYSCLK_24MHz] = {UART_PLL, 128, 1, 8},
	[SYSCLK_25MHz] = {UART_PLL, 768, 5, 10},
	[SYSCLK_26MHz] = {UART_PLL, 384, 13, 2},
};

static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
	[SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2},
	[SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2},
	[SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2},
	[SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
};

static struct pll_init_data ddr3_pll_config_800[MAX_SYSCLK] = {
	[SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
	[SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
	[SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
	[SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
};

static struct pll_init_data ddr3_pll_config_1066[MAX_SYSCLK] = {
	[SYSCLK_19MHz] = {DDR3A_PLL, 194, 1, 14},
	[SYSCLK_24MHz] = {DDR3A_PLL, 156, 1, 14},
	[SYSCLK_25MHz] = {DDR3A_PLL, 149, 1, 14},
	[SYSCLK_26MHz] = {DDR3A_PLL, 144, 1, 14},
};

struct pll_init_data *get_pll_init_data(int pll)
{
	int speed;
	struct pll_init_data *data = NULL;
	u8 sysclk_index = get_sysclk_index();

	switch (pll) {
	case MAIN_PLL:
		speed = get_max_dev_speed(dev_speeds);
		data = &main_pll_config[sysclk_index][speed];
		break;
	case TETRIS_PLL:
		speed = get_max_arm_speed(speeds);
		data = &tetris_pll_config[sysclk_index][speed];
		break;
	case NSS_PLL:
		data = &nss_pll_config[sysclk_index];
		break;
	case UART_PLL:
		data = &uart_pll_config[sysclk_index];
		break;
	case DDR3_PLL:
		if (cpu_revision() & CPU_66AK2G1x) {
			speed = get_max_arm_speed(speeds);
			if (speed == SPD1000)
				data = &ddr3_pll_config_1066[sysclk_index];
			else
				data = &ddr3_pll_config_800[sysclk_index];
		} else {
			data = &ddr3_pll_config_800[sysclk_index];
		}
		break;
	default:
		data = NULL;
	}

	return data;
}

s16 divn_val[16] = {
	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
};

#if defined(CONFIG_MMC)
int board_mmc_init(struct bd_info *bis)
{
	if (psc_enable_module(KS2_LPSC_MMC)) {
		printf("%s module enabled failed\n", __func__);
		return -1;
	}

	if (board_is_k2g_gp() || board_is_k2g_g1())
		omap_mmc_init(0, 0, 0, -1, -1);

	omap_mmc_init(1, 0, 0, -1, -1);
	return 0;
}
#endif

#if defined(CONFIG_MULTI_DTB_FIT)
int board_fit_config_name_match(const char *name)
{
	bool eeprom_read = board_ti_was_eeprom_read();

	if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
		return 0;
	else if (!strcmp(name, "keystone-k2g-evm") &&
		(board_ti_is("66AK2GGP") || board_ti_is("66AK2GG1")))
		return 0;
	else if (!strcmp(name, "keystone-k2g-ice") &&
		 (board_ti_is("66AK2GIC") || board_is_k2g_i1()))
		return 0;
	else
		return -1;
}
#endif

#if defined(CONFIG_DTB_RESELECT)
static int k2g_alt_board_detect(void)
{
#if !CONFIG_IS_ENABLED(DM_I2C)
	int rc;

	rc = i2c_set_bus_num(1);
	if (rc)
		return rc;

	rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS);
	if (rc)
		return rc;
#else
	struct udevice *bus, *dev;
	int rc;

	rc = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus);
	if (rc)
		return rc;
	rc = dm_i2c_probe(bus, K2G_GP_AUDIO_CODEC_ADDRESS, 0, &dev);
	if (rc)
		return rc;
#endif
	ti_i2c_eeprom_am_set("66AK2GGP", "1.0X");

	return 0;
}

static void k2g_reset_mux_config(void)
{
	/* Unlock the reset mux register */
	clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);

	/* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
	clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
			RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);

	/* lock the reset mux register to prevent any spurious writes. */
	setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
}

int embedded_dtb_select(void)
{
	int rc;
	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
			CONFIG_EEPROM_CHIP_ADDRESS);
	if (rc) {
		rc = k2g_alt_board_detect();
		if (rc) {
			printf("Unable to do board detection\n");
			return -1;
		}
	}

	fdtdec_setup();

	k2g_mux_config();

	k2g_reset_mux_config();

	if (board_is_k2g_gp() || board_is_k2g_g1()) {
		/* deassert FLASH_HOLD */
		clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
			     BIT(9));
		setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
			     BIT(9));
	} else if (board_is_k2g_ice() || board_is_k2g_i1()) {
		/* GBE Phy workaround. For Phy to latch the input
		 * configuration, a GPIO reset is asserted at the
		 * Phy reset pin to latch configuration correctly after SoC
		 * reset. GPIO0 Pin 10 (Ball AA20) is used for this on ICE
		 * board. Just do a low to high transition.
		 */
		clrbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_DIR_OFFSET,
			     BIT(10));
		setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_CLRDATA_OFFSET,
			     BIT(10));
		/* Delay just to get a transition to high */
		udelay(100);
		setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_SETDATA_OFFSET,
			     BIT(10));
	}

	return 0;
}
#endif

#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
	int rc;

	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
			CONFIG_EEPROM_CHIP_ADDRESS);
	if (rc)
		printf("ti_i2c_eeprom_init failed %d\n", rc);

	board_ti_set_ethaddr(1);
#endif

#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	if (board_is_k2g_gp())
		env_set("board_name", "66AK2GGP\0");
	else if (board_is_k2g_g1())
		env_set("board_name", "66AK2GG1\0");
	else if (board_is_k2g_ice())
		env_set("board_name", "66AK2GIC\0");
	else if (board_is_k2g_i1())
		env_set("board_name", "66AK2GI1\0");
#endif
	return 0;
}
#endif

#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
	init_plls();

	k2g_mux_config();

	return 0;
}
#endif

#ifdef CONFIG_SPL_BUILD
void spl_init_keystone_plls(void)
{
	init_plls();
}
#endif

#ifdef CONFIG_TI_SECURE_DEVICE
void board_pmmc_image_process(ulong pmmc_image, size_t pmmc_size)
{
	int id = env_get_ulong("dev_pmmc", 10, 0);
	int ret;

	if (!rproc_is_initialized())
		rproc_init();

	ret = rproc_load(id, pmmc_image, pmmc_size);
	printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
	       id, pmmc_image, pmmc_size, ret ? " Failed!" : " Success!");

	if (!ret)
		rproc_start(id);
}

U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_PMMC, board_pmmc_image_process);
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
bda920c6 VA	2	/*
	3	* K2G EVM : Board initialization
	4	*
	5	* (C) Copyright 2015
	6	* Texas Instruments Incorporated, <www.ti.com>
bda920c6	7	*/
d678a59d TR	8	#include <common.h>
d678a59d TR	9	#include <eeprom.h>
9eef56db	10	#include <env.h>
db41d65a	11	#include <hang.h>
4d72caa5	12	#include <image.h>
5255932f	13	#include <init.h>
bda920c6	14	#include <asm/arch/clock.h>
91266ccb	15	#include <asm/ti-common/keystone_net.h>
3b68939f RQ	16	#include <asm/arch/psc_defs.h>
3b68939f RQ	17	#include <asm/arch/mmc_host_def.h>
5f48da9a CJF	18	#include <fdtdec.h>
5f48da9a CJF	19	#include <i2c.h>
58fac52d	20	#include <remoteproc.h>
cd93d625	21	#include <linux/bitops.h>
c05ed00a	22	#include <linux/delay.h>
dd78b8cf	23	#include "mux-k2g.h"
752a8311	24	#include "../common/board_detect.h"
bda920c6	25
5f48da9a CJF	26	#define K2G_GP_AUDIO_CODEC_ADDRESS 0x1B
5f48da9a CJF	27
c5f177de LV	28	const unsigned int sysclk_array[MAX_SYSCLK] = {
	29	19200000,
	30	24000000,
	31	25000000,
	32	26000000,
	33	};
	34
ee3c6532 LV	35	unsigned int get_external_clk(u32 clk)
	36	{
	37	unsigned int clk_freq;
	38	u8 sysclk_index = get_sysclk_index();
	39
	40	switch (clk) {
	41	case sys_clk:
	42	clk_freq = sysclk_array[sysclk_index];
	43	break;
	44	case pa_clk:
	45	clk_freq = sysclk_array[sysclk_index];
	46	break;
	47	case tetris_clk:
	48	clk_freq = sysclk_array[sysclk_index];
	49	break;
	50	case ddr3a_clk:
	51	clk_freq = sysclk_array[sysclk_index];
	52	break;
	53	case uart_clk:
	54	clk_freq = sysclk_array[sysclk_index];
	55	break;
	56	default:
	57	clk_freq = 0;
	58	break;
	59	}
	60
	61	return clk_freq;
	62	}
e6d71e1c	63
4849d954	64	int speeds[DEVSPEED_NUMSPDS] = {
ef76ebb1 LV	65	SPD400,
	66	SPD600,
	67	SPD800,
	68	SPD900,
	69	SPD1000,
	70	SPD900,
	71	SPD800,
	72	SPD600,
	73	SPD400,
	74	SPD200,
	75	};
	76
	77	static int dev_speeds[DEVSPEED_NUMSPDS] = {
	78	SPD600,
	79	SPD800,
	80	SPD900,
	81	SPD1000,
	82	SPD900,
	83	SPD800,
	84	SPD600,
	85	SPD400,
	86	};
	87
c5f177de LV	88	static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = {
	89	[SYSCLK_19MHz] = {
	90	[SPD400] = {MAIN_PLL, 125, 3, 2},
	91	[SPD600] = {MAIN_PLL, 125, 2, 2},
	92	[SPD800] = {MAIN_PLL, 250, 3, 2},
9cb5eaf2 LV	93	[SPD900] = {MAIN_PLL, 187, 2, 2},
9cb5eaf2 LV	94	[SPD1000] = {MAIN_PLL, 104, 1, 2},
c5f177de LV	95	},
	96	[SYSCLK_24MHz] = {
	97	[SPD400] = {MAIN_PLL, 100, 3, 2},
	98	[SPD600] = {MAIN_PLL, 300, 6, 2},
	99	[SPD800] = {MAIN_PLL, 200, 3, 2},
9cb5eaf2 LV	100	[SPD900] = {MAIN_PLL, 75, 1, 2},
9cb5eaf2 LV	101	[SPD1000] = {MAIN_PLL, 250, 3, 2},
c5f177de LV	102	},
	103	[SYSCLK_25MHz] = {
	104	[SPD400] = {MAIN_PLL, 32, 1, 2},
	105	[SPD600] = {MAIN_PLL, 48, 1, 2},
	106	[SPD800] = {MAIN_PLL, 64, 1, 2},
9cb5eaf2 LV	107	[SPD900] = {MAIN_PLL, 72, 1, 2},
9cb5eaf2 LV	108	[SPD1000] = {MAIN_PLL, 80, 1, 2},
c5f177de LV	109	},
	110	[SYSCLK_26MHz] = {
	111	[SPD400] = {MAIN_PLL, 400, 13, 2},
	112	[SPD600] = {MAIN_PLL, 230, 5, 2},
	113	[SPD800] = {MAIN_PLL, 123, 2, 2},
9cb5eaf2 LV	114	[SPD900] = {MAIN_PLL, 69, 1, 2},
9cb5eaf2 LV	115	[SPD1000] = {MAIN_PLL, 384, 5, 2},
c5f177de LV	116	},
	117	};
	118
	119	static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = {
	120	[SYSCLK_19MHz] = {
	121	[SPD200] = {TETRIS_PLL, 625, 6, 10},
	122	[SPD400] = {TETRIS_PLL, 125, 1, 6},
	123	[SPD600] = {TETRIS_PLL, 125, 1, 4},
	124	[SPD800] = {TETRIS_PLL, 333, 2, 4},
	125	[SPD900] = {TETRIS_PLL, 187, 2, 2},
	126	[SPD1000] = {TETRIS_PLL, 104, 1, 2},
	127	},
	128	[SYSCLK_24MHz] = {
	129	[SPD200] = {TETRIS_PLL, 250, 3, 10},
	130	[SPD400] = {TETRIS_PLL, 100, 1, 6},
	131	[SPD600] = {TETRIS_PLL, 100, 1, 4},
	132	[SPD800] = {TETRIS_PLL, 400, 3, 4},
	133	[SPD900] = {TETRIS_PLL, 75, 1, 2},
	134	[SPD1000] = {TETRIS_PLL, 250, 3, 2},
	135	},
	136	[SYSCLK_25MHz] = {
	137	[SPD200] = {TETRIS_PLL, 80, 1, 10},
	138	[SPD400] = {TETRIS_PLL, 96, 1, 6},
	139	[SPD600] = {TETRIS_PLL, 96, 1, 4},
	140	[SPD800] = {TETRIS_PLL, 128, 1, 4},
	141	[SPD900] = {TETRIS_PLL, 72, 1, 2},
	142	[SPD1000] = {TETRIS_PLL, 80, 1, 2},
	143	},
	144	[SYSCLK_26MHz] = {
	145	[SPD200] = {TETRIS_PLL, 307, 4, 10},
	146	[SPD400] = {TETRIS_PLL, 369, 4, 6},
	147	[SPD600] = {TETRIS_PLL, 369, 4, 4},
	148	[SPD800] = {TETRIS_PLL, 123, 1, 4},
	149	[SPD900] = {TETRIS_PLL, 69, 1, 2},
	150	[SPD1000] = {TETRIS_PLL, 384, 5, 2},
	151	},
ef76ebb1 LV	152	};
ef76ebb1 LV	153
c5f177de LV	154	static struct pll_init_data uart_pll_config[MAX_SYSCLK] = {
	155	[SYSCLK_19MHz] = {UART_PLL, 160, 1, 8},
	156	[SYSCLK_24MHz] = {UART_PLL, 128, 1, 8},
	157	[SYSCLK_25MHz] = {UART_PLL, 768, 5, 10},
	158	[SYSCLK_26MHz] = {UART_PLL, 384, 13, 2},
ef76ebb1 LV	159	};
ef76ebb1 LV	160
c5f177de LV	161	static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
	162	[SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2},
	163	[SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2},
	164	[SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2},
	165	[SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
	166	};
	167
4849d954	168	static struct pll_init_data ddr3_pll_config_800[MAX_SYSCLK] = {
c5f177de LV	169	[SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
	170	[SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
	171	[SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
	172	[SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
	173	};
bda920c6	174
4849d954 RC	175	static struct pll_init_data ddr3_pll_config_1066[MAX_SYSCLK] = {
	176	[SYSCLK_19MHz] = {DDR3A_PLL, 194, 1, 14},
	177	[SYSCLK_24MHz] = {DDR3A_PLL, 156, 1, 14},
	178	[SYSCLK_25MHz] = {DDR3A_PLL, 149, 1, 14},
	179	[SYSCLK_26MHz] = {DDR3A_PLL, 144, 1, 14},
	180	};
	181
bda920c6 VA	182	struct pll_init_data *get_pll_init_data(int pll)
bda920c6 VA	183	{
ef76ebb1	184	int speed;
bda920c6	185	struct pll_init_data *data = NULL;
c5f177de	186	u8 sysclk_index = get_sysclk_index();
bda920c6 VA	187
	188	switch (pll) {
	189	case MAIN_PLL:
ef76ebb1	190	speed = get_max_dev_speed(dev_speeds);
c5f177de	191	data = &main_pll_config[sysclk_index][speed];
bda920c6 VA	192	break;
bda920c6 VA	193	case TETRIS_PLL:
4849d954	194	speed = get_max_arm_speed(speeds);
c5f177de	195	data = &tetris_pll_config[sysclk_index][speed];
bda920c6 VA	196	break;
bda920c6 VA	197	case NSS_PLL:
c5f177de	198	data = &nss_pll_config[sysclk_index];
bda920c6 VA	199	break;
bda920c6 VA	200	case UART_PLL:
c5f177de	201	data = &uart_pll_config[sysclk_index];
bda920c6 VA	202	break;
bda920c6 VA	203	case DDR3_PLL:
4849d954 RC	204	if (cpu_revision() & CPU_66AK2G1x) {
	205	speed = get_max_arm_speed(speeds);
	206	if (speed == SPD1000)
	207	data = &ddr3_pll_config_1066[sysclk_index];
	208	else
	209	data = &ddr3_pll_config_800[sysclk_index];
	210	} else {
	211	data = &ddr3_pll_config_800[sysclk_index];
	212	}
bda920c6 VA	213	break;
	214	default:
	215	data = NULL;
	216	}
	217
	218	return data;
	219	}
	220
	221	s16 divn_val[16] = {
	222	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
	223	};
	224
4aa2ba3a	225	#if defined(CONFIG_MMC)
b75d8dc5	226	int board_mmc_init(struct bd_info *bis)
3b68939f RQ	227	{
	228	if (psc_enable_module(KS2_LPSC_MMC)) {
	229	printf("%s module enabled failed\n", __func__);
	230	return -1;
	231	}
	232
4849d954	233	if (board_is_k2g_gp() \|\| board_is_k2g_g1())
4f490402 CJF	234	omap_mmc_init(0, 0, 0, -1, -1);
4f490402 CJF	235
3b68939f RQ	236	omap_mmc_init(1, 0, 0, -1, -1);
	237	return 0;
	238	}
	239	#endif
	240
11955590	241	#if defined(CONFIG_MULTI_DTB_FIT)
7234f215 CJF	242	int board_fit_config_name_match(const char *name)
	243	{
	244	bool eeprom_read = board_ti_was_eeprom_read();
	245
	246	if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
	247	return 0;
4849d954 RC	248	else if (!strcmp(name, "keystone-k2g-evm") &&
4849d954 RC	249	(board_ti_is("66AK2GGP") \|\| board_ti_is("66AK2GG1")))
7234f215	250	return 0;
d2aa5727 LV	251	else if (!strcmp(name, "keystone-k2g-ice") &&
d2aa5727 LV	252	(board_ti_is("66AK2GIC") \|\| board_is_k2g_i1()))
bc420967	253	return 0;
7234f215 CJF	254	else
	255	return -1;
	256	}
	257	#endif
	258
5f48da9a CJF	259	#if defined(CONFIG_DTB_RESELECT)
	260	static int k2g_alt_board_detect(void)
	261	{
2147a169	262	#if !CONFIG_IS_ENABLED(DM_I2C)
5f48da9a CJF	263	int rc;
	264
	265	rc = i2c_set_bus_num(1);
	266	if (rc)
	267	return rc;
	268
	269	rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS);
	270	if (rc)
	271	return rc;
1514244c JJH	272	#else
	273	struct udevice bus, dev;
	274	int rc;
5f48da9a	275
1514244c JJH	276	rc = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus);
	277	if (rc)
	278	return rc;
	279	rc = dm_i2c_probe(bus, K2G_GP_AUDIO_CODEC_ADDRESS, 0, &dev);
	280	if (rc)
	281	return rc;
	282	#endif
5f48da9a CJF	283	ti_i2c_eeprom_am_set("66AK2GGP", "1.0X");
	284
	285	return 0;
	286	}
	287
e2924e59 LV	288	static void k2g_reset_mux_config(void)
	289	{
	290	/* Unlock the reset mux register */
	291	clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
	292
	293	/* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
	294	clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
	295	RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
	296
	297	/* lock the reset mux register to prevent any spurious writes. */
	298	setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
	299	}
	300
e820f523	301	int embedded_dtb_select(void)
bda920c6	302	{
e820f523 CJF	303	int rc;
	304	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
	305	CONFIG_EEPROM_CHIP_ADDRESS);
	306	if (rc) {
	307	rc = k2g_alt_board_detect();
	308	if (rc) {
	309	printf("Unable to do board detection\n");
	310	return -1;
	311	}
	312	}
bda920c6	313
e820f523	314	fdtdec_setup();
dd78b8cf	315
b9b342ea CJF	316	k2g_mux_config();
b9b342ea CJF	317
e2924e59 LV	318	k2g_reset_mux_config();
e2924e59 LV	319
4849d954	320	if (board_is_k2g_gp() \|\| board_is_k2g_g1()) {
4f490402 CJF	321	/* deassert FLASH_HOLD */
	322	clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
	323	BIT(9));
	324	setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
	325	BIT(9));
d2aa5727	326	} else if (board_is_k2g_ice() \|\| board_is_k2g_i1()) {
f748ec9d MK	327	/* GBE Phy workaround. For Phy to latch the input
	328	* configuration, a GPIO reset is asserted at the
	329	* Phy reset pin to latch configuration correctly after SoC
	330	* reset. GPIO0 Pin 10 (Ball AA20) is used for this on ICE
	331	* board. Just do a low to high transition.
	332	*/
	333	clrbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_DIR_OFFSET,
	334	BIT(10));
	335	setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_CLRDATA_OFFSET,
	336	BIT(10));
	337	/* Delay just to get a transition to high */
	338	udelay(100);
	339	setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_SETDATA_OFFSET,
	340	BIT(10));
4f490402	341	}
83b9bf11	342
bda920c6 VA	343	return 0;
	344	}
	345	#endif
	346
752a8311 RQ	347	#ifdef CONFIG_BOARD_LATE_INIT
	348	int board_late_init(void)
	349	{
	350	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
	351	int rc;
	352
	353	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
	354	CONFIG_EEPROM_CHIP_ADDRESS);
	355	if (rc)
	356	printf("ti_i2c_eeprom_init failed %d\n", rc);
	357
	358	board_ti_set_ethaddr(1);
	359	#endif
	360
92761fcc CJF	361	#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
92761fcc CJF	362	if (board_is_k2g_gp())
382bee57	363	env_set("board_name", "66AK2GGP\0");
4849d954 RC	364	else if (board_is_k2g_g1())
4849d954 RC	365	env_set("board_name", "66AK2GG1\0");
92761fcc	366	else if (board_is_k2g_ice())
382bee57	367	env_set("board_name", "66AK2GIC\0");
d2aa5727 LV	368	else if (board_is_k2g_i1())
d2aa5727 LV	369	env_set("board_name", "66AK2GI1\0");
92761fcc	370	#endif
752a8311 RQ	371	return 0;
	372	}
	373	#endif
	374
e820f523 CJF	375	#ifdef CONFIG_BOARD_EARLY_INIT_F
	376	int board_early_init_f(void)
	377	{
	378	init_plls();
	379
	380	k2g_mux_config();
	381
	382	return 0;
	383	}
	384	#endif
	385
bda920c6 VA	386	#ifdef CONFIG_SPL_BUILD
	387	void spl_init_keystone_plls(void)
	388	{
	389	init_plls();
	390	}
	391	#endif
91266ccb	392
58fac52d AD	393	#ifdef CONFIG_TI_SECURE_DEVICE
	394	void board_pmmc_image_process(ulong pmmc_image, size_t pmmc_size)
	395	{
952c3462	396	int id = env_get_ulong("dev_pmmc", 10, 0);
58fac52d AD	397	int ret;
	398
	399	if (!rproc_is_initialized())
	400	rproc_init();
	401
	402	ret = rproc_load(id, pmmc_image, pmmc_size);
	403	printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
	404	id, pmmc_image, pmmc_size, ret ? " Failed!" : " Success!");
	405
	406	if (!ret)
	407	rproc_start(id);
	408	}
	409
	410	U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_PMMC, board_pmmc_image_process);
	411	#endif