projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| ef509b90 VA |
2 | /* |
| 3 | * Keystone2: DDR3 initialization | |
| 4 | * | |
| 5 | * (C) Copyright 2012-2014 | |
| 6 | * Texas Instruments Incorporated, <www.ti.com> | |
| ef509b90 VA |
7 | */ |
| 8 | ||
| d678a59d | 9 | #include <common.h> |
| b1babef8 | 10 | #include "ddr3_cfg.h" |
| 0b868589 | 11 | #include <asm/arch/ddr3.h> |
| ef509b90 | 12 | #include <asm/arch/hardware.h> |
| ef509b90 VA |
13 | |
| 14 | struct pll_init_data ddr3a_333 = DDR3_PLL_333(A); | |
| ef509b90 | 15 | struct pll_init_data ddr3a_400 = DDR3_PLL_400(A); |
| ef509b90 | 16 | |
| 66c98a0c | 17 | u32 ddr3_init(void) |
| ef509b90 | 18 | { |
| 66c98a0c | 19 | u32 ddr3_size; |
| d9a76e77 | 20 | struct ddr3_spd_cb spd_cb; |
| ef509b90 | 21 | |
| d9a76e77 VA |
22 | if (ddr3_get_dimm_params_from_spd(&spd_cb)) { |
| 23 | printf("Sorry, I don't know how to configure DDR3A.\n" | |
| 24 | "Bye :(\n"); | |
| 25 | for (;;) | |
| 26 | ; | |
| 27 | } | |
| ef509b90 | 28 | |
| d9a76e77 | 29 | printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name); |
| ef509b90 | 30 | |
| d9a76e77 VA |
31 | if ((cpu_revision() > 1) || |
| 32 | (__raw_readl(KS2_RSTCTRL_RSTYPE) & 0x1)) { | |
| 33 | printf("DDR3 speed %d\n", spd_cb.ddrspdclock); | |
| 34 | if (spd_cb.ddrspdclock == 1600) | |
| 35 | init_pll(&ddr3a_400); | |
| 36 | else | |
| 37 | init_pll(&ddr3a_333); | |
| 38 | } | |
| 101eec50 | 39 | |
| d9a76e77 VA |
40 | if (cpu_revision() > 0) { |
| 41 | if (cpu_revision() > 1) { | |
| 42 | /* PG 2.0 */ | |
| 43 | /* Reset DDR3A PHY after PLL enabled */ | |
| 44 | ddr3_reset_ddrphy(); | |
| 45 | spd_cb.phy_cfg.zq0cr1 |= 0x10000; | |
| 46 | spd_cb.phy_cfg.zq1cr1 |= 0x10000; | |
| 47 | spd_cb.phy_cfg.zq2cr1 |= 0x10000; | |
| ef509b90 | 48 | } |
| d9a76e77 VA |
49 | ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg); |
| 50 | ||
| 51 | ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg); | |
| 52 | ||
| 53 | ddr3_size = spd_cb.ddr_size_gbyte; | |
| ef509b90 | 54 | } else { |
| d9a76e77 VA |
55 | ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg); |
| 56 | spd_cb.emif_cfg.sdcfg |= 0x1000; | |
| 57 | ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg); | |
| 58 | ddr3_size = spd_cb.ddr_size_gbyte / 2; | |
| ef509b90 | 59 | } |
| d9a76e77 | 60 | printf("DRAM: %d GiB (includes reported below)\n", ddr3_size); |
| 6c343825 MK |
61 | |
| 62 | /* Apply the workaround for PG 1.0 and 1.1 Silicons */ | |
| 63 | if (cpu_revision() <= 1) | |
| 64 | ddr3_err_reset_workaround(); | |
| 89f44bb0 | 65 | |
| 89f44bb0 VA |
66 | return ddr3_size; |
| 67 | } |