[people/ms/u-boot.git] / board / ti / omap5_uevm / evm.c

/*
 * (C) Copyright 2010
 * Texas Instruments Incorporated, <www.ti.com>
 * Aneesh V       <aneesh@ti.com>
 * Steve Sakoman  <steve@sakoman.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <palmas.h>
#include <asm/arch/omap.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <tca642x.h>
#include <usb.h>
#include <linux/usb/gadget.h>
#include <dwc3-uboot.h>
#include <dwc3-omap-uboot.h>
#include <ti-usb-phy-uboot.h>

#include "mux_data.h"

#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_XHCI_OMAP)
#include <sata.h>
#include <usb.h>
#include <asm/gpio.h>
#include <asm/mach-types.h>
#include <asm/arch/clock.h>
#include <asm/arch/ehci.h>
#include <asm/ehci-omap.h>
#include <asm/arch/sata.h>

#define DIE_ID_REG_BASE     (OMAP54XX_L4_CORE_BASE + 0x2000)
#define DIE_ID_REG_OFFSET	0x200

#endif

DECLARE_GLOBAL_DATA_PTR;

const struct omap_sysinfo sysinfo = {
	"Board: OMAP5432 uEVM\n"
};

/**
 * @brief tca642x_init - uEVM default values for the GPIO expander
 * input reg, output reg, polarity reg, configuration reg
 */
struct tca642x_bank_info tca642x_init[] = {
	{ .input_reg = 0x00,
	  .output_reg = 0x04,
	  .polarity_reg = 0x00,
	  .configuration_reg = 0x80 },
	{ .input_reg = 0x00,
	  .output_reg = 0x00,
	  .polarity_reg = 0x00,
	  .configuration_reg = 0xff },
	{ .input_reg = 0x00,
	  .output_reg = 0x00,
	  .polarity_reg = 0x00,
	  .configuration_reg = 0x40 },
};

#ifdef CONFIG_USB_DWC3
static struct dwc3_device usb_otg_ss = {
	.maximum_speed = USB_SPEED_SUPER,
	.base = OMAP5XX_USB_OTG_SS_BASE,
	.tx_fifo_resize = false,
	.index = 0,
};

static struct dwc3_omap_device usb_otg_ss_glue = {
	.base = (void *)OMAP5XX_USB_OTG_SS_GLUE_BASE,
	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
	.index = 0,
};

static struct ti_usb_phy_device usb_phy_device = {
	.pll_ctrl_base = (void *)OMAP5XX_USB3_PHY_PLL_CTRL,
	.usb2_phy_power = (void *)OMAP5XX_USB2_PHY_POWER,
	.usb3_phy_power = (void *)OMAP5XX_USB3_PHY_POWER,
	.index = 0,
};

int board_usb_init(int index, enum usb_init_type init)
{
	if (index) {
		printf("Invalid Controller Index\n");
		return -EINVAL;
	}

	if (init == USB_INIT_DEVICE) {
		usb_otg_ss.dr_mode = USB_DR_MODE_PERIPHERAL;
		usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
	} else {
		usb_otg_ss.dr_mode = USB_DR_MODE_HOST;
		usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
	}

	enable_usb_clocks(index);
	ti_usb_phy_uboot_init(&usb_phy_device);
	dwc3_omap_uboot_init(&usb_otg_ss_glue);
	dwc3_uboot_init(&usb_otg_ss);

	return 0;
}

int board_usb_cleanup(int index, enum usb_init_type init)
{
	if (index) {
		printf("Invalid Controller Index\n");
		return -EINVAL;
	}

	ti_usb_phy_uboot_exit(index);
	dwc3_uboot_exit(index);
	dwc3_omap_uboot_exit(index);
	disable_usb_clocks(index);

	return 0;
}

int usb_gadget_handle_interrupts(int index)
{
	u32 status;

	status = dwc3_omap_uboot_interrupt_status(index);
	if (status)
		dwc3_uboot_handle_interrupt(index);

	return 0;
}
#endif

/**
 * @brief board_init
 *
 * @return 0
 */
int board_init(void)
{
	gpmc_init();
	gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */

	tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init);

	return 0;
}

int board_eth_init(bd_t *bis)
{
	return 0;
}

#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_XHCI_OMAP)
static void enable_host_clocks(void)
{
	int auxclk;
	int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK |
				OPTFCLKEN_HSIC480M_P3_CLK |
				OPTFCLKEN_HSIC60M_P2_CLK |
				OPTFCLKEN_HSIC480M_P2_CLK |
				OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK);

	/* Enable port 2 and 3 clocks*/
	setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);

	/* Enable port 2 and 3 usb host ports tll clocks*/
	setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
			(OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE));
#ifdef CONFIG_USB_XHCI_OMAP
	/* Enable the USB OTG Super speed clocks */
	setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
			(OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW));
#endif

	auxclk = readl((*prcm)->scrm_auxclk1);
	/* Request auxilary clock */
	auxclk |= AUXCLK_ENABLE_MASK;
	writel(auxclk, (*prcm)->scrm_auxclk1);
}
#endif

/**
 * @brief misc_init_r - Configure EVM board specific configurations
 * such as power configurations, ethernet initialization as phase2 of
 * boot sequence
 *
 * @return 0
 */
int misc_init_r(void)
{
#ifdef CONFIG_PALMAS_POWER
	palmas_init_settings();
#endif

	omap_die_id_usbethaddr();

	return 0;
}

void set_muxconf_regs(void)
{
	do_set_mux((*ctrl)->control_padconf_core_base,
		   core_padconf_array_essential,
		   sizeof(core_padconf_array_essential) /
		   sizeof(struct pad_conf_entry));

	do_set_mux((*ctrl)->control_padconf_wkup_base,
		   wkup_padconf_array_essential,
		   sizeof(wkup_padconf_array_essential) /
		   sizeof(struct pad_conf_entry));
}

#if defined(CONFIG_MMC)
int board_mmc_init(bd_t *bis)
{
	omap_mmc_init(0, 0, 0, -1, -1);
	omap_mmc_init(1, 0, 0, -1, -1);
	return 0;
}
#endif

#ifdef CONFIG_USB_EHCI_HCD
static struct omap_usbhs_board_data usbhs_bdata = {
	.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
	.port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
	.port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
};

int ehci_hcd_init(int index, enum usb_init_type init,
		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
	int ret;

	enable_host_clocks();

	ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
	if (ret < 0) {
		puts("Failed to initialize ehci\n");
		return ret;
	}

	return 0;
}

int ehci_hcd_stop(void)
{
	return omap_ehci_hcd_stop();
}

void usb_hub_reset_devices(struct usb_hub_device *hub, int port)
{
	/* The LAN9730 needs to be reset after the port power has been set. */
	if (port == 3) {
		gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0);
		udelay(10);
		gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1);
	}
}
#endif

#ifdef CONFIG_USB_XHCI_OMAP
/**
 * @brief board_usb_init - Configure EVM board specific configurations
 * for the LDO's and clocks for the USB blocks.
 *
 * @return 0
 */
int board_usb_init(int index, enum usb_init_type init)
{
	int ret;
#ifdef CONFIG_PALMAS_USB_SS_PWR
	ret = palmas_enable_ss_ldo();
#endif

	enable_host_clocks();

	return 0;
}
#endif
Commit	Line	Data
508a58fa S	1	/*
	2	* (C) Copyright 2010
	3	* Texas Instruments Incorporated, <www.ti.com>
	4	* Aneesh V <aneesh@ti.com>
	5	* Steve Sakoman <steve@sakoman.com>
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
508a58fa S	8	*/
508a58fa S	9	#include <common.h>
cb199102	10	#include <palmas.h>
7ba792c0	11	#include <asm/arch/omap.h>
508a58fa S	12	#include <asm/arch/sys_proto.h>
508a58fa S	13	#include <asm/arch/mmc_host_def.h>
fdce7b63	14	#include <tca642x.h>
7ba792c0 KVA	15	#include <usb.h>
	16	#include <linux/usb/gadget.h>
	17	#include <dwc3-uboot.h>
	18	#include <dwc3-omap-uboot.h>
	19	#include <ti-usb-phy-uboot.h>
508a58fa S	20
	21	#include "mux_data.h"
	22
8850c5d5	23	#if defined(CONFIG_USB_EHCI_HCD) \|\| defined(CONFIG_USB_XHCI_OMAP)
e9024ef2	24	#include <sata.h>
5e5cfaf9	25	#include <usb.h>
1572eadf	26	#include <asm/gpio.h>
c62db35d	27	#include <asm/mach-types.h>
5e5cfaf9 DM	28	#include <asm/arch/clock.h>
	29	#include <asm/arch/ehci.h>
	30	#include <asm/ehci-omap.h>
afdc6321	31	#include <asm/arch/sata.h>
04025b42 DM	32
	33	#define DIE_ID_REG_BASE (OMAP54XX_L4_CORE_BASE + 0x2000)
	34	#define DIE_ID_REG_OFFSET 0x200
	35
5e5cfaf9 DM	36	#endif
5e5cfaf9 DM	37
508a58fa S	38	DECLARE_GLOBAL_DATA_PTR;
	39
	40	const struct omap_sysinfo sysinfo = {
5a7bd384	41	"Board: OMAP5432 uEVM\n"
508a58fa S	42	};
508a58fa S	43
fdce7b63 DM	44	/**
	45	* @brief tca642x_init - uEVM default values for the GPIO expander
	46	* input reg, output reg, polarity reg, configuration reg
	47	*/
	48	struct tca642x_bank_info tca642x_init[] = {
	49	{ .input_reg = 0x00,
	50	.output_reg = 0x04,
	51	.polarity_reg = 0x00,
	52	.configuration_reg = 0x80 },
	53	{ .input_reg = 0x00,
	54	.output_reg = 0x00,
	55	.polarity_reg = 0x00,
	56	.configuration_reg = 0xff },
	57	{ .input_reg = 0x00,
	58	.output_reg = 0x00,
	59	.polarity_reg = 0x00,
	60	.configuration_reg = 0x40 },
	61	};
	62
7ba792c0 KVA	63	#ifdef CONFIG_USB_DWC3
	64	static struct dwc3_device usb_otg_ss = {
	65	.maximum_speed = USB_SPEED_SUPER,
	66	.base = OMAP5XX_USB_OTG_SS_BASE,
	67	.tx_fifo_resize = false,
	68	.index = 0,
	69	};
	70
	71	static struct dwc3_omap_device usb_otg_ss_glue = {
	72	.base = (void *)OMAP5XX_USB_OTG_SS_GLUE_BASE,
	73	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
	74	.index = 0,
	75	};
	76
	77	static struct ti_usb_phy_device usb_phy_device = {
	78	.pll_ctrl_base = (void *)OMAP5XX_USB3_PHY_PLL_CTRL,
	79	.usb2_phy_power = (void *)OMAP5XX_USB2_PHY_POWER,
	80	.usb3_phy_power = (void *)OMAP5XX_USB3_PHY_POWER,
	81	.index = 0,
	82	};
	83
	84	int board_usb_init(int index, enum usb_init_type init)
	85	{
	86	if (index) {
	87	printf("Invalid Controller Index\n");
	88	return -EINVAL;
	89	}
	90
	91	if (init == USB_INIT_DEVICE) {
	92	usb_otg_ss.dr_mode = USB_DR_MODE_PERIPHERAL;
	93	usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
	94	} else {
	95	usb_otg_ss.dr_mode = USB_DR_MODE_HOST;
	96	usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
	97	}
	98
6f1af1e3	99	enable_usb_clocks(index);
7ba792c0 KVA	100	ti_usb_phy_uboot_init(&usb_phy_device);
	101	dwc3_omap_uboot_init(&usb_otg_ss_glue);
	102	dwc3_uboot_init(&usb_otg_ss);
	103
	104	return 0;
	105	}
	106
	107	int board_usb_cleanup(int index, enum usb_init_type init)
	108	{
	109	if (index) {
	110	printf("Invalid Controller Index\n");
	111	return -EINVAL;
	112	}
	113
	114	ti_usb_phy_uboot_exit(index);
	115	dwc3_uboot_exit(index);
	116	dwc3_omap_uboot_exit(index);
6f1af1e3	117	disable_usb_clocks(index);
7ba792c0 KVA	118
	119	return 0;
	120	}
	121
	122	int usb_gadget_handle_interrupts(int index)
	123	{
	124	u32 status;
	125
	126	status = dwc3_omap_uboot_interrupt_status(index);
	127	if (status)
	128	dwc3_uboot_handle_interrupt(index);
	129
	130	return 0;
	131	}
	132	#endif
	133
508a58fa S	134	/**
	135	* @brief board_init
	136	*
	137	* @return 0
	138	*/
	139	int board_init(void)
	140	{
	141	gpmc_init();
94ba26f2	142	gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
508a58fa S	143	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
508a58fa S	144
fdce7b63 DM	145	tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init);
fdce7b63 DM	146
508a58fa S	147	return 0;
	148	}
	149
	150	int board_eth_init(bd_t *bis)
	151	{
	152	return 0;
	153	}
	154
8850c5d5	155	#if defined(CONFIG_USB_EHCI_HCD) \|\| defined(CONFIG_USB_XHCI_OMAP)
96805532 DM	156	static void enable_host_clocks(void)
	157	{
	158	int auxclk;
	159	int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK \|
	160	OPTFCLKEN_HSIC480M_P3_CLK \|
	161	OPTFCLKEN_HSIC60M_P2_CLK \|
	162	OPTFCLKEN_HSIC480M_P2_CLK \|
	163	OPTFCLKEN_UTMI_P3_CLK \| OPTFCLKEN_UTMI_P2_CLK);
	164
	165	/* Enable port 2 and 3 clocks*/
	166	setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
	167
	168	/* Enable port 2 and 3 usb host ports tll clocks*/
	169	setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
	170	(OPTFCLKEN_USB_CH1_CLK_ENABLE \| OPTFCLKEN_USB_CH2_CLK_ENABLE));
	171	#ifdef CONFIG_USB_XHCI_OMAP
	172	/* Enable the USB OTG Super speed clocks */
	173	setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
	174	(OPTFCLKEN_REFCLK960M \| OTG_SS_CLKCTRL_MODULEMODE_HW));
	175	#endif
	176
	177	auxclk = readl((*prcm)->scrm_auxclk1);
	178	/* Request auxilary clock */
	179	auxclk \|= AUXCLK_ENABLE_MASK;
	180	writel(auxclk, (*prcm)->scrm_auxclk1);
	181	}
	182	#endif
	183
508a58fa S	184	/**
	185	* @brief misc_init_r - Configure EVM board specific configurations
	186	* such as power configurations, ethernet initialization as phase2 of
	187	* boot sequence
	188	*
	189	* @return 0
	190	*/
	191	int misc_init_r(void)
	192	{
cb199102	193	#ifdef CONFIG_PALMAS_POWER
12733881	194	palmas_init_settings();
508a58fa	195	#endif
96805532	196
07815eb9	197	omap_die_id_usbethaddr();
ea02b653	198
508a58fa S	199	return 0;
	200	}
	201
3ef56e61	202	void set_muxconf_regs(void)
508a58fa	203	{
9239f5b6 LV	204	do_set_mux((*ctrl)->control_padconf_core_base,
9239f5b6 LV	205	core_padconf_array_essential,
508a58fa S	206	sizeof(core_padconf_array_essential) /
	207	sizeof(struct pad_conf_entry));
	208
9239f5b6 LV	209	do_set_mux((*ctrl)->control_padconf_wkup_base,
9239f5b6 LV	210	wkup_padconf_array_essential,
508a58fa S	211	sizeof(wkup_padconf_array_essential) /
	212	sizeof(struct pad_conf_entry));
	213	}
	214
4aa2ba3a	215	#if defined(CONFIG_MMC)
508a58fa S	216	int board_mmc_init(bd_t *bis)
508a58fa S	217	{
e3913f56 NK	218	omap_mmc_init(0, 0, 0, -1, -1);
e3913f56 NK	219	omap_mmc_init(1, 0, 0, -1, -1);
508a58fa S	220	return 0;
	221	}
	222	#endif
5e5cfaf9	223
8850c5d5	224	#ifdef CONFIG_USB_EHCI_HCD
5e5cfaf9 DM	225	static struct omap_usbhs_board_data usbhs_bdata = {
	226	.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
	227	.port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
	228	.port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
	229	};
	230
127efc4f TK	231	int ehci_hcd_init(int index, enum usb_init_type init,
127efc4f TK	232	struct ehci_hccr hccr, struct ehci_hcor hcor)
5e5cfaf9 DM	233	{
5e5cfaf9 DM	234	int ret;
5e5cfaf9 DM	235
	236	enable_host_clocks();
	237
16297cfb	238	ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
5e5cfaf9 DM	239	if (ret < 0) {
	240	puts("Failed to initialize ehci\n");
	241	return ret;
	242	}
	243
	244	return 0;
	245	}
	246
	247	int ehci_hcd_stop(void)
	248	{
63a7578e	249	return omap_ehci_hcd_stop();
5e5cfaf9	250	}
1572eadf	251
883946e8	252	void usb_hub_reset_devices(struct usb_hub_device *hub, int port)
1572eadf DM	253	{
	254	/* The LAN9730 needs to be reset after the port power has been set. */
	255	if (port == 3) {
	256	gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0);
	257	udelay(10);
	258	gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1);
	259	}
	260	}
5e5cfaf9	261	#endif
96805532 DM	262
	263	#ifdef CONFIG_USB_XHCI_OMAP
	264	/**
	265	* @brief board_usb_init - Configure EVM board specific configurations
	266	* for the LDO's and clocks for the USB blocks.
	267	*
	268	* @return 0
	269	*/
7e575c46	270	int board_usb_init(int index, enum usb_init_type init)
96805532 DM	271	{
	272	int ret;
	273	#ifdef CONFIG_PALMAS_USB_SS_PWR
	274	ret = palmas_enable_ss_ldo();
	275	#endif
	276
	277	enable_host_clocks();
	278
	279	return 0;
	280	}
	281	#endif