[people/ms/u-boot.git] / board / ti / panda / panda.c

/*
 * (C) Copyright 2010
 * Texas Instruments Incorporated, <www.ti.com>
 * Steve Sakoman  <steve@sakoman.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/gpio.h>

#include "panda_mux_data.h"

#ifdef CONFIG_USB_EHCI
#include <usb.h>
#include <asm/arch/ehci.h>
#include <asm/ehci-omap.h>
#endif

#define PANDA_ULPI_PHY_TYPE_GPIO       182
#define PANDA_BOARD_ID_1_GPIO          101
#define PANDA_ES_BOARD_ID_1_GPIO        48
#define PANDA_BOARD_ID_2_GPIO          171
#define PANDA_ES_BOARD_ID_3_GPIO         3
#define PANDA_ES_BOARD_ID_4_GPIO         2

DECLARE_GLOBAL_DATA_PTR;

const struct omap_sysinfo sysinfo = {
	"Board: OMAP4 Panda\n"
};

struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000;

/**
 * @brief board_init
 *
 * @return 0
 */
int board_init(void)
{
	gpmc_init();

	gd->bd->bi_arch_number = MACH_TYPE_OMAP4_PANDA;
	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */

	return 0;
}

int board_eth_init(bd_t *bis)
{
	return 0;
}

/*
* Routine: get_board_revision
* Description: Detect if we are running on a panda revision A1-A6,
*              or an ES panda board. This can be done by reading
*              the level of GPIOs and checking the processor revisions.
*              This should result in:
*			Panda 4430:
*              GPIO171, GPIO101, GPIO182: 0 1 1 => A1-A5
*              GPIO171, GPIO101, GPIO182: 1 0 1 => A6
*			Panda ES:
*              GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 0 1 1 => B1/B2
*              GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 1 1 1 => B3
*/
int get_board_revision(void)
{
	int board_id0, board_id1, board_id2;
	int board_id3, board_id4;
	int board_id;

	int processor_rev = omap_revision();

	/* Setup the mux for the common board ID pins (gpio 171 and 182) */
	writew((IEN | M3), (*ctrl)->control_padconf_core_base + UNIPRO_TX0);
	writew((IEN | M3), (*ctrl)->control_padconf_core_base + FREF_CLK2_OUT);

	board_id0 = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
	board_id2 = gpio_get_value(PANDA_BOARD_ID_2_GPIO);

	if ((processor_rev >= OMAP4460_ES1_0 &&
	     processor_rev <= OMAP4460_ES1_1)) {
		/*
		 * Setup the mux for the ES specific board ID pins (gpio 101,
		 * 2 and 3.
		 */
		writew((IEN | M3), (*ctrl)->control_padconf_core_base +
				GPMC_A24);
		writew((IEN | M3), (*ctrl)->control_padconf_core_base +
				UNIPRO_RY0);
		writew((IEN | M3), (*ctrl)->control_padconf_core_base +
				UNIPRO_RX1);

		board_id1 = gpio_get_value(PANDA_ES_BOARD_ID_1_GPIO);
		board_id3 = gpio_get_value(PANDA_ES_BOARD_ID_3_GPIO);
		board_id4 = gpio_get_value(PANDA_ES_BOARD_ID_4_GPIO);

#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
		setenv("board_name", strcat(CONFIG_SYS_BOARD, "-es"));
#endif
		board_id = ((board_id4 << 4) | (board_id3 << 3) |
			(board_id2 << 2) | (board_id1 << 1) | (board_id0));
	} else {
		/* Setup the mux for the Ax specific board ID pins (gpio 101) */
		writew((IEN | M3), (*ctrl)->control_padconf_core_base +
				FREF_CLK2_OUT);

		board_id1 = gpio_get_value(PANDA_BOARD_ID_1_GPIO);
		board_id = ((board_id2 << 2) | (board_id1 << 1) | (board_id0));

#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
		if ((board_id >= 0x3) && (processor_rev == OMAP4430_ES2_3))
			setenv("board_name", strcat(CONFIG_SYS_BOARD, "-a4"));
#endif
	}

	return board_id;
}

/**
 * @brief misc_init_r - Configure Panda board specific configurations
 * such as power configurations, ethernet initialization as phase2 of
 * boot sequence
 *
 * @return 0
 */
int misc_init_r(void)
{
	int phy_type;
	u32 auxclk, altclksrc;

	/* EHCI is not supported on ES1.0 */
	if (omap_revision() == OMAP4430_ES1_0)
		return 0;

	get_board_revision();

	gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO);
	phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);

	if (phy_type == 1) {
		/* ULPI PHY supplied by auxclk3 derived from sys_clk */
		debug("ULPI PHY supplied by auxclk3\n");

		auxclk = readl(&scrm->auxclk3);
		/* Select sys_clk */
		auxclk &= ~AUXCLK_SRCSELECT_MASK;
		auxclk |=  AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
		/* Set the divisor to 2 */
		auxclk &= ~AUXCLK_CLKDIV_MASK;
		auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
		/* Request auxilary clock #3 */
		auxclk |= AUXCLK_ENABLE_MASK;

		writel(auxclk, &scrm->auxclk3);
	} else {
		/* ULPI PHY supplied by auxclk1 derived from PER dpll */
		debug("ULPI PHY supplied by auxclk1\n");

		auxclk = readl(&scrm->auxclk1);
		/* Select per DPLL */
		auxclk &= ~AUXCLK_SRCSELECT_MASK;
		auxclk |=  AUXCLK_SRCSELECT_PER_DPLL << AUXCLK_SRCSELECT_SHIFT;
		/* Set the divisor to 16 */
		auxclk &= ~AUXCLK_CLKDIV_MASK;
		auxclk |= AUXCLK_CLKDIV_16 << AUXCLK_CLKDIV_SHIFT;
		/* Request auxilary clock #3 */
		auxclk |= AUXCLK_ENABLE_MASK;

		writel(auxclk, &scrm->auxclk1);
	}

	altclksrc = readl(&scrm->altclksrc);

	/* Activate alternate system clock supplier */
	altclksrc &= ~ALTCLKSRC_MODE_MASK;
	altclksrc |= ALTCLKSRC_MODE_ACTIVE;

	/* enable clocks */
	altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK;

	writel(altclksrc, &scrm->altclksrc);

	return 0;
}

void set_muxconf_regs_essential(void)
{
	do_set_mux((*ctrl)->control_padconf_core_base,
		   core_padconf_array_essential,
		   sizeof(core_padconf_array_essential) /
		   sizeof(struct pad_conf_entry));

	do_set_mux((*ctrl)->control_padconf_wkup_base,
		   wkup_padconf_array_essential,
		   sizeof(wkup_padconf_array_essential) /
		   sizeof(struct pad_conf_entry));

	if (omap_revision() >= OMAP4460_ES1_0)
		do_set_mux((*ctrl)->control_padconf_wkup_base,
			   wkup_padconf_array_essential_4460,
			   sizeof(wkup_padconf_array_essential_4460) /
			   sizeof(struct pad_conf_entry));
}

void set_muxconf_regs_non_essential(void)
{
	do_set_mux((*ctrl)->control_padconf_core_base,
		   core_padconf_array_non_essential,
		   sizeof(core_padconf_array_non_essential) /
		   sizeof(struct pad_conf_entry));

	if (omap_revision() < OMAP4460_ES1_0)
		do_set_mux((*ctrl)->control_padconf_core_base,
			   core_padconf_array_non_essential_4430,
			   sizeof(core_padconf_array_non_essential_4430) /
			   sizeof(struct pad_conf_entry));
	else
		do_set_mux((*ctrl)->control_padconf_core_base,
			   core_padconf_array_non_essential_4460,
			   sizeof(core_padconf_array_non_essential_4460) /
			   sizeof(struct pad_conf_entry));

	do_set_mux((*ctrl)->control_padconf_wkup_base,
		   wkup_padconf_array_non_essential,
		   sizeof(wkup_padconf_array_non_essential) /
		   sizeof(struct pad_conf_entry));

	if (omap_revision() < OMAP4460_ES1_0)
		do_set_mux((*ctrl)->control_padconf_wkup_base,
			   wkup_padconf_array_non_essential_4430,
			   sizeof(wkup_padconf_array_non_essential_4430) /
			   sizeof(struct pad_conf_entry));
}

#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
int board_mmc_init(bd_t *bis)
{
	return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif

#ifdef CONFIG_USB_EHCI

static struct omap_usbhs_board_data usbhs_bdata = {
	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
	.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};

int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
	int ret;
	unsigned int utmi_clk;

	/* Now we can enable our port clocks */
	utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
	utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
	sr32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, utmi_clk);

	ret = omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
	if (ret < 0)
		return ret;

	return 0;
}

int ehci_hcd_stop(int index)
{
	return omap_ehci_hcd_stop();
}
#endif

/*
 * get_board_rev() - get board revision
 */
u32 get_board_rev(void)
{
	return 0x20;
}
Commit	Line	Data
c57cca25 SS	1	/*
	2	* (C) Copyright 2010
	3	* Texas Instruments Incorporated, <www.ti.com>
	4	* Steve Sakoman <steve@sakoman.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
c57cca25 SS	7	*/
	8	#include <common.h>
	9	#include <asm/arch/sys_proto.h>
7e982c95	10	#include <asm/arch/mmc_host_def.h>
af1d002f	11	#include <asm/arch/clock.h>
df65a3fe	12	#include <asm/arch/gpio.h>
43b62393	13	#include <asm/gpio.h>
c57cca25	14
469ec1e3	15	#include "panda_mux_data.h"
2ad853c3	16
43b62393 G	17	#ifdef CONFIG_USB_EHCI
	18	#include <usb.h>
	19	#include <asm/arch/ehci.h>
	20	#include <asm/ehci-omap.h>
	21	#endif
	22
df65a3fe	23	#define PANDA_ULPI_PHY_TYPE_GPIO 182
7d47d1ca DM	24	#define PANDA_BOARD_ID_1_GPIO 101
	25	#define PANDA_ES_BOARD_ID_1_GPIO 48
	26	#define PANDA_BOARD_ID_2_GPIO 171
	27	#define PANDA_ES_BOARD_ID_3_GPIO 3
	28	#define PANDA_ES_BOARD_ID_4_GPIO 2
df65a3fe	29
c57cca25 SS	30	DECLARE_GLOBAL_DATA_PTR;
	31
	32	const struct omap_sysinfo sysinfo = {
	33	"Board: OMAP4 Panda\n"
	34	};
	35
df65a3fe CL	36	struct omap4_scrm_regs const scrm = (struct omap4_scrm_regs )0x4a30a000;
df65a3fe CL	37
c57cca25 SS	38	/**
	39	* @brief board_init
	40	*
	41	* @return 0
	42	*/
	43	int board_init(void)
	44	{
27952014 SS	45	gpmc_init();
27952014 SS	46
c57cca25 SS	47	gd->bd->bi_arch_number = MACH_TYPE_OMAP4_PANDA;
	48	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
	49
	50	return 0;
	51	}
	52
	53	int board_eth_init(bd_t *bis)
	54	{
	55	return 0;
	56	}
	57
7d47d1ca DM	58	/*
	59	* Routine: get_board_revision
	60	* Description: Detect if we are running on a panda revision A1-A6,
	61	* or an ES panda board. This can be done by reading
	62	* the level of GPIOs and checking the processor revisions.
	63	* This should result in:
	64	* Panda 4430:
	65	* GPIO171, GPIO101, GPIO182: 0 1 1 => A1-A5
	66	* GPIO171, GPIO101, GPIO182: 1 0 1 => A6
	67	* Panda ES:
	68	* GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 0 1 1 => B1/B2
	69	* GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 1 1 1 => B3
	70	*/
	71	int get_board_revision(void)
	72	{
	73	int board_id0, board_id1, board_id2;
	74	int board_id3, board_id4;
	75	int board_id;
	76
	77	int processor_rev = omap_revision();
	78
	79	/* Setup the mux for the common board ID pins (gpio 171 and 182) */
	80	writew((IEN \| M3), (*ctrl)->control_padconf_core_base + UNIPRO_TX0);
	81	writew((IEN \| M3), (*ctrl)->control_padconf_core_base + FREF_CLK2_OUT);
	82
	83	board_id0 = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
	84	board_id2 = gpio_get_value(PANDA_BOARD_ID_2_GPIO);
	85
	86	if ((processor_rev >= OMAP4460_ES1_0 &&
	87	processor_rev <= OMAP4460_ES1_1)) {
	88	/*
	89	* Setup the mux for the ES specific board ID pins (gpio 101,
	90	* 2 and 3.
	91	*/
	92	writew((IEN \| M3), (*ctrl)->control_padconf_core_base +
	93	GPMC_A24);
	94	writew((IEN \| M3), (*ctrl)->control_padconf_core_base +
	95	UNIPRO_RY0);
	96	writew((IEN \| M3), (*ctrl)->control_padconf_core_base +
	97	UNIPRO_RX1);
	98
	99	board_id1 = gpio_get_value(PANDA_ES_BOARD_ID_1_GPIO);
	100	board_id3 = gpio_get_value(PANDA_ES_BOARD_ID_3_GPIO);
	101	board_id4 = gpio_get_value(PANDA_ES_BOARD_ID_4_GPIO);
	102
	103	#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	104	setenv("board_name", strcat(CONFIG_SYS_BOARD, "-es"));
	105	#endif
	106	board_id = ((board_id4 << 4) \| (board_id3 << 3) \|
	107	(board_id2 << 2) \| (board_id1 << 1) \| (board_id0));
	108	} else {
	109	/* Setup the mux for the Ax specific board ID pins (gpio 101) */
	110	writew((IEN \| M3), (*ctrl)->control_padconf_core_base +
	111	FREF_CLK2_OUT);
	112
	113	board_id1 = gpio_get_value(PANDA_BOARD_ID_1_GPIO);
	114	board_id = ((board_id2 << 2) \| (board_id1 << 1) \| (board_id0));
	115
	116	#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	117	if ((board_id >= 0x3) && (processor_rev == OMAP4430_ES2_3))
	118	setenv("board_name", strcat(CONFIG_SYS_BOARD, "-a4"));
	119	#endif
	120	}
	121
122	return board_id;
123	}
124
c57cca25 SS	125	/**
	126	* @brief misc_init_r - Configure Panda board specific configurations
	127	* such as power configurations, ethernet initialization as phase2 of
	128	* boot sequence
	129	*
	130	* @return 0
	131	*/
	132	int misc_init_r(void)
	133	{
df65a3fe CL	134	int phy_type;
	135	u32 auxclk, altclksrc;
	136
	137	/* EHCI is not supported on ES1.0 */
	138	if (omap_revision() == OMAP4430_ES1_0)
	139	return 0;
	140
7d47d1ca	141	get_board_revision();
34f667bb	142
df65a3fe CL	143	gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO);
	144	phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
	145
	146	if (phy_type == 1) {
	147	/* ULPI PHY supplied by auxclk3 derived from sys_clk */
	148	debug("ULPI PHY supplied by auxclk3\n");
	149
	150	auxclk = readl(&scrm->auxclk3);
	151	/* Select sys_clk */
	152	auxclk &= ~AUXCLK_SRCSELECT_MASK;
	153	auxclk \|= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
	154	/* Set the divisor to 2 */
	155	auxclk &= ~AUXCLK_CLKDIV_MASK;
	156	auxclk \|= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
	157	/* Request auxilary clock #3 */
	158	auxclk \|= AUXCLK_ENABLE_MASK;
	159
	160	writel(auxclk, &scrm->auxclk3);
bf3b98a1	161	} else {
df65a3fe CL	162	/* ULPI PHY supplied by auxclk1 derived from PER dpll */
	163	debug("ULPI PHY supplied by auxclk1\n");
	164
	165	auxclk = readl(&scrm->auxclk1);
	166	/* Select per DPLL */
	167	auxclk &= ~AUXCLK_SRCSELECT_MASK;
	168	auxclk \|= AUXCLK_SRCSELECT_PER_DPLL << AUXCLK_SRCSELECT_SHIFT;
	169	/* Set the divisor to 16 */
	170	auxclk &= ~AUXCLK_CLKDIV_MASK;
	171	auxclk \|= AUXCLK_CLKDIV_16 << AUXCLK_CLKDIV_SHIFT;
	172	/* Request auxilary clock #3 */
	173	auxclk \|= AUXCLK_ENABLE_MASK;
	174
	175	writel(auxclk, &scrm->auxclk1);
	176	}
	177
	178	altclksrc = readl(&scrm->altclksrc);
	179
	180	/* Activate alternate system clock supplier */
	181	altclksrc &= ~ALTCLKSRC_MODE_MASK;
	182	altclksrc \|= ALTCLKSRC_MODE_ACTIVE;
	183
	184	/* enable clocks */
	185	altclksrc \|= ALTCLKSRC_ENABLE_INT_MASK \| ALTCLKSRC_ENABLE_EXT_MASK;
	186
	187	writel(altclksrc, &scrm->altclksrc);
	188
c57cca25 SS	189	return 0;
c57cca25 SS	190	}
2ad853c3	191
508a58fa S	192	void set_muxconf_regs_essential(void)
508a58fa S	193	{
9239f5b6 LV	194	do_set_mux((*ctrl)->control_padconf_core_base,
9239f5b6 LV	195	core_padconf_array_essential,
508a58fa S	196	sizeof(core_padconf_array_essential) /
	197	sizeof(struct pad_conf_entry));
	198
9239f5b6 LV	199	do_set_mux((*ctrl)->control_padconf_wkup_base,
9239f5b6 LV	200	wkup_padconf_array_essential,
508a58fa S	201	sizeof(wkup_padconf_array_essential) /
	202	sizeof(struct pad_conf_entry));
	203
	204	if (omap_revision() >= OMAP4460_ES1_0)
9239f5b6	205	do_set_mux((*ctrl)->control_padconf_wkup_base,
bf3b98a1 DM	206	wkup_padconf_array_essential_4460,
	207	sizeof(wkup_padconf_array_essential_4460) /
	208	sizeof(struct pad_conf_entry));
508a58fa S	209	}
508a58fa S	210
469ec1e3	211	void set_muxconf_regs_non_essential(void)
2ad853c3	212	{
9239f5b6 LV	213	do_set_mux((*ctrl)->control_padconf_core_base,
9239f5b6 LV	214	core_padconf_array_non_essential,
469ec1e3	215	sizeof(core_padconf_array_non_essential) /
2ad853c3 SS	216	sizeof(struct pad_conf_entry));
2ad853c3 SS	217
53430a4f	218	if (omap_revision() < OMAP4460_ES1_0)
9239f5b6	219	do_set_mux((*ctrl)->control_padconf_core_base,
bf3b98a1 DM	220	core_padconf_array_non_essential_4430,
	221	sizeof(core_padconf_array_non_essential_4430) /
	222	sizeof(struct pad_conf_entry));
53430a4f	223	else
9239f5b6	224	do_set_mux((*ctrl)->control_padconf_core_base,
bf3b98a1 DM	225	core_padconf_array_non_essential_4460,
	226	sizeof(core_padconf_array_non_essential_4460) /
	227	sizeof(struct pad_conf_entry));
53430a4f	228
9239f5b6 LV	229	do_set_mux((*ctrl)->control_padconf_wkup_base,
9239f5b6 LV	230	wkup_padconf_array_non_essential,
469ec1e3	231	sizeof(wkup_padconf_array_non_essential) /
2ad853c3	232	sizeof(struct pad_conf_entry));
53430a4f RSA	233
53430a4f RSA	234	if (omap_revision() < OMAP4460_ES1_0)
9239f5b6	235	do_set_mux((*ctrl)->control_padconf_wkup_base,
bf3b98a1 DM	236	wkup_padconf_array_non_essential_4430,
	237	sizeof(wkup_padconf_array_non_essential_4430) /
	238	sizeof(struct pad_conf_entry));
2ad853c3	239	}
7e982c95	240
508a58fa	241	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
7e982c95 SG	242	int board_mmc_init(bd_t *bis)
7e982c95 SG	243	{
e3913f56	244	return omap_mmc_init(0, 0, 0, -1, -1);
7e982c95 SG	245	}
7e982c95 SG	246	#endif
508a58fa	247
43b62393 G	248	#ifdef CONFIG_USB_EHCI
	249
	250	static struct omap_usbhs_board_data usbhs_bdata = {
	251	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
	252	.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
	253	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
	254	};
	255
676ae068	256	int ehci_hcd_init(int index, struct ehci_hccr hccr, struct ehci_hcor hcor)
43b62393 G	257	{
	258	int ret;
	259	unsigned int utmi_clk;
	260
	261	/* Now we can enable our port clocks */
	262	utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
	263	utmi_clk \|= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
	264	sr32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, utmi_clk);
	265
676ae068	266	ret = omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
43b62393 G	267	if (ret < 0)
	268	return ret;
	269
	270	return 0;
	271	}
	272
676ae068	273	int ehci_hcd_stop(int index)
43b62393 G	274	{
	275	return omap_ehci_hcd_stop();
	276	}
	277	#endif
	278
508a58fa S	279	/*
	280	* get_board_rev() - get board revision
	281	*/
	282	u32 get_board_rev(void)
	283	{
	284	return 0x20;
	285	}