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Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""
[thirdparty/u-boot.git] / board / toradex / apalis_imx6 / apalis_imx6.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
592f4aed
MK		 2/*
3 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
4 * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
5177087f 5 * Copyright (C) 2014-2019, Toradex AG
592f4aed 6 * copied from nitrogen6x
592f4aed
MK		 7 */
8
d678a59d 9#include <common.h>
9a3b4ceb 10#include <cpu_func.h>
9d922450 11#include <dm.h>
4d72caa5 12#include <image.h>
5255932f 13#include <init.h>
90526e9f 14#include <net.h>
401d1c4f 15#include <asm/global_data.h>
cd93d625 16#include <linux/bitops.h>
c05ed00a 17#include <linux/delay.h>
5177087f 18
72b49e2c 19#include <ahci.h>
592f4aed
MK		 20#include <asm/arch/clock.h>
21#include <asm/arch/crm_regs.h>
592f4aed 22#include <asm/arch/imx-regs.h>
592f4aed 23#include <asm/arch/mx6-ddr.h>
5177087f
MZ		 24#include <asm/arch/mx6-pins.h>
25#include <asm/arch/mxc_hdmi.h>
26#include <asm/arch/sys_proto.h>
592f4aed
MK		 27#include <asm/bootm.h>
28#include <asm/gpio.h>
5177087f 29#include <asm/mach-imx/boot_mode.h>
552a848e 30#include <asm/mach-imx/iomux-v3.h>
552a848e 31#include <asm/mach-imx/sata.h>
552a848e 32#include <asm/mach-imx/video.h>
506df9dc 33#include <asm/sections.h>
72b49e2c 34#include <dm/device-internal.h>
592f4aed 35#include <dm/platform_data/serial_mxc.h>
72b49e2c 36#include <dwc_ahsata.h>
9fb625ce 37#include <env.h>
e37ac717 38#include <fsl_esdhc_imx.h>
592f4aed 39#include <imx_thermal.h>
592f4aed
MK		 40#include <micrel.h>
41#include <miiphy.h>
42#include <netdev.h>
43
44#include "../common/tdx-cfg-block.h"
45#ifdef CONFIG_TDX_CMD_IMX_MFGR
46#include "pf0100.h"
47#endif
48
49DECLARE_GLOBAL_DATA_PTR;
50
51#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
52 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
53 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
54
55#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
3ef55a74
MK		 56 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
57 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
58
59#define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
592f4aed
MK		 60 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
61 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
62
63#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
64 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
65
592f4aed
MK		 66#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
67 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
68 PAD_CTL_SRE_SLOW)
69
592f4aed
MK		 70#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
71 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
72 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
73
74#define TRISTATE (PAD_CTL_HYS | PAD_CTL_SPEED_MED)
75
592f4aed
MK		 76#define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
77
72b49e2c
MZ		 78#define APALIS_IMX6_SATA_INIT_RETRIES 10
79
592f4aed
MK		 80int dram_init(void)
81{
82 /* use the DDR controllers configured size */
aa6e94de 83 gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
592f4aed
MK		 84 (ulong)imx_ddr_size());
85
86 return 0;
87}
88
89/* Apalis UART1 */
90iomux_v3_cfg_t const uart1_pads_dce[] = {
91 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
92 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
93};
94iomux_v3_cfg_t const uart1_pads_dte[] = {
95 MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
96 MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
97};
98
536c564b 99#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
592f4aed
MK		 100/* Apalis MMC1 */
101iomux_v3_cfg_t const usdhc1_pads[] = {
102 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
103 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
104 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
108 MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
109 MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
110 MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
111 MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
112 MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
113# define GPIO_MMC_CD IMX_GPIO_NR(4, 20)
114};
115
116/* Apalis SD1 */
117iomux_v3_cfg_t const usdhc2_pads[] = {
118 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
120 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
121 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
122 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
123 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
124 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
125# define GPIO_SD_CD IMX_GPIO_NR(6, 14)
126};
127
128/* eMMC */
129iomux_v3_cfg_t const usdhc3_pads[] = {
3ef55a74
MK		 130 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
131 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
132 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
133 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
134 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
135 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
136 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
137 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
138 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
139 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
5177087f 140 MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
592f4aed 141};
e37ac717 142#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
592f4aed
MK		 143
144int mx6_rgmii_rework(struct phy_device *phydev)
145{
f72e48ba
PS		 146 int tmp;
147
148 switch (ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) {
149 case PHY_ID_KSZ9131:
150 /* read rxc dll control - devaddr = 0x02, register = 0x4c */
151 tmp = ksz9031_phy_extended_read(phydev, 0x02,
152 MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
153 MII_KSZ9031_MOD_DATA_NO_POST_INC);
154 /* disable rxdll bypass (enable 2ns skew delay on RXC) */
155 tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
156 /* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */
157 ksz9031_phy_extended_write(phydev, 0x02,
158 MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
159 MII_KSZ9031_MOD_DATA_NO_POST_INC,
160 tmp);
161 /* read txc dll control - devaddr = 0x02, register = 0x4d */
162 tmp = ksz9031_phy_extended_read(phydev, 0x02,
163 MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
164 MII_KSZ9031_MOD_DATA_NO_POST_INC);
165 /* disable rxdll bypass (enable 2ns skew delay on TXC) */
166 tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
167 /* txc data pad skew 2ns - devaddr = 0x02, register = 0x4d */
168 ksz9031_phy_extended_write(phydev, 0x02,
169 MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
170 MII_KSZ9031_MOD_DATA_NO_POST_INC,
171 tmp);
172
173 /* control data pad skew - devaddr = 0x02, register = 0x04 */
174 ksz9031_phy_extended_write(phydev, 0x02,
175 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
176 MII_KSZ9031_MOD_DATA_NO_POST_INC,
177 0x007d);
178 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
179 ksz9031_phy_extended_write(phydev, 0x02,
180 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
181 MII_KSZ9031_MOD_DATA_NO_POST_INC,
182 0x7777);
183 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
184 ksz9031_phy_extended_write(phydev, 0x02,
185 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
186 MII_KSZ9031_MOD_DATA_NO_POST_INC,
187 0xdddd);
188 /* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
189 ksz9031_phy_extended_write(phydev, 0x02,
190 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
191 MII_KSZ9031_MOD_DATA_NO_POST_INC,
192 0x0007);
193 break;
194 case PHY_ID_KSZ9031:
195 default:
196 /* control data pad skew - devaddr = 0x02, register = 0x04 */
197 ksz9031_phy_extended_write(phydev, 0x02,
198 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
199 MII_KSZ9031_MOD_DATA_NO_POST_INC,
200 0x0000);
201 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
202 ksz9031_phy_extended_write(phydev, 0x02,
203 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
204 MII_KSZ9031_MOD_DATA_NO_POST_INC,
205 0x0000);
206 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
207 ksz9031_phy_extended_write(phydev, 0x02,
208 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
209 MII_KSZ9031_MOD_DATA_NO_POST_INC,
210 0x0000);
211 /* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
212 ksz9031_phy_extended_write(phydev, 0x02,
213 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
214 MII_KSZ9031_MOD_DATA_NO_POST_INC,
215 0x03FF);
216 break;
217 }
218
592f4aed
MK		 219 return 0;
220}
221
222iomux_v3_cfg_t const enet_pads[] = {
223 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
224 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
225 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
226 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
227 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
228 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
229 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
230 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
231 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
232 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
233 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
234 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
235 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
236 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
237 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
238 /* KSZ9031 PHY Reset */
5177087f
MZ		 239 MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL) |
240 MUX_MODE_SION,
592f4aed
MK		 241# define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
242};
243
592f4aed
MK		 244/* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
245iomux_v3_cfg_t const gpio_pads[] = {
246 /* Apalis GPIO1 - GPIO8 */
5177087f
MZ		 247 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
248 MUX_MODE_SION,
249 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
250 MUX_MODE_SION,
251 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
252 MUX_MODE_SION,
253 MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
254 MUX_MODE_SION,
255 MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
256 MUX_MODE_SION,
257 MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP) |
258 MUX_MODE_SION,
259 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
260 MUX_MODE_SION,
261 MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
262 MUX_MODE_SION,
263 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
264 MUX_MODE_SION,
592f4aed
MK		 265};
266
267static void setup_iomux_gpio(void)
268{
269 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
270}
271
272iomux_v3_cfg_t const usb_pads[] = {
273 /* USBH_EN */
5177087f 274 MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
592f4aed
MK		 275# define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
276 /* USB_VBUS_DET */
277 MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
278# define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28)
279 /* USBO1_ID */
280 MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
281 /* USBO1_EN */
5177087f 282 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
592f4aed
MK		 283# define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
284};
285
286/*
287 * UARTs are used in DTE mode, switch the mode on all UARTs before
288 * any pinmuxing connects a (DCE) output to a transceiver output.
289 */
389f61ef
MK		 290#define UCR3 0x88 /* FIFO Control Register */
291#define UCR3_RI BIT(8) /* RIDELT DTE mode */
292#define UCR3_DCD BIT(9) /* DCDDELT DTE mode */
592f4aed 293#define UFCR 0x90 /* FIFO Control Register */
389f61ef 294#define UFCR_DCEDTE BIT(6) /* DCE=0 */
592f4aed
MK		 295
296static void setup_dtemode_uart(void)
297{
298 setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
299 setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
300 setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
301 setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
389f61ef
MK		 302
303 clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
304 clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
305 clrbits_le32((u32 *)(UART4_BASE + UCR3), UCR3_DCD | UCR3_RI);
306 clrbits_le32((u32 *)(UART5_BASE + UCR3), UCR3_DCD | UCR3_RI);
592f4aed 307}
592f4aed
MK		 308
309static void setup_iomux_dte_uart(void)
310{
311 setup_dtemode_uart();
312 imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
313 ARRAY_SIZE(uart1_pads_dte));
314}
592f4aed
MK		 315
316#ifdef CONFIG_USB_EHCI_MX6
317int board_ehci_hcd_init(int port)
318{
319 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
320 return 0;
321}
592f4aed
MK		 322#endif
323
536c564b 324#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
5177087f 325/* use the following sequence: eMMC, MMC1, SD1 */
6cc04547 326struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = {
592f4aed
MK		 327 {USDHC3_BASE_ADDR},
328 {USDHC1_BASE_ADDR},
329 {USDHC2_BASE_ADDR},
330};
331
332int board_mmc_getcd(struct mmc *mmc)
333{
334 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
335 int ret = true; /* default: assume inserted */
336
337 switch (cfg->esdhc_base) {
338 case USDHC1_BASE_ADDR:
5177087f 339 gpio_request(GPIO_MMC_CD, "MMC_CD");
592f4aed
MK		 340 gpio_direction_input(GPIO_MMC_CD);
341 ret = !gpio_get_value(GPIO_MMC_CD);
342 break;
343 case USDHC2_BASE_ADDR:
5177087f 344 gpio_request(GPIO_MMC_CD, "SD_CD");
592f4aed
MK		 345 gpio_direction_input(GPIO_SD_CD);
346 ret = !gpio_get_value(GPIO_SD_CD);
347 break;
348 }
349
350 return ret;
351}
352
b75d8dc5 353int board_mmc_init(struct bd_info *bis)
592f4aed 354{
592f4aed
MK		 355 struct src *psrc = (struct src *)SRC_BASE_ADDR;
356 unsigned reg = readl(&psrc->sbmr1) >> 11;
357 /*
358 * Upon reading BOOT_CFG register the following map is done:
359 * Bit 11 and 12 of BOOT_CFG register can determine the current
360 * mmc port
361 * 0x1 SD1
362 * 0x2 SD2
363 * 0x3 SD4
364 */
365
366 switch (reg & 0x3) {
367 case 0x0:
368 imx_iomux_v3_setup_multiple_pads(
369 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
370 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
371 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
372 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
373 break;
374 case 0x1:
375 imx_iomux_v3_setup_multiple_pads(
376 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
377 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
378 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
379 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
380 break;
381 case 0x2:
382 imx_iomux_v3_setup_multiple_pads(
383 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
384 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
385 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
386 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
387 break;
388 default:
389 puts("MMC boot device not available");
390 }
391
392 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
592f4aed 393}
e37ac717 394#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
592f4aed
MK		 395
396int board_phy_config(struct phy_device *phydev)
397{
398 mx6_rgmii_rework(phydev);
399 if (phydev->drv->config)
400 phydev->drv->config(phydev);
401
402 return 0;
403}
404
592f4aed
MK		 405static iomux_v3_cfg_t const pwr_intb_pads[] = {
406 /*
407 * the bootrom sets the iomux to vselect, potentially connecting
408 * two outputs. Set this back to GPIO
409 */
410 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
411};
412
413#if defined(CONFIG_VIDEO_IPUV3)
414
415static iomux_v3_cfg_t const backlight_pads[] = {
416 /* Backlight on RGB connector: J15 */
5177087f
MZ		 417 MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) |
418 MUX_MODE_SION,
592f4aed
MK		 419#define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
420 /* additional CPU pin on BKL_PWM, keep in tristate */
421 MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
422 /* Backlight PWM, used as GPIO in U-Boot */
5177087f
MZ		 423 MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL) |
424 MUX_MODE_SION,
592f4aed
MK		 425#define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
426 /* buffer output enable 0: buffer enabled */
5177087f 427 MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
592f4aed
MK		 428#define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
429 /* PSAVE# integrated VDAC */
5177087f
MZ		 430 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) |
431 MUX_MODE_SION,
592f4aed
MK		 432#define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
433};
434
435static iomux_v3_cfg_t const rgb_pads[] = {
436 MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
437 MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
438 MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
439 MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
440 MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
441 MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
442 MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
443 MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
444 MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
445 MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
446 MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
447 MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
448 MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
449 MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
450 MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
451 MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
452 MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
453 MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
454 MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
455 MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
456 MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
457 MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
458 MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB),
459 MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB),
460 MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB),
461 MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB),
462 MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB),
463 MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB),
464};
465
592f4aed
MK		 466static void do_enable_hdmi(struct display_info_t const *dev)
467{
468 imx_enable_hdmi_phy();
469}
470
592f4aed
MK		 471static void enable_lvds(struct display_info_t const *dev)
472{
473 struct iomuxc *iomux = (struct iomuxc *)
474 IOMUXC_BASE_ADDR;
475 u32 reg = readl(&iomux->gpr[2]);
476 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
477 writel(reg, &iomux->gpr[2]);
478 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
479 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
480 gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
481}
482
483static void enable_rgb(struct display_info_t const *dev)
484{
485 imx_iomux_v3_setup_multiple_pads(
486 rgb_pads,
487 ARRAY_SIZE(rgb_pads));
488 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
489 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
490 gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
491}
492
493static int detect_default(struct display_info_t const *dev)
494{
495 (void) dev;
496 return 1;
497}
498
499struct display_info_t const displays[] = {{
500 .bus = -1,
501 .addr = 0,
502 .pixfmt = IPU_PIX_FMT_RGB24,
503 .detect = detect_hdmi,
504 .enable = do_enable_hdmi,
505 .mode = {
506 .name = "HDMI",
507 .refresh = 60,
508 .xres = 1024,
509 .yres = 768,
510 .pixclock = 15385,
511 .left_margin = 220,
512 .right_margin = 40,
513 .upper_margin = 21,
514 .lower_margin = 7,
515 .hsync_len = 60,
516 .vsync_len = 10,
517 .sync = FB_SYNC_EXT,
518 .vmode = FB_VMODE_NONINTERLACED
519} }, {
520 .bus = -1,
521 .addr = 0,
522 .di = 1,
523 .pixfmt = IPU_PIX_FMT_RGB24,
524 .detect = detect_default,
525 .enable = enable_rgb,
526 .mode = {
527 .name = "vga-rgb",
528 .refresh = 60,
529 .xres = 640,
530 .yres = 480,
531 .pixclock = 33000,
532 .left_margin = 48,
533 .right_margin = 16,
534 .upper_margin = 31,
535 .lower_margin = 11,
536 .hsync_len = 96,
537 .vsync_len = 2,
538 .sync = 0,
539 .vmode = FB_VMODE_NONINTERLACED
540} }, {
541 .bus = -1,
542 .addr = 0,
543 .di = 1,
544 .pixfmt = IPU_PIX_FMT_RGB24,
545 .enable = enable_rgb,
546 .mode = {
547 .name = "wvga-rgb",
548 .refresh = 60,
549 .xres = 800,
550 .yres = 480,
551 .pixclock = 25000,
552 .left_margin = 40,
553 .right_margin = 88,
554 .upper_margin = 33,
555 .lower_margin = 10,
556 .hsync_len = 128,
557 .vsync_len = 2,
558 .sync = 0,
559 .vmode = FB_VMODE_NONINTERLACED
560} }, {
561 .bus = -1,
562 .addr = 0,
563 .pixfmt = IPU_PIX_FMT_LVDS666,
592f4aed
MK		 564 .enable = enable_lvds,
565 .mode = {
566 .name = "wsvga-lvds",
567 .refresh = 60,
568 .xres = 1024,
569 .yres = 600,
570 .pixclock = 15385,
571 .left_margin = 220,
572 .right_margin = 40,
573 .upper_margin = 21,
574 .lower_margin = 7,
575 .hsync_len = 60,
576 .vsync_len = 10,
577 .sync = FB_SYNC_EXT,
578 .vmode = FB_VMODE_NONINTERLACED
579} } };
580size_t display_count = ARRAY_SIZE(displays);
581
582static void setup_display(void)
583{
584 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
585 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
586 int reg;
587
588 enable_ipu_clock();
589 imx_setup_hdmi();
590 /* Turn on LDB0,IPU,IPU DI0 clocks */
591 reg = __raw_readl(&mxc_ccm->CCGR3);
592 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
593 writel(reg, &mxc_ccm->CCGR3);
594
595 /* set LDB0, LDB1 clk select to 011/011 */
596 reg = readl(&mxc_ccm->cs2cdr);
597 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
598 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
599 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
600 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
601 writel(reg, &mxc_ccm->cs2cdr);
602
603 reg = readl(&mxc_ccm->cscmr2);
604 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
605 writel(reg, &mxc_ccm->cscmr2);
606
607 reg = readl(&mxc_ccm->chsccdr);
608 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
609 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
610 writel(reg, &mxc_ccm->chsccdr);
611
612 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
613 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
614 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
615 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
616 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
617 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
618 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
619 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
620 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
621 writel(reg, &iomux->gpr[2]);
622
623 reg = readl(&iomux->gpr[3]);
624 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
625 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
626 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
627 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
628 writel(reg, &iomux->gpr[3]);
629
630 /* backlight unconditionally on for now */
631 imx_iomux_v3_setup_multiple_pads(backlight_pads,
632 ARRAY_SIZE(backlight_pads));
633 /* use 0 for EDT 7", use 1 for LG fullHD panel */
5177087f
MZ		 634 gpio_request(RGB_BACKLIGHTPWM_GP, "BKL1_PWM");
635 gpio_request(RGB_BACKLIGHTPWM_OE, "BKL1_PWM_EN");
636 gpio_request(RGB_BACKLIGHT_GP, "BKL1_ON");
592f4aed
MK		 637 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
638 gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
639 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
640}
a3c90217
GS		 641
642/*
643 * Backlight off before OS handover
644 */
645void board_preboot_os(void)
646{
647 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
648 gpio_direction_output(RGB_BACKLIGHT_GP, 0);
649}
592f4aed
MK		 650#endif /* defined(CONFIG_VIDEO_IPUV3) */
651
652int board_early_init_f(void)
653{
654 imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
655 ARRAY_SIZE(pwr_intb_pads));
592f4aed 656 setup_iomux_dte_uart();
405c97fd 657
592f4aed
MK		 658 return 0;
659}
660
661/*
662 * Do not overwrite the console
663 * Use always serial for U-Boot console
664 */
665int overwrite_console(void)
666{
667 return 1;
668}
669
670int board_init(void)
671{
672 /* address of boot parameters */
673 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
674
f89bfe7c
FE		 675#if defined(CONFIG_VIDEO_IPUV3)
676 setup_display();
677#endif
678
592f4aed
MK		 679#ifdef CONFIG_TDX_CMD_IMX_MFGR
680 (void) pmic_init();
681#endif
682
10e40d54 683#ifdef CONFIG_SATA
592f4aed
MK		 684 setup_sata();
685#endif
686
687 setup_iomux_gpio();
688
689 return 0;
690}
691
692#ifdef CONFIG_BOARD_LATE_INIT
693int board_late_init(void)
694{
9774462e 695#if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
592f4aed
MK		 696 char env_str[256];
697 u32 rev;
698
9774462e 699 rev = get_board_revision();
592f4aed 700 snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
382bee57 701 env_set("board_rev", env_str);
405c97fd 702#endif /* CONFIG_BOARD_LATE_INIT */
592f4aed 703
220bb4e1 704 if (IS_ENABLED(CONFIG_USB) && is_boot_from_usb()) {
15834c63 705 env_set("bootdelay", "0");
220bb4e1
HDF		 706 if (IS_ENABLED(CONFIG_CMD_USB_SDP)) {
707 printf("Serial Downloader recovery mode, using sdp command\n");
708 env_set("bootcmd", "sdp 0");
709 } else if (IS_ENABLED(CONFIG_CMD_FASTBOOT)) {
710 printf("Fastboot recovery mode, using fastboot command\n");
711 env_set("bootcmd", "fastboot usb 0");
712 }
15834c63 713 }
15834c63 714
592f4aed
MK		 715 return 0;
716}
717#endif /* CONFIG_BOARD_LATE_INIT */
718
592f4aed 719#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
b75d8dc5 720int ft_board_setup(void *blob, struct bd_info *bd)
592f4aed
MK		 721{
722 return ft_common_board_setup(blob, bd);
723}
724#endif
725
726#ifdef CONFIG_CMD_BMODE
727static const struct boot_mode board_boot_modes[] = {
728 /* 4-bit bus width */
729 {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
730 {"sd", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
731 {NULL, 0},
732};
733#endif
734
735int misc_init_r(void)
736{
737#ifdef CONFIG_CMD_BMODE
738 add_board_boot_modes(board_boot_modes);
739#endif
740 return 0;
741}
742
743#ifdef CONFIG_LDO_BYPASS_CHECK
744/* TODO, use external pmic, for now always ldo_enable */
745void ldo_mode_set(int ldo_bypass)
746{
747 return;
748}
749#endif
750
751#ifdef CONFIG_SPL_BUILD
752#include <spl.h>
b08c8c48 753#include <linux/libfdt.h>
592f4aed
MK		 754#include "asm/arch/mx6q-ddr.h"
755#include "asm/arch/iomux.h"
756#include "asm/arch/crm_regs.h"
757
592f4aed
MK		 758static void ccgr_init(void)
759{
760 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
761
762 writel(0x00C03F3F, &ccm->CCGR0);
763 writel(0x0030FC03, &ccm->CCGR1);
764 writel(0x0FFFFFF3, &ccm->CCGR2);
765 writel(0x3FF0300F, &ccm->CCGR3);
766 writel(0x00FFF300, &ccm->CCGR4);
767 writel(0x0F0000F3, &ccm->CCGR5);
768 writel(0x000003FF, &ccm->CCGR6);
769
770/*
771 * Setup CCM_CCOSR register as follows:
772 *
d4cd19de
FD		 773 * clko2_en = 1 --> CKO2 enabled
774 * clko2_div = 000 --> divide by 1
775 * clko2_sel = 01110 --> osc_clk (24MHz)
592f4aed 776 *
d4cd19de
FD		 777 * clk_out_sel = 1 --> Output CKO2 to CKO1
778 *
779 * This sets both CLKO2/CLKO1 output to 24MHz,
780 * CLKO1 configuration not relevant because of clk_out_sel
781 * (CLKO1 set to default)
592f4aed 782 */
d4cd19de 783 writel(0x010E0101, &ccm->ccosr);
592f4aed
MK		 784}
785
592f4aed 786
66af2c3e
FD		 787#define PAD_CTL_INPUT_DDR BIT(17)
788
789struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
790 /* Differential input, 40 ohm DSE */
791 .dram_sdclk_0 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
792 .dram_sdclk_1 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
793 .dram_cas = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
794 .dram_ras = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
795 .dram_reset = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
796
797 /* SDKE[0:1]: BIT(12) and BIT(13) are reserved and set at reset */
798 .dram_sdcke0 = 0x00003000,
799 .dram_sdcke1 = 0x00003000,
800
801 .dram_sdba2 = 0x00000000,
802
803 /* ODT[0:1]: 40 ohm DSE, BIT(12) and BIT(13) are reserved and set at reset */
804 .dram_sdodt0 = PAD_CTL_DSE_40ohm | 0x00003000,
805 .dram_sdodt1 = PAD_CTL_DSE_40ohm | 0x00003000,
806
807 /* SDQS[0:7]: 40 ohm DSE, Pull/Keeper Disabled, ODT Disabled */
808 .dram_sdqs0 = PAD_CTL_DSE_40ohm,
809 .dram_sdqs1 = PAD_CTL_DSE_40ohm,
810 .dram_sdqs2 = PAD_CTL_DSE_40ohm,
811 .dram_sdqs3 = PAD_CTL_DSE_40ohm,
812 .dram_sdqs4 = PAD_CTL_DSE_40ohm,
813 .dram_sdqs5 = PAD_CTL_DSE_40ohm,
814 .dram_sdqs6 = PAD_CTL_DSE_40ohm,
815 .dram_sdqs7 = PAD_CTL_DSE_40ohm,
816
817 /* DQM[0:7]: Differential input, 40 ohm DSE, Pull/Keeper Disabled, ODT Disabled */
818 .dram_dqm0 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
819 .dram_dqm1 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
820 .dram_dqm2 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
821 .dram_dqm3 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
822 .dram_dqm4 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
823 .dram_dqm5 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
824 .dram_dqm6 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
825 .dram_dqm7 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
826};
827
828struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
829 /* DDR3 */
830 .grp_ddr_type = 0x000C0000,
831
832 /* SDQS[0:7]: Differential input */
833 .grp_ddrmode_ctl = PAD_CTL_INPUT_DDR,
834
835 /* DATA[0:63]: Pull/Keeper disabled */
836 .grp_ddrpke = 0,
837
838 /* ADDR[0:16], SDBA[0:1]: 40 ohm DSE */
839 .grp_addds = PAD_CTL_DSE_40ohm,
840
841 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm DSE */
842 .grp_ctlds = PAD_CTL_DSE_40ohm,
843
844 /* DATA[0:63]: Differential input */
845 .grp_ddrmode = PAD_CTL_INPUT_DDR,
846
847 /* DATA[0:63]: 40 ohm DSE */
848 .grp_b0ds = PAD_CTL_DSE_40ohm,
849 .grp_b1ds = PAD_CTL_DSE_40ohm,
850 .grp_b2ds = PAD_CTL_DSE_40ohm,
851 .grp_b3ds = PAD_CTL_DSE_40ohm,
852 .grp_b4ds = PAD_CTL_DSE_40ohm,
853 .grp_b5ds = PAD_CTL_DSE_40ohm,
854 .grp_b6ds = PAD_CTL_DSE_40ohm,
855 .grp_b7ds = PAD_CTL_DSE_40ohm,
856};
857
858struct mx6_ddr_sysinfo sysinfo = {
859 .dsize = 2, /* width of data bus: 2=64 */
860 .cs_density = 32, /* full range so that get_mem_size() works, 32Gb per CS */
861 .ncs = 1,
862 .cs1_mirror = 0,
863 .rtt_wr = 2, /* Dynamic ODT, RZQ/2 */
864 .rtt_nom = 0, /* Disabled */
865 .walat = 0, /* Write additional latency */
866 .ralat = 5, /* Read additional latency */
867 .mif3_mode = 3, /* Command prediction working mode */
868 .bi_on = 1, /* Bank interleaving enabled */
869 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
870 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
871 .pd_fast_exit = 1, /* enable precharge power-down fast exit */
872 .ddr_type = DDR_TYPE_DDR3,
873 .refsel = 1, /* Refresh cycles at 32KHz */
874 .refr = 3, /* 4 refresh commands per refresh cycle */
875};
876
877static const struct mx6_mmdc_calibration mx6_mmdc_calib = {
878 .p0_mpwldectrl0 = 0x0009000E,
879 .p0_mpwldectrl1 = 0x0018000B,
880 .p1_mpwldectrl0 = 0x00060015,
881 .p1_mpwldectrl1 = 0x0006000E,
882 .p0_mpdgctrl0 = 0x432A0338,
883 .p0_mpdgctrl1 = 0x03260324,
884 .p1_mpdgctrl0 = 0x43340344,
885 .p1_mpdgctrl1 = 0x031E027C,
886 .p0_mprddlctl = 0x33272D2E,
887 .p1_mprddlctl = 0x2F312B37,
888 .p0_mpwrdlctl = 0x3A35433C,
889 .p1_mpwrdlctl = 0x4336453F,
890};
891
892static const struct mx6_ddr3_cfg ddr3_cfg = {
893 .mem_speed = 1066,
894 .density = 2,
895 .width = 16,
896 .banks = 8,
897 .rowaddr = 14,
898 .coladdr = 10,
899 .pagesz = 2,
900 .trcd = 1312,
901 .trcmin = 4812,
902 .trasmin = 3500,
903 .SRT = 0,
904};
905
906struct mx6_ddr_sysinfo sysinfo_it = {
907 .dsize = 2, /* width of data bus: 2=64 */
908 .cs_density = 32, /* full range so that get_mem_size() works, 32Gb per CS */
909 .ncs = 1,
910 .cs1_mirror = 0,
911 .rtt_wr = 1, /* Dynamic ODT, RZQ/4 */
912 .rtt_nom = 1, /* RZQ/4 */
913 .walat = 0, /* Write additional latency */
914 .ralat = 5, /* Read additional latency */
915 .mif3_mode = 3, /* Command prediction working mode */
916 .bi_on = 1, /* Bank interleaving enabled */
917 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
918 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
919 .pd_fast_exit = 1, /* enable precharge power-down fast exit */
920 .ddr_type = DDR_TYPE_DDR3,
921 .refsel = 1, /* Refresh cycles at 32KHz */
922 .refr = 7, /* 8 refresh commands per refresh cycle */
923};
924
925static const struct mx6_mmdc_calibration mx6_mmdc_calib_it = {
926 .p0_mpwldectrl0 = 0x0009000E,
927 .p0_mpwldectrl1 = 0x0018000B,
928 .p1_mpwldectrl0 = 0x00060015,
929 .p1_mpwldectrl1 = 0x0006000E,
930 .p0_mpdgctrl0 = 0x03300338,
931 .p0_mpdgctrl1 = 0x03240324,
932 .p1_mpdgctrl0 = 0x03440350,
933 .p1_mpdgctrl1 = 0x032C0308,
934 .p0_mprddlctl = 0x40363C3E,
935 .p1_mprddlctl = 0x3C3E3C46,
936 .p0_mpwrdlctl = 0x403E463E,
937 .p1_mpwrdlctl = 0x4A384C46,
938};
939
940static const struct mx6_ddr3_cfg ddr3_cfg_it = {
941 .mem_speed = 1066,
942 .density = 4,
943 .width = 16,
944 .banks = 8,
945 .rowaddr = 15,
946 .coladdr = 10,
947 .pagesz = 2,
948 .trcd = 1312,
949 .trcmin = 4812,
950 .trasmin = 3500,
951 .SRT = 1,
952};
953
592f4aed 954
a591e75f 955/* Perform DDR DRAM calibration */
66af2c3e 956static void spl_dram_perform_cal(const struct mx6_ddr_sysinfo *ddr_sysinfo)
a591e75f
FD		 957{
958#ifdef CONFIG_MX6_DDRCAL
959 int err;
a591e75f 960
66af2c3e 961 err = mmdc_do_write_level_calibration(ddr_sysinfo);
a591e75f
FD		 962 if (err)
963 printf("error %d from write level calibration\n", err);
66af2c3e 964 err = mmdc_do_dqs_calibration(ddr_sysinfo);
a591e75f
FD		 965 if (err)
966 printf("error %d from dqs calibration\n", err);
967#endif
968}
969
592f4aed
MK		 970static void spl_dram_init(void)
971{
66af2c3e 972 bool temp_grade_it;
592f4aed 973
66af2c3e 974 switch (get_cpu_temp_grade(NULL, NULL)) {
592f4aed
MK		 975 case TEMP_COMMERCIAL:
976 case TEMP_EXTCOMMERCIAL:
977 puts("Commercial temperature grade DDR3 timings.\n");
66af2c3e 978 temp_grade_it = false;
592f4aed
MK		 979 break;
980 case TEMP_INDUSTRIAL:
981 case TEMP_AUTOMOTIVE:
982 default:
983 puts("Industrial temperature grade DDR3 timings.\n");
66af2c3e 984 temp_grade_it = true;
592f4aed
MK		 985 break;
986 };
66af2c3e
FD		 987
988 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
989
990 if (temp_grade_it)
991 mx6_dram_cfg(&sysinfo_it, &mx6_mmdc_calib_it, &ddr3_cfg_it);
992 else
993 mx6_dram_cfg(&sysinfo, &mx6_mmdc_calib, &ddr3_cfg);
994
592f4aed 995 udelay(100);
66af2c3e
FD		 996
997 if (temp_grade_it)
998 spl_dram_perform_cal(&sysinfo_it);
999 else
1000 spl_dram_perform_cal(&sysinfo);
592f4aed
MK		 1001}
1002
1003void board_init_f(ulong dummy)
1004{
1005 /* setup AIPS and disable watchdog */
1006 arch_cpu_init();
1007
1008 ccgr_init();
1009 gpr_init();
1010
ab92352d 1011 /* iomux */
592f4aed
MK		 1012 board_early_init_f();
1013
1014 /* setup GP timer */
1015 timer_init();
1016
1017 /* UART clocks enabled and gd valid - init serial console */
1018 preloader_console_init();
1019
592f4aed
MK		 1020 /* Make sure we use dte mode */
1021 setup_dtemode_uart();
592f4aed
MK		 1022
1023 /* DDR initialization */
1024 spl_dram_init();
1025
1026 /* Clear the BSS. */
1027 memset(__bss_start, 0, __bss_end - __bss_start);
1028
1029 /* load/boot image from boot device */
1030 board_init_r(NULL, 0);
1031}
1032
6f8ef051
RS		 1033#ifdef CONFIG_SPL_LOAD_FIT
1034int board_fit_config_name_match(const char *name)
1035{
1036 if (!strcmp(name, "imx6-apalis"))
1037 return 0;
1038
1039 return -1;
1040}
1041#endif
1042
35b65dd8 1043void reset_cpu(void)
592f4aed
MK		 1044{
1045}
1046
5177087f 1047#endif /* CONFIG_SPL_BUILD */
592f4aed 1048
8a8d24bd 1049static struct mxc_serial_plat mxc_serial_plat = {
592f4aed
MK		 1050 .reg = (struct mxc_uart *)UART1_BASE,
1051 .use_dte = true,
1052};
1053
20e442ab 1054U_BOOT_DRVINFO(mxc_serial) = {
592f4aed 1055 .name = "serial_mxc",
caa4daa2 1056 .plat = &mxc_serial_plat,
592f4aed 1057};
"Das U-Boot" Source Tree