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Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""
[thirdparty/u-boot.git] / board / toradex / colibri_imx6 / colibri_imx6.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
a02d517b
MK		 2/*
3 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
4 * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
e7cf5349 5 * Copyright (C) 2014-2019, Toradex AG
a02d517b 6 * copied from nitrogen6x
a02d517b
MK		 7 */
8
d678a59d 9#include <common.h>
9a3b4ceb 10#include <cpu_func.h>
9d922450 11#include <dm.h>
9eef56db 12#include <env.h>
5255932f 13#include <init.h>
90526e9f 14#include <net.h>
401d1c4f 15#include <asm/global_data.h>
cd93d625 16#include <linux/bitops.h>
c05ed00a 17#include <linux/delay.h>
e7cf5349 18
a02d517b
MK		 19#include <asm/arch/clock.h>
20#include <asm/arch/crm_regs.h>
21#include <asm/arch/imx-regs.h>
a02d517b 22#include <asm/arch/mx6-ddr.h>
e7cf5349 23#include <asm/arch/mx6-pins.h>
a02d517b
MK		 24#include <asm/arch/mxc_hdmi.h>
25#include <asm/arch/sys_proto.h>
26#include <asm/bootm.h>
27#include <asm/gpio.h>
e7cf5349 28#include <asm/mach-imx/boot_mode.h>
552a848e 29#include <asm/mach-imx/iomux-v3.h>
552a848e 30#include <asm/mach-imx/sata.h>
552a848e 31#include <asm/mach-imx/video.h>
506df9dc 32#include <asm/sections.h>
bee73083 33#include <cpu.h>
a02d517b 34#include <dm/platform_data/serial_mxc.h>
e37ac717 35#include <fsl_esdhc_imx.h>
a02d517b 36#include <imx_thermal.h>
a02d517b 37#include <miiphy.h>
a02d517b 38#include <netdev.h>
82029bf5 39#include <cpu.h>
a02d517b
MK		 40
41#include "../common/tdx-cfg-block.h"
42#ifdef CONFIG_TDX_CMD_IMX_MFGR
43#include "pf0100.h"
44#endif
45
46DECLARE_GLOBAL_DATA_PTR;
47
48#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
49 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
50 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
51
52#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
eaa50e08
MK		 53 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
54 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
55
56#define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
a02d517b
MK		 57 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
58 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
59
a02d517b
MK		 60#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
61 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
62 PAD_CTL_SRE_SLOW)
63
64#define NO_PULLUP ( \
65 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
66 PAD_CTL_SRE_SLOW)
67
68#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
69 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
70 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
71
a02d517b
MK		 72#define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
73
74int dram_init(void)
75{
76 /* use the DDR controllers configured size */
aa6e94de 77 gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
a02d517b
MK		 78 (ulong)imx_ddr_size());
79
80 return 0;
81}
82
83/* Colibri UARTA */
84iomux_v3_cfg_t const uart1_pads[] = {
85 MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
86 MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
87};
88
bfeaea7d 89#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
6eea69bd 90/* Colibri MMC */
a02d517b
MK		 91iomux_v3_cfg_t const usdhc1_pads[] = {
92 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
95 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
96 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
97 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
98 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
99# define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
100};
101
102/* eMMC */
103iomux_v3_cfg_t const usdhc3_pads[] = {
eaa50e08
MK		 104 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
105 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
106 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
107 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
108 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
109 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
110 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
111 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
112 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
113 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
a02d517b
MK		 114 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
115};
e37ac717 116#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
a02d517b 117
a02d517b
MK		 118/* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
119iomux_v3_cfg_t const gpio_pads[] = {
120 /* ADDRESS[17:18] [25] used as GPIO */
e7cf5349
MZ		 121 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
122 MUX_MODE_SION,
123 MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
124 MUX_MODE_SION,
125 MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(WEAK_PULLUP) |
126 MUX_MODE_SION,
a02d517b 127 /* ADDRESS[19:24] used as GPIO */
e7cf5349
MZ		 128 MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
129 MUX_MODE_SION,
130 MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
131 MUX_MODE_SION,
132 MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
133 MUX_MODE_SION,
134 MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
135 MUX_MODE_SION,
136 MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
137 MUX_MODE_SION,
138 MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP) |
139 MUX_MODE_SION,
a02d517b 140 /* DATA[16:29] [31] used as GPIO */
e7cf5349
MZ		 141 MX6_PAD_EIM_LBA__GPIO2_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) |
142 MUX_MODE_SION,
143 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) |
144 MUX_MODE_SION,
145 MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
146 MUX_MODE_SION,
147 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
148 MUX_MODE_SION,
149 MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
150 MUX_MODE_SION,
151 MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
152 MUX_MODE_SION,
153 MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP) |
154 MUX_MODE_SION,
155 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
156 MUX_MODE_SION,
157 MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
158 MUX_MODE_SION,
159 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
160 MUX_MODE_SION,
161 MX6_PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) |
162 MUX_MODE_SION,
163 MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
164 MUX_MODE_SION,
165 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
166 MUX_MODE_SION,
167 MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
168 MUX_MODE_SION,
169 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) |
170 MUX_MODE_SION,
a02d517b 171 /* DQM[0:3] used as GPIO */
e7cf5349
MZ		 172 MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(WEAK_PULLUP) |
173 MUX_MODE_SION,
174 MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(WEAK_PULLUP) |
175 MUX_MODE_SION,
176 MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
177 MUX_MODE_SION,
178 MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) |
179 MUX_MODE_SION,
a02d517b 180 /* RDY used as GPIO */
e7cf5349
MZ		 181 MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) |
182 MUX_MODE_SION,
a02d517b 183 /* ADDRESS[16] DATA[30] used as GPIO */
e7cf5349
MZ		 184 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
185 MUX_MODE_SION,
186 MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
187 MUX_MODE_SION,
a02d517b 188 /* CSI pins used as GPIO */
e7cf5349
MZ		 189 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
190 MUX_MODE_SION,
191 MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
192 MUX_MODE_SION,
193 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
194 MUX_MODE_SION,
195 MX6_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
196 MUX_MODE_SION,
197 MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) |
198 MUX_MODE_SION,
199 MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
200 MUX_MODE_SION,
201 MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
202 MUX_MODE_SION,
203 MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
204 MUX_MODE_SION,
205 MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(WEAK_PULLUP) |
206 MUX_MODE_SION,
207 MX6_PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) |
208 MUX_MODE_SION,
209 MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) |
210 MUX_MODE_SION,
211 MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
212 MUX_MODE_SION,
213 MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
214 MUX_MODE_SION,
a02d517b 215 /* GPIO */
e7cf5349
MZ		 216 MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(WEAK_PULLUP) |
217 MUX_MODE_SION,
218 MX6_PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) |
219 MUX_MODE_SION,
220 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
221 MUX_MODE_SION,
222 MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP) |
223 MUX_MODE_SION,
224 MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP) |
225 MUX_MODE_SION,
226 MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) |
227 MUX_MODE_SION,
228 MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
229 MUX_MODE_SION,
230 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
231 MUX_MODE_SION,
232 MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
233 MUX_MODE_SION,
234 MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
235 MUX_MODE_SION,
236 MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
237 MUX_MODE_SION,
a02d517b
MK		 238 /* USBH_OC */
239 MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(WEAK_PULLUP),
240 /* USBC_ID */
241 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP),
242 /* USBC_DET */
243 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
244};
245
246static void setup_iomux_gpio(void)
247{
248 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
249}
250
251iomux_v3_cfg_t const usb_pads[] = {
e7cf5349
MZ		 252 /* USBH_PEN */
253 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
a02d517b
MK		 254# define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
255};
256
257/*
258 * UARTs are used in DTE mode, switch the mode on all UARTs before
259 * any pinmuxing connects a (DCE) output to a transceiver output.
260 */
08621424
MK		 261#define UCR3 0x88 /* FIFO Control Register */
262#define UCR3_RI BIT(8) /* RIDELT DTE mode */
263#define UCR3_DCD BIT(9) /* DCDDELT DTE mode */
a02d517b 264#define UFCR 0x90 /* FIFO Control Register */
08621424 265#define UFCR_DCEDTE BIT(6) /* DCE=0 */
a02d517b
MK		 266
267static void setup_dtemode_uart(void)
268{
269 setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
270 setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
271 setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
08621424
MK		 272
273 clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
274 clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
275 clrbits_le32((u32 *)(UART3_BASE + UCR3), UCR3_DCD | UCR3_RI);
a02d517b
MK		 276}
277
278static void setup_iomux_uart(void)
279{
280 setup_dtemode_uart();
281 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
282}
283
284#ifdef CONFIG_USB_EHCI_MX6
285int board_ehci_hcd_init(int port)
286{
287 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
288 return 0;
289}
7b726c09 290#endif
a02d517b 291
bfeaea7d 292#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
a02d517b 293/* use the following sequence: eMMC, MMC */
6cc04547 294struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = {
a02d517b
MK		 295 {USDHC3_BASE_ADDR},
296 {USDHC1_BASE_ADDR},
297};
298
299int board_mmc_getcd(struct mmc *mmc)
300{
301 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
302 int ret = true; /* default: assume inserted */
303
304 switch (cfg->esdhc_base) {
305 case USDHC1_BASE_ADDR:
e7cf5349 306 gpio_request(GPIO_MMC_CD, "MMC_CD");
a02d517b
MK		 307 gpio_direction_input(GPIO_MMC_CD);
308 ret = !gpio_get_value(GPIO_MMC_CD);
309 break;
310 }
311
312 return ret;
313}
314
b75d8dc5 315int board_mmc_init(struct bd_info *bis)
a02d517b 316{
a02d517b
MK		 317 struct src *psrc = (struct src *)SRC_BASE_ADDR;
318 unsigned reg = readl(&psrc->sbmr1) >> 11;
319 /*
320 * Upon reading BOOT_CFG register the following map is done:
321 * Bit 11 and 12 of BOOT_CFG register can determine the current
322 * mmc port
323 * 0x1 SD1
324 * 0x2 SD2
325 * 0x3 SD4
326 */
327
328 switch (reg & 0x3) {
329 case 0x0:
330 imx_iomux_v3_setup_multiple_pads(
331 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
332 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
333 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
334 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
335 break;
336 case 0x2:
337 imx_iomux_v3_setup_multiple_pads(
338 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
339 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
340 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
341 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
342 break;
343 default:
344 puts("MMC boot device not available");
345 }
346
347 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
a02d517b 348}
e37ac717 349#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
a02d517b
MK		 350
351int board_phy_config(struct phy_device *phydev)
352{
353 if (phydev->drv->config)
354 phydev->drv->config(phydev);
355
356 return 0;
357}
358
431cd76d 359int setup_fec(void)
a02d517b 360{
a02d517b 361 int ret;
1efb80c4 362 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
a02d517b
MK		 363
364 /* provide the PHY clock from the i.MX 6 */
365 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
366 if (ret)
367 return ret;
e7cf5349 368
1efb80c4
IO		 369 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
370
a02d517b
MK		 371 return 0;
372}
373
374static iomux_v3_cfg_t const pwr_intb_pads[] = {
375 /*
376 * the bootrom sets the iomux to vselect, potentially connecting
377 * two outputs. Set this back to GPIO
378 */
379 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
380};
381
382#if defined(CONFIG_VIDEO_IPUV3)
383
384static iomux_v3_cfg_t const backlight_pads[] = {
385 /* Backlight On */
e7cf5349 386 MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
a02d517b
MK		 387#define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
388 /* Backlight PWM, used as GPIO in U-Boot */
389 MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PULLUP),
e7cf5349
MZ		 390 MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL) |
391 MUX_MODE_SION,
a02d517b
MK		 392#define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
393};
394
395static iomux_v3_cfg_t const rgb_pads[] = {
396 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
397 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
398 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
399 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
400 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
401 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
402 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
403 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
404 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
405 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
406 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
407 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
408 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
409 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
410 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
411 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
412 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
413 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
414 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
415 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
416 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
417 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
418};
419
420static void do_enable_hdmi(struct display_info_t const *dev)
421{
422 imx_enable_hdmi_phy();
423}
424
425static void enable_rgb(struct display_info_t const *dev)
426{
427 imx_iomux_v3_setup_multiple_pads(
428 rgb_pads,
429 ARRAY_SIZE(rgb_pads));
430 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
431 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
432}
433
434static int detect_default(struct display_info_t const *dev)
435{
436 (void) dev;
437 return 1;
438}
439
440struct display_info_t const displays[] = {{
441 .bus = -1,
442 .addr = 0,
443 .pixfmt = IPU_PIX_FMT_RGB24,
444 .detect = detect_hdmi,
445 .enable = do_enable_hdmi,
446 .mode = {
447 .name = "HDMI",
448 .refresh = 60,
449 .xres = 1024,
450 .yres = 768,
451 .pixclock = 15385,
452 .left_margin = 220,
453 .right_margin = 40,
454 .upper_margin = 21,
455 .lower_margin = 7,
456 .hsync_len = 60,
457 .vsync_len = 10,
458 .sync = FB_SYNC_EXT,
459 .vmode = FB_VMODE_NONINTERLACED
460} }, {
461 .bus = -1,
462 .addr = 0,
463 .pixfmt = IPU_PIX_FMT_RGB666,
464 .detect = detect_default,
465 .enable = enable_rgb,
466 .mode = {
467 .name = "vga-rgb",
468 .refresh = 60,
469 .xres = 640,
470 .yres = 480,
471 .pixclock = 33000,
472 .left_margin = 48,
473 .right_margin = 16,
474 .upper_margin = 31,
475 .lower_margin = 11,
476 .hsync_len = 96,
477 .vsync_len = 2,
478 .sync = 0,
479 .vmode = FB_VMODE_NONINTERLACED
480} }, {
481 .bus = -1,
482 .addr = 0,
483 .pixfmt = IPU_PIX_FMT_RGB666,
484 .enable = enable_rgb,
485 .mode = {
486 .name = "wvga-rgb",
487 .refresh = 60,
488 .xres = 800,
489 .yres = 480,
490 .pixclock = 25000,
491 .left_margin = 40,
492 .right_margin = 88,
493 .upper_margin = 33,
494 .lower_margin = 10,
495 .hsync_len = 128,
496 .vsync_len = 2,
497 .sync = 0,
498 .vmode = FB_VMODE_NONINTERLACED
499} } };
500size_t display_count = ARRAY_SIZE(displays);
501
502static void setup_display(void)
503{
504 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
505 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
506 int reg;
507
508 enable_ipu_clock();
509 imx_setup_hdmi();
510 /* Turn on LDB0,IPU,IPU DI0 clocks */
511 reg = __raw_readl(&mxc_ccm->CCGR3);
512 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
513 writel(reg, &mxc_ccm->CCGR3);
514
515 /* set LDB0, LDB1 clk select to 011/011 */
516 reg = readl(&mxc_ccm->cs2cdr);
517 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
518 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
519 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
520 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
521 writel(reg, &mxc_ccm->cs2cdr);
522
523 reg = readl(&mxc_ccm->cscmr2);
524 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
525 writel(reg, &mxc_ccm->cscmr2);
526
527 reg = readl(&mxc_ccm->chsccdr);
528 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
529 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
530 writel(reg, &mxc_ccm->chsccdr);
531
532 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
533 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
534 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
535 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
536 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
537 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
538 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
539 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
540 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
541 writel(reg, &iomux->gpr[2]);
542
543 reg = readl(&iomux->gpr[3]);
544 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
545 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
546 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
547 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
548 writel(reg, &iomux->gpr[3]);
549
550 /* backlight unconditionally on for now */
551 imx_iomux_v3_setup_multiple_pads(backlight_pads,
552 ARRAY_SIZE(backlight_pads));
553 /* use 0 for EDT 7", use 1 for LG fullHD panel */
e7cf5349
MZ		 554 gpio_request(RGB_BACKLIGHTPWM_GP, "PWM<A>");
555 gpio_request(RGB_BACKLIGHT_GP, "BL_ON");
a02d517b
MK		 556 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
557 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
558}
a3c90217
GS		 559
560/*
561 * Backlight off before OS handover
562 */
563void board_preboot_os(void)
564{
565 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
566 gpio_direction_output(RGB_BACKLIGHT_GP, 0);
567}
a02d517b
MK		 568#endif /* defined(CONFIG_VIDEO_IPUV3) */
569
570int board_early_init_f(void)
571{
572 imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
573 ARRAY_SIZE(pwr_intb_pads));
574 setup_iomux_uart();
575
a02d517b
MK		 576 return 0;
577}
578
579/*
580 * Do not overwrite the console
581 * Use always serial for U-Boot console
582 */
583int overwrite_console(void)
584{
585 return 1;
586}
587
588int board_init(void)
589{
590 /* address of boot parameters */
591 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
431cd76d
IO		 592#if defined(CONFIG_FEC_MXC)
593 setup_fec();
594#endif
464c988a
FE		 595#if defined(CONFIG_VIDEO_IPUV3)
596 setup_display();
597#endif
598
a02d517b
MK		 599#ifdef CONFIG_TDX_CMD_IMX_MFGR
600 (void) pmic_init();
601#endif
602
10e40d54 603#ifdef CONFIG_SATA
a02d517b
MK		 604 setup_sata();
605#endif
606
607 setup_iomux_gpio();
608
609 return 0;
610}
611
612#ifdef CONFIG_BOARD_LATE_INIT
613int board_late_init(void)
614{
9774462e 615#if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
a02d517b
MK		 616 char env_str[256];
617 u32 rev;
618
9774462e 619 rev = get_board_revision();
a02d517b 620 snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
382bee57 621 env_set("board_rev", env_str);
a02d517b
MK		 622#endif
623
220bb4e1 624 if (IS_ENABLED(CONFIG_USB) && is_boot_from_usb()) {
52084bfc 625 env_set("bootdelay", "0");
220bb4e1
HDF		 626 if (IS_ENABLED(CONFIG_CMD_USB_SDP)) {
627 printf("Serial Downloader recovery mode, using sdp command\n");
628 env_set("bootcmd", "sdp 0");
629 } else if (IS_ENABLED(CONFIG_CMD_FASTBOOT)) {
630 printf("Fastboot recovery mode, using fastboot command\n");
631 env_set("bootcmd", "fastboot usb 0");
632 }
52084bfc 633 }
52084bfc 634
a02d517b
MK		 635 return 0;
636}
637#endif /* CONFIG_BOARD_LATE_INIT */
638
a02d517b 639#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
b75d8dc5 640int ft_board_setup(void *blob, struct bd_info *bd)
a02d517b 641{
bee73083
BD		 642 u32 cma_size;
643
644 ft_common_board_setup(blob, bd);
645
52084bfc 646 cma_size = env_get_ulong("cma-size", 10, 320 * 1024 * 1024);
bee73083
BD		 647 cma_size = min((u32)(gd->ram_size >> 1), cma_size);
648
649 fdt_setprop_u32(blob,
650 fdt_path_offset(blob, "/reserved-memory/linux,cma"),
651 "size",
652 cma_size);
653 return 0;
a02d517b
MK		 654}
655#endif
656
657#ifdef CONFIG_CMD_BMODE
658static const struct boot_mode board_boot_modes[] = {
659 {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
660 {NULL, 0},
661};
662#endif
663
664int misc_init_r(void)
665{
666#ifdef CONFIG_CMD_BMODE
667 add_board_boot_modes(board_boot_modes);
668#endif
669 return 0;
670}
671
672#ifdef CONFIG_LDO_BYPASS_CHECK
673/* TODO, use external pmic, for now always ldo_enable */
674void ldo_mode_set(int ldo_bypass)
675{
676 return;
677}
678#endif
679
680#ifdef CONFIG_SPL_BUILD
681#include <spl.h>
b08c8c48 682#include <linux/libfdt.h>
a02d517b
MK		 683#include "asm/arch/mx6dl-ddr.h"
684#include "asm/arch/iomux.h"
685#include "asm/arch/crm_regs.h"
686
687static int mx6s_dcd_table[] = {
688/* ddr-setup.cfg */
689
690MX6_IOM_DRAM_SDQS0, 0x00000030,
691MX6_IOM_DRAM_SDQS1, 0x00000030,
692MX6_IOM_DRAM_SDQS2, 0x00000030,
693MX6_IOM_DRAM_SDQS3, 0x00000030,
694MX6_IOM_DRAM_SDQS4, 0x00000030,
695MX6_IOM_DRAM_SDQS5, 0x00000030,
696MX6_IOM_DRAM_SDQS6, 0x00000030,
697MX6_IOM_DRAM_SDQS7, 0x00000030,
698
699MX6_IOM_GRP_B0DS, 0x00000030,
700MX6_IOM_GRP_B1DS, 0x00000030,
701MX6_IOM_GRP_B2DS, 0x00000030,
702MX6_IOM_GRP_B3DS, 0x00000030,
703MX6_IOM_GRP_B4DS, 0x00000030,
704MX6_IOM_GRP_B5DS, 0x00000030,
705MX6_IOM_GRP_B6DS, 0x00000030,
706MX6_IOM_GRP_B7DS, 0x00000030,
707MX6_IOM_GRP_ADDDS, 0x00000030,
708/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
709MX6_IOM_GRP_CTLDS, 0x00000030,
710
711MX6_IOM_DRAM_DQM0, 0x00020030,
712MX6_IOM_DRAM_DQM1, 0x00020030,
713MX6_IOM_DRAM_DQM2, 0x00020030,
714MX6_IOM_DRAM_DQM3, 0x00020030,
715MX6_IOM_DRAM_DQM4, 0x00020030,
716MX6_IOM_DRAM_DQM5, 0x00020030,
717MX6_IOM_DRAM_DQM6, 0x00020030,
718MX6_IOM_DRAM_DQM7, 0x00020030,
719
720MX6_IOM_DRAM_CAS, 0x00020030,
721MX6_IOM_DRAM_RAS, 0x00020030,
722MX6_IOM_DRAM_SDCLK_0, 0x00020030,
723MX6_IOM_DRAM_SDCLK_1, 0x00020030,
724
725MX6_IOM_DRAM_RESET, 0x00020030,
726MX6_IOM_DRAM_SDCKE0, 0x00003000,
727MX6_IOM_DRAM_SDCKE1, 0x00003000,
728
729MX6_IOM_DRAM_SDODT0, 0x00003030,
730MX6_IOM_DRAM_SDODT1, 0x00003030,
731
732/* (differential input) */
733MX6_IOM_DDRMODE_CTL, 0x00020000,
734/* (differential input) */
735MX6_IOM_GRP_DDRMODE, 0x00020000,
736/* disable ddr pullups */
737MX6_IOM_GRP_DDRPKE, 0x00000000,
738MX6_IOM_DRAM_SDBA2, 0x00000000,
739/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
740MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
741
742/* Read data DQ Byte0-3 delay */
743MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
744MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
745MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
746MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
747MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
748MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
749MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
750MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
751
752/*
753 * MDMISC mirroring interleaved (row/bank/col)
754 */
44103cf3 755MX6_MMDC_P0_MDMISC, 0x000b17c0,
a02d517b
MK		 756
757/*
758 * MDSCR con_req
759 */
760MX6_MMDC_P0_MDSCR, 0x00008000,
761
762
763/* 800mhz_2x64mx16.cfg */
764
765MX6_MMDC_P0_MDPDC, 0x0002002D,
766MX6_MMDC_P0_MDCFG0, 0x2C305503,
767MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
768MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
769MX6_MMDC_P0_MDRWD, 0x000026D2,
770MX6_MMDC_P0_MDOR, 0x00301023,
771MX6_MMDC_P0_MDOTC, 0x00333030,
772MX6_MMDC_P0_MDPDC, 0x0002556D,
773/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
774MX6_MMDC_P0_MDASP, 0x00000017,
775/* DDR3 DATA BUS SIZE: 64BIT */
776/* MX6_MMDC_P0_MDCTL, 0x821A0000, */
777/* DDR3 DATA BUS SIZE: 32BIT */
778MX6_MMDC_P0_MDCTL, 0x82190000,
779
780/* Write commands to DDR */
781/* Load Mode Registers */
782/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
783/* MX6_MMDC_P0_MDSCR, 0x04408032, */
784MX6_MMDC_P0_MDSCR, 0x04008032,
785MX6_MMDC_P0_MDSCR, 0x00008033,
786MX6_MMDC_P0_MDSCR, 0x00048031,
787MX6_MMDC_P0_MDSCR, 0x13208030,
788/* ZQ calibration */
789MX6_MMDC_P0_MDSCR, 0x04008040,
790
791MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
792MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
793MX6_MMDC_P0_MDREF, 0x00005800,
794
795MX6_MMDC_P0_MPODTCTRL, 0x00000000,
796MX6_MMDC_P1_MPODTCTRL, 0x00000000,
797
798MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
799MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
800MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
801MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
802
803MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
804MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
805MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
806MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
807
808MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
809MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
810MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
811MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
812
813MX6_MMDC_P0_MPMUR0, 0x00000800,
814MX6_MMDC_P1_MPMUR0, 0x00000800,
815MX6_MMDC_P0_MDSCR, 0x00000000,
816MX6_MMDC_P0_MAPSR, 0x00011006,
817};
818
819static int mx6dl_dcd_table[] = {
820/* ddr-setup.cfg */
821
822MX6_IOM_DRAM_SDQS0, 0x00000030,
823MX6_IOM_DRAM_SDQS1, 0x00000030,
824MX6_IOM_DRAM_SDQS2, 0x00000030,
825MX6_IOM_DRAM_SDQS3, 0x00000030,
826MX6_IOM_DRAM_SDQS4, 0x00000030,
827MX6_IOM_DRAM_SDQS5, 0x00000030,
828MX6_IOM_DRAM_SDQS6, 0x00000030,
829MX6_IOM_DRAM_SDQS7, 0x00000030,
830
831MX6_IOM_GRP_B0DS, 0x00000030,
832MX6_IOM_GRP_B1DS, 0x00000030,
833MX6_IOM_GRP_B2DS, 0x00000030,
834MX6_IOM_GRP_B3DS, 0x00000030,
835MX6_IOM_GRP_B4DS, 0x00000030,
836MX6_IOM_GRP_B5DS, 0x00000030,
837MX6_IOM_GRP_B6DS, 0x00000030,
838MX6_IOM_GRP_B7DS, 0x00000030,
839MX6_IOM_GRP_ADDDS, 0x00000030,
840/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
841MX6_IOM_GRP_CTLDS, 0x00000030,
842
843MX6_IOM_DRAM_DQM0, 0x00020030,
844MX6_IOM_DRAM_DQM1, 0x00020030,
845MX6_IOM_DRAM_DQM2, 0x00020030,
846MX6_IOM_DRAM_DQM3, 0x00020030,
847MX6_IOM_DRAM_DQM4, 0x00020030,
848MX6_IOM_DRAM_DQM5, 0x00020030,
849MX6_IOM_DRAM_DQM6, 0x00020030,
850MX6_IOM_DRAM_DQM7, 0x00020030,
851
852MX6_IOM_DRAM_CAS, 0x00020030,
853MX6_IOM_DRAM_RAS, 0x00020030,
854MX6_IOM_DRAM_SDCLK_0, 0x00020030,
855MX6_IOM_DRAM_SDCLK_1, 0x00020030,
856
857MX6_IOM_DRAM_RESET, 0x00020030,
858MX6_IOM_DRAM_SDCKE0, 0x00003000,
859MX6_IOM_DRAM_SDCKE1, 0x00003000,
860
861MX6_IOM_DRAM_SDODT0, 0x00003030,
862MX6_IOM_DRAM_SDODT1, 0x00003030,
863
864/* (differential input) */
865MX6_IOM_DDRMODE_CTL, 0x00020000,
866/* (differential input) */
867MX6_IOM_GRP_DDRMODE, 0x00020000,
868/* disable ddr pullups */
869MX6_IOM_GRP_DDRPKE, 0x00000000,
870MX6_IOM_DRAM_SDBA2, 0x00000000,
871/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
872MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
873
874/* Read data DQ Byte0-3 delay */
875MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
876MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
877MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
878MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
879MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
880MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
881MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
882MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
883
884/*
885 * MDMISC mirroring interleaved (row/bank/col)
886 */
44103cf3 887MX6_MMDC_P0_MDMISC, 0x000b17c0,
a02d517b
MK		 888
889/*
890 * MDSCR con_req
891 */
892MX6_MMDC_P0_MDSCR, 0x00008000,
893
894
895/* 800mhz_2x64mx16.cfg */
896
897MX6_MMDC_P0_MDPDC, 0x0002002D,
898MX6_MMDC_P0_MDCFG0, 0x2C305503,
899MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
900MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
901MX6_MMDC_P0_MDRWD, 0x000026D2,
902MX6_MMDC_P0_MDOR, 0x00301023,
903MX6_MMDC_P0_MDOTC, 0x00333030,
904MX6_MMDC_P0_MDPDC, 0x0002556D,
905/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
906MX6_MMDC_P0_MDASP, 0x00000017,
907/* DDR3 DATA BUS SIZE: 64BIT */
908MX6_MMDC_P0_MDCTL, 0x821A0000,
909/* DDR3 DATA BUS SIZE: 32BIT */
910/* MX6_MMDC_P0_MDCTL, 0x82190000, */
911
912/* Write commands to DDR */
913/* Load Mode Registers */
914/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
915/* MX6_MMDC_P0_MDSCR, 0x04408032, */
916MX6_MMDC_P0_MDSCR, 0x04008032,
917MX6_MMDC_P0_MDSCR, 0x00008033,
918MX6_MMDC_P0_MDSCR, 0x00048031,
919MX6_MMDC_P0_MDSCR, 0x13208030,
920/* ZQ calibration */
921MX6_MMDC_P0_MDSCR, 0x04008040,
922
923MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
924MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
925MX6_MMDC_P0_MDREF, 0x00005800,
926
927MX6_MMDC_P0_MPODTCTRL, 0x00000000,
928MX6_MMDC_P1_MPODTCTRL, 0x00000000,
929
930MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
931MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
932MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
933MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
934
935MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
936MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
937MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
938MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
939
940MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
941MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
942MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
943MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
944
945MX6_MMDC_P0_MPMUR0, 0x00000800,
946MX6_MMDC_P1_MPMUR0, 0x00000800,
947MX6_MMDC_P0_MDSCR, 0x00000000,
948MX6_MMDC_P0_MAPSR, 0x00011006,
949};
950
951static void ccgr_init(void)
952{
953 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
954
955 writel(0x00C03F3F, &ccm->CCGR0);
956 writel(0x0030FC03, &ccm->CCGR1);
957 writel(0x0FFFFFF3, &ccm->CCGR2);
958 writel(0x3FF0300F, &ccm->CCGR3);
959 writel(0x00FFF300, &ccm->CCGR4);
960 writel(0x0F0000F3, &ccm->CCGR5);
961 writel(0x000003FF, &ccm->CCGR6);
962
963/*
964 * Setup CCM_CCOSR register as follows:
965 *
d4cd19de
FD		 966 * clko2_en = 1 --> CKO2 enabled
967 * clko2_div = 000 --> divide by 1
968 * clko2_sel = 01110 --> osc_clk (24MHz)
a02d517b 969 *
d4cd19de
FD		 970 * clk_out_sel = 1 --> Output CKO2 to CKO1
971 *
972 * This sets both CLKO2/CLKO1 output to 24MHz,
973 * CLKO1 configuration not relevant because of clk_out_sel
974 * (CLKO1 set to default)
a02d517b 975 */
d4cd19de 976 writel(0x010E0101, &ccm->ccosr);
a02d517b
MK		 977}
978
a02d517b
MK		 979static void ddr_init(int *table, int size)
980{
981 int i;
982
983 for (i = 0; i < size / 2 ; i++)
984 writel(table[2 * i + 1], table[2 * i]);
985}
986
1194d171
FD		 987/* Perform DDR DRAM calibration */
988static void spl_dram_perform_cal(u8 dsize)
989{
990#ifdef CONFIG_MX6_DDRCAL
991 int err;
992 struct mx6_ddr_sysinfo ddr_sysinfo = {
993 .dsize = dsize,
994 };
995
996 err = mmdc_do_write_level_calibration(&ddr_sysinfo);
997 if (err)
998 printf("error %d from write level calibration\n", err);
999 err = mmdc_do_dqs_calibration(&ddr_sysinfo);
1000 if (err)
1001 printf("error %d from dqs calibration\n", err);
1002#endif
1003}
1004
a02d517b
MK		 1005static void spl_dram_init(void)
1006{
1007 int minc, maxc;
1194d171 1008 u8 dsize = 2;
a02d517b
MK		 1009
1010 switch (get_cpu_temp_grade(&minc, &maxc)) {
1011 case TEMP_COMMERCIAL:
1012 case TEMP_EXTCOMMERCIAL:
1013 if (is_cpu_type(MXC_CPU_MX6DL)) {
1014 puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n");
1015 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1016 } else {
1017 puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
1194d171 1018 dsize = 1;
a02d517b
MK		 1019 ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1020 }
1021 break;
1022 case TEMP_INDUSTRIAL:
1023 case TEMP_AUTOMOTIVE:
1024 default:
1025 if (is_cpu_type(MXC_CPU_MX6DL)) {
2910c0a1 1026 puts("Industrial temperature grade DDR3 timings, 64bit bus width.\n");
a02d517b
MK		 1027 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1028 } else {
1029 puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
1194d171 1030 dsize = 1;
a02d517b
MK		 1031 ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1032 }
1033 break;
1034 };
1035 udelay(100);
1194d171 1036 spl_dram_perform_cal(dsize);
a02d517b
MK		 1037}
1038
82029bf5
GS		 1039static iomux_v3_cfg_t const gpio_reset_pad[] = {
1040 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL) |
1041 MUX_MODE_SION
1042#define GPIO_NRESET IMX_GPIO_NR(6, 27)
1043};
1044
1045#define IMX_RESET_CAUSE_POR 0x00011
1046static void nreset_out(void)
1047{
1048 int reset_cause = get_imx_reset_cause();
1049
1050 if (reset_cause != IMX_RESET_CAUSE_POR) {
1051 imx_iomux_v3_setup_multiple_pads(gpio_reset_pad,
1052 ARRAY_SIZE(gpio_reset_pad));
1053 gpio_direction_output(GPIO_NRESET, 1);
1054 udelay(100);
1055 gpio_direction_output(GPIO_NRESET, 0);
1056 }
1057}
1058
a02d517b
MK		 1059void board_init_f(ulong dummy)
1060{
1061 /* setup AIPS and disable watchdog */
1062 arch_cpu_init();
1063
1064 ccgr_init();
1065 gpr_init();
1066
6eea69bd 1067 /* iomux */
a02d517b
MK		 1068 board_early_init_f();
1069
1070 /* setup GP timer */
1071 timer_init();
1072
1073 /* UART clocks enabled and gd valid - init serial console */
1074 preloader_console_init();
1075
1076 /* Make sure we use dte mode */
1077 setup_dtemode_uart();
1078
1079 /* DDR initialization */
1080 spl_dram_init();
1081
1082 /* Clear the BSS. */
1083 memset(__bss_start, 0, __bss_end - __bss_start);
1084
82029bf5
GS		 1085 /* Assert nReset_Out */
1086 nreset_out();
1087
a02d517b
MK		 1088 /* load/boot image from boot device */
1089 board_init_r(NULL, 0);
1090}
1091
87421ab6
ML		 1092#ifdef CONFIG_SPL_LOAD_FIT
1093int board_fit_config_name_match(const char *name)
1094{
1095 if (!strcmp(name, "imx6-colibri"))
1096 return 0;
1097
1098 return -1;
1099}
1100#endif
1101
35b65dd8 1102void reset_cpu(void)
a02d517b
MK		 1103{
1104}
1105
e7cf5349 1106#endif /* CONFIG_SPL_BUILD */
a02d517b 1107
8a8d24bd 1108static struct mxc_serial_plat mxc_serial_plat = {
a02d517b
MK		 1109 .reg = (struct mxc_uart *)UART1_BASE,
1110 .use_dte = true,
1111};
1112
20e442ab 1113U_BOOT_DRVINFO(mxc_serial) = {
a02d517b 1114 .name = "serial_mxc",
caa4daa2 1115 .plat = &mxc_serial_plat,
a02d517b 1116};
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