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6c7a1408 WD |
1 | /* |
2 | * (C) Copyright 2003-2004 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * (C) Copyright 2004 | |
6 | * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #include <common.h> | |
28 | #include <mpc5xxx.h> | |
29 | #include <pci.h> | |
19403633 | 30 | #include <netdev.h> |
6c7a1408 WD |
31 | |
32 | #include "sdram.h" | |
33 | ||
34 | #if CONFIG_TOTAL5200_REV==2 | |
35 | #include "mt48lc32m16a2-75.h" | |
36 | #else | |
37 | #include "mt48lc16m16a2-75.h" | |
38 | #endif | |
39 | ||
9973e3c6 | 40 | phys_size_t initdram (int board_type) |
6c7a1408 WD |
41 | { |
42 | sdram_conf_t sdram_conf; | |
43 | ||
44 | sdram_conf.ddr = SDRAM_DDR; | |
45 | sdram_conf.mode = SDRAM_MODE; | |
46 | sdram_conf.emode = 0; | |
47 | sdram_conf.control = SDRAM_CONTROL; | |
48 | sdram_conf.config1 = SDRAM_CONFIG1; | |
49 | sdram_conf.config2 = SDRAM_CONFIG2; | |
50 | #if defined(CONFIG_MPC5200) | |
51 | sdram_conf.tapdelay = 0; | |
52 | #endif | |
53 | #if defined(CONFIG_MGT5100) | |
54 | sdram_conf.addrsel = SDRAM_ADDRSEL; | |
55 | #endif | |
56 | return mpc5xxx_sdram_init (&sdram_conf); | |
57 | } | |
58 | ||
59 | int checkboard (void) | |
60 | { | |
61 | #if defined(CONFIG_MPC5200) | |
62 | #if CONFIG_TOTAL5200_REV==2 | |
63 | puts ("Board: Total5200 Rev.2 "); | |
64 | #else | |
65 | puts ("Board: Total5200 "); | |
66 | #endif | |
67 | #elif defined(CONFIG_MGT5100) | |
68 | puts ("Board: Total5100 "); | |
69 | #endif | |
70 | ||
9b55a253 WD |
71 | /* |
72 | * Retrieve FPGA Revision. | |
73 | */ | |
6d0f6bcf | 74 | printf ("(FPGA %08lX)\n", *(vu_long *) (CONFIG_SYS_FPGA_BASE + 0x400)); |
6c7a1408 | 75 | |
9b55a253 WD |
76 | /* |
77 | * Take all peripherals in power-up mode. | |
78 | */ | |
6c7a1408 | 79 | #if CONFIG_TOTAL5200_REV==2 |
6d0f6bcf | 80 | *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x46) = 0x70; |
6c7a1408 | 81 | #else |
6d0f6bcf | 82 | *(vu_long *) (CONFIG_SYS_CPLD_BASE + 0x400) = 0x70; |
6c7a1408 WD |
83 | #endif |
84 | ||
85 | return 0; | |
86 | } | |
87 | ||
88 | #if defined(CONFIG_MGT5100) | |
89 | int board_early_init_r(void) | |
90 | { | |
91 | /* | |
92 | * Now, when we are in RAM, enable CS0 | |
93 | * because CS_BOOT cannot be written. | |
94 | */ | |
95 | *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ | |
96 | *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ | |
97 | ||
98 | return 0; | |
99 | } | |
100 | #endif | |
101 | ||
102 | #ifdef CONFIG_PCI | |
103 | static struct pci_controller hose; | |
104 | ||
105 | extern void pci_mpc5xxx_init(struct pci_controller *); | |
106 | ||
107 | void pci_init_board(void) | |
108 | { | |
109 | pci_mpc5xxx_init(&hose); | |
110 | } | |
111 | #endif | |
112 | ||
d39b5741 | 113 | #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) |
6c7a1408 WD |
114 | |
115 | /* IRDA_1 aka PSC6_3 (pin C13) */ | |
116 | #define GPIO_IRDA_1 0x20000000UL | |
117 | ||
118 | void init_ide_reset (void) | |
119 | { | |
120 | debug ("init_ide_reset\n"); | |
121 | ||
53677ef1 | 122 | /* Configure IRDA_1 (PSC6_3) as GPIO output for ATA reset */ |
6c7a1408 WD |
123 | *(vu_long *) MPC5XXX_GPIO_ENABLE |= GPIO_IRDA_1; |
124 | *(vu_long *) MPC5XXX_GPIO_DIR |= GPIO_IRDA_1; | |
125 | } | |
126 | ||
127 | void ide_set_reset (int idereset) | |
128 | { | |
129 | debug ("ide_reset(%d)\n", idereset); | |
130 | ||
131 | if (idereset) { | |
132 | *(vu_long *) MPC5XXX_GPIO_DATA_O &= ~GPIO_IRDA_1; | |
133 | } else { | |
134 | *(vu_long *) MPC5XXX_GPIO_DATA_O |= GPIO_IRDA_1; | |
135 | } | |
136 | } | |
d39b5741 | 137 | #endif |
81050926 WD |
138 | |
139 | #ifdef CONFIG_VIDEO_SED13806 | |
140 | #include <sed13806.h> | |
141 | ||
142 | #define DISPLAY_WIDTH 640 | |
143 | #define DISPLAY_HEIGHT 480 | |
144 | ||
145 | #ifdef CONFIG_VIDEO_SED13806_8BPP | |
146 | #error CONFIG_VIDEO_SED13806_8BPP not supported. | |
147 | #endif /* CONFIG_VIDEO_SED13806_8BPP */ | |
148 | ||
149 | #ifdef CONFIG_VIDEO_SED13806_16BPP | |
150 | static const S1D_REGS init_regs [] = | |
151 | { | |
152 | {0x0001,0x00}, /* Miscellaneous Register */ | |
153 | {0x01FC,0x00}, /* Display Mode Register */ | |
154 | {0x0004,0x00}, /* General IO Pins Configuration Register 0 */ | |
155 | {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ | |
156 | {0x0008,0x00}, /* General IO Pins Control Register 0 */ | |
157 | {0x0009,0x00}, /* General IO Pins Control Register 1 */ | |
158 | {0x0010,0x02}, /* Memory Clock Configuration Register */ | |
159 | {0x0014,0x02}, /* LCD Pixel Clock Configuration Register */ | |
160 | {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ | |
161 | {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ | |
162 | {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ | |
163 | {0x0021,0x03}, /* DRAM Refresh Rate Register */ | |
164 | {0x002A,0x00}, /* DRAM Timings Control Register 0 */ | |
165 | {0x002B,0x01}, /* DRAM Timings Control Register 1 */ | |
166 | {0x0020,0x80}, /* Memory Configuration Register */ | |
167 | {0x0030,0x25}, /* Panel Type Register */ | |
168 | {0x0031,0x00}, /* MOD Rate Register */ | |
169 | {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ | |
170 | {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ | |
171 | {0x0035,0x01}, /* TFT FPLINE Start Position Register */ | |
172 | {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ | |
173 | {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ | |
174 | {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ | |
175 | {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ | |
176 | {0x003B,0x0A}, /* TFT FPFRAME Start Position Register */ | |
177 | {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ | |
178 | {0x0040,0x05}, /* LCD Display Mode Register */ | |
179 | {0x0041,0x00}, /* LCD Miscellaneous Register */ | |
180 | {0x0042,0x00}, /* LCD Display Start Address Register 0 */ | |
181 | {0x0043,0x00}, /* LCD Display Start Address Register 1 */ | |
182 | {0x0044,0x00}, /* LCD Display Start Address Register 2 */ | |
183 | {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */ | |
184 | {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ | |
185 | {0x0048,0x00}, /* LCD Pixel Panning Register */ | |
186 | {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ | |
187 | {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ | |
188 | {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ | |
189 | {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ | |
190 | {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ | |
191 | {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ | |
192 | {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ | |
193 | {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ | |
194 | {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ | |
195 | {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ | |
196 | {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ | |
197 | {0x005B,0x10}, /* TV Output Control Register */ | |
198 | {0x0060,0x05}, /* CRT/TV Display Mode Register */ | |
199 | {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ | |
200 | {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ | |
201 | {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ | |
202 | {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */ | |
203 | {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */ | |
204 | {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ | |
205 | {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ | |
206 | {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ | |
207 | {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ | |
208 | {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ | |
209 | {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ | |
210 | {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ | |
211 | {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ | |
212 | {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ | |
213 | {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ | |
214 | {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ | |
215 | {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ | |
216 | {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ | |
217 | {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ | |
218 | {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ | |
219 | {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ | |
220 | {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ | |
221 | {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ | |
222 | {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ | |
223 | {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ | |
224 | {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ | |
225 | {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ | |
226 | {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ | |
227 | {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ | |
228 | {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ | |
229 | {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ | |
230 | {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ | |
231 | {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ | |
232 | {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ | |
233 | {0x0100,0x00}, /* BitBlt Control Register 0 */ | |
234 | {0x0101,0x00}, /* BitBlt Control Register 1 */ | |
235 | {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ | |
236 | {0x0103,0x00}, /* BitBlt Operation Register */ | |
237 | {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ | |
238 | {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ | |
239 | {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ | |
240 | {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ | |
241 | {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ | |
242 | {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ | |
243 | {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ | |
244 | {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ | |
245 | {0x0110,0x00}, /* BitBlt Width Register 0 */ | |
246 | {0x0111,0x00}, /* BitBlt Width Register 1 */ | |
247 | {0x0112,0x00}, /* BitBlt Height Register 0 */ | |
248 | {0x0113,0x00}, /* BitBlt Height Register 1 */ | |
249 | {0x0114,0x00}, /* BitBlt Background Color Register 0 */ | |
250 | {0x0115,0x00}, /* BitBlt Background Color Register 1 */ | |
251 | {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ | |
252 | {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ | |
253 | {0x01E0,0x00}, /* Look-Up Table Mode Register */ | |
254 | {0x01E2,0x00}, /* Look-Up Table Address Register */ | |
255 | {0x01E4,0x00}, /* Look-Up Table Data Register */ | |
256 | {0x01F0,0x00}, /* Power Save Configuration Register */ | |
257 | {0x01F1,0x00}, /* Power Save Status Register */ | |
258 | {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ | |
259 | {0x01FC,0x01}, /* Display Mode Register */ | |
260 | {0, 0} | |
261 | }; | |
262 | #endif /* CONFIG_VIDEO_SED13806_16BPP */ | |
263 | ||
264 | #ifdef CONFIG_CONSOLE_EXTRA_INFO | |
265 | /* Return text to be printed besides the logo. */ | |
266 | void video_get_info_str (int line_number, char *info) | |
267 | { | |
268 | if (line_number == 1) { | |
281e00a3 | 269 | #ifdef CONFIG_MGT5100 |
81050926 WD |
270 | strcpy (info, " Total5100"); |
271 | #elif CONFIG_TOTAL5200_REV==1 | |
272 | strcpy (info, " Total5200"); | |
273 | #elif CONFIG_TOTAL5200_REV==2 | |
274 | strcpy (info, " Total5200 Rev.2"); | |
275 | #else | |
276 | #error CONFIG_TOTAL5200_REV must be 1 or 2. | |
277 | #endif | |
278 | } else { | |
279 | info [0] = '\0'; | |
280 | } | |
281 | } | |
282 | #endif | |
283 | ||
284 | /* Returns SED13806 base address. First thing called in the driver. */ | |
285 | unsigned int board_video_init (void) | |
286 | { | |
6d0f6bcf | 287 | return CONFIG_SYS_LCD_BASE; |
81050926 WD |
288 | } |
289 | ||
290 | /* Called after initializing the SED13806 and before clearing the screen. */ | |
291 | void board_validate_screen (unsigned int base) | |
292 | { | |
293 | } | |
294 | ||
295 | /* Return a pointer to the initialization sequence. */ | |
296 | const S1D_REGS *board_get_regs (void) | |
297 | { | |
298 | return init_regs; | |
299 | } | |
300 | ||
301 | int board_get_width (void) | |
302 | { | |
303 | return DISPLAY_WIDTH; | |
304 | } | |
305 | ||
306 | int board_get_height (void) | |
307 | { | |
308 | return DISPLAY_HEIGHT; | |
309 | } | |
310 | ||
311 | #endif /* CONFIG_VIDEO_SED13806 */ | |
19403633 BW |
312 | |
313 | int board_eth_init(bd_t *bis) | |
314 | { | |
e1d7480b | 315 | cpu_eth_init(bis); /* Built in FEC comes first */ |
19403633 BW |
316 | return pci_eth_init(bis); |
317 | } |