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56523f12 | 1 | /* |
45a212c4 | 2 | * (C) Copyright 2003-2006 |
56523f12 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * (C) Copyright 2004 | |
6 | * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. | |
7 | * | |
45a212c4 | 8 | * (C) Copyright 2004-2006 |
56523f12 WD |
9 | * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de |
10 | * | |
11 | * See file CREDITS for list of people who contributed to this | |
12 | * project. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or | |
15 | * modify it under the terms of the GNU General Public License as | |
16 | * published by the Free Software Foundation; either version 2 of | |
17 | * the License, or (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
81050926 | 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
56523f12 WD |
22 | * GNU General Public License for more details. |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
27 | * MA 02111-1307 USA | |
28 | */ | |
29 | ||
30 | #include <common.h> | |
31 | #include <mpc5xxx.h> | |
32 | #include <pci.h> | |
45a212c4 | 33 | #include <asm/processor.h> |
cf2817a8 | 34 | #include <libfdt.h> |
19403633 | 35 | #include <netdev.h> |
8f8416fa | 36 | |
8f0b7cbe WD |
37 | #ifdef CONFIG_VIDEO_SM501 |
38 | #include <sm501.h> | |
39 | #endif | |
40 | ||
56523f12 WD |
41 | #if defined(CONFIG_MPC5200_DDR) |
42 | #include "mt46v16m16-75.h" | |
43 | #else | |
44 | #include "mt48lc16m16a2-75.h" | |
45 | #endif | |
8f0b7cbe | 46 | |
c313b2c6 MK |
47 | #ifdef CONFIG_OF_LIBFDT |
48 | #include <fdt_support.h> | |
49 | #endif /* CONFIG_OF_LIBFDT */ | |
50 | ||
1218abf1 WD |
51 | DECLARE_GLOBAL_DATA_PTR; |
52 | ||
7e6bf358 WD |
53 | #ifdef CONFIG_PS2MULT |
54 | void ps2mult_early_init(void); | |
55 | #endif | |
56523f12 | 56 | |
6d0f6bcf | 57 | #ifndef CONFIG_SYS_RAMBOOT |
56523f12 WD |
58 | static void sdram_start (int hi_addr) |
59 | { | |
60 | long hi_addr_bit = hi_addr ? 0x01000000 : 0; | |
61 | ||
62 | /* unlock mode register */ | |
63 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | | |
64 | hi_addr_bit; | |
65 | __asm__ volatile ("sync"); | |
66 | ||
67 | /* precharge all banks */ | |
68 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | | |
69 | hi_addr_bit; | |
70 | __asm__ volatile ("sync"); | |
71 | ||
72 | #if SDRAM_DDR | |
73 | /* set mode register: extended mode */ | |
74 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; | |
75 | __asm__ volatile ("sync"); | |
76 | ||
77 | /* set mode register: reset DLL */ | |
78 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; | |
79 | __asm__ volatile ("sync"); | |
80 | #endif | |
81 | ||
82 | /* precharge all banks */ | |
83 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | | |
84 | hi_addr_bit; | |
85 | __asm__ volatile ("sync"); | |
86 | ||
87 | /* auto refresh */ | |
88 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | | |
89 | hi_addr_bit; | |
90 | __asm__ volatile ("sync"); | |
91 | ||
92 | /* set mode register */ | |
93 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; | |
94 | __asm__ volatile ("sync"); | |
95 | ||
96 | /* normal operation */ | |
97 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; | |
98 | __asm__ volatile ("sync"); | |
99 | } | |
100 | #endif | |
101 | ||
102 | /* | |
103 | * ATTENTION: Although partially referenced initdram does NOT make real use | |
6d0f6bcf | 104 | * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE |
81050926 | 105 | * is something else than 0x00000000. |
56523f12 WD |
106 | */ |
107 | ||
9973e3c6 | 108 | phys_size_t initdram (int board_type) |
56523f12 WD |
109 | { |
110 | ulong dramsize = 0; | |
111 | ulong dramsize2 = 0; | |
45a212c4 WD |
112 | uint svr, pvr; |
113 | ||
6d0f6bcf | 114 | #ifndef CONFIG_SYS_RAMBOOT |
56523f12 WD |
115 | ulong test1, test2; |
116 | ||
117 | /* setup SDRAM chip selects */ | |
118 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ | |
119 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */ | |
120 | __asm__ volatile ("sync"); | |
121 | ||
122 | /* setup config registers */ | |
123 | *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; | |
124 | *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; | |
125 | __asm__ volatile ("sync"); | |
126 | ||
127 | #if SDRAM_DDR | |
128 | /* set tap delay */ | |
129 | *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; | |
130 | __asm__ volatile ("sync"); | |
131 | #endif | |
132 | ||
133 | /* find RAM size using SDRAM CS0 only */ | |
134 | sdram_start(0); | |
6d0f6bcf | 135 | test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); |
56523f12 | 136 | sdram_start(1); |
6d0f6bcf | 137 | test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); |
56523f12 WD |
138 | if (test1 > test2) { |
139 | sdram_start(0); | |
140 | dramsize = test1; | |
141 | } else { | |
142 | dramsize = test2; | |
143 | } | |
144 | ||
145 | /* memory smaller than 1MB is impossible */ | |
146 | if (dramsize < (1 << 20)) { | |
147 | dramsize = 0; | |
148 | } | |
149 | ||
150 | /* set SDRAM CS0 size according to the amount of RAM found */ | |
151 | if (dramsize > 0) { | |
152 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + | |
153 | __builtin_ffs(dramsize >> 20) - 1; | |
154 | } else { | |
155 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ | |
156 | } | |
157 | ||
158 | /* let SDRAM CS1 start right after CS0 */ | |
159 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */ | |
160 | ||
161 | /* find RAM size using SDRAM CS1 only */ | |
f3a329ac MK |
162 | if (!dramsize) |
163 | sdram_start(0); | |
6d0f6bcf | 164 | test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000); |
f3a329ac MK |
165 | if (!dramsize) { |
166 | sdram_start(1); | |
6d0f6bcf | 167 | test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000); |
f3a329ac | 168 | } |
56523f12 WD |
169 | if (test1 > test2) { |
170 | sdram_start(0); | |
171 | dramsize2 = test1; | |
172 | } else { | |
173 | dramsize2 = test2; | |
174 | } | |
175 | ||
176 | /* memory smaller than 1MB is impossible */ | |
177 | if (dramsize2 < (1 << 20)) { | |
178 | dramsize2 = 0; | |
179 | } | |
180 | ||
181 | /* set SDRAM CS1 size according to the amount of RAM found */ | |
182 | if (dramsize2 > 0) { | |
183 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize | |
184 | | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); | |
185 | } else { | |
186 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ | |
187 | } | |
188 | ||
6d0f6bcf | 189 | #else /* CONFIG_SYS_RAMBOOT */ |
56523f12 WD |
190 | |
191 | /* retrieve size of memory connected to SDRAM CS0 */ | |
192 | dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; | |
193 | if (dramsize >= 0x13) { | |
194 | dramsize = (1 << (dramsize - 0x13)) << 20; | |
195 | } else { | |
196 | dramsize = 0; | |
197 | } | |
198 | ||
199 | /* retrieve size of memory connected to SDRAM CS1 */ | |
200 | dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; | |
201 | if (dramsize2 >= 0x13) { | |
202 | dramsize2 = (1 << (dramsize2 - 0x13)) << 20; | |
203 | } else { | |
204 | dramsize2 = 0; | |
205 | } | |
6d0f6bcf | 206 | #endif /* CONFIG_SYS_RAMBOOT */ |
56523f12 | 207 | |
45a212c4 WD |
208 | /* |
209 | * On MPC5200B we need to set the special configuration delay in the | |
210 | * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM | |
211 | * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: | |
212 | * | |
213 | * "The SDelay should be written to a value of 0x00000004. It is | |
214 | * required to account for changes caused by normal wafer processing | |
215 | * parameters." | |
216 | */ | |
217 | svr = get_svr(); | |
218 | pvr = get_pvr(); | |
219 | if ((SVR_MJREV(svr) >= 2) && | |
220 | (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { | |
221 | ||
222 | *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; | |
223 | __asm__ volatile ("sync"); | |
224 | } | |
225 | ||
226 | #if defined(CONFIG_TQM5200_B) | |
227 | return dramsize + dramsize2; | |
228 | #else | |
56523f12 | 229 | return dramsize; |
45a212c4 | 230 | #endif /* CONFIG_TQM5200_B */ |
56523f12 WD |
231 | } |
232 | ||
56523f12 WD |
233 | int checkboard (void) |
234 | { | |
5078cce8 | 235 | #if defined(CONFIG_AEVFIFO) |
8f79e4c2 WD |
236 | puts ("Board: AEVFIFO\n"); |
237 | return 0; | |
238 | #endif | |
5078cce8 WD |
239 | |
240 | #if defined(CONFIG_TQM5200S) | |
241 | # define MODULE_NAME "TQM5200S" | |
45a212c4 | 242 | #else |
5078cce8 | 243 | # define MODULE_NAME "TQM5200" |
7e6bf358 | 244 | #endif |
5078cce8 WD |
245 | |
246 | #if defined(CONFIG_STK52XX) | |
247 | # define CARRIER_NAME "STK52xx" | |
248 | #elif defined(CONFIG_TB5200) | |
249 | # define CARRIER_NAME "TB5200" | |
135ae006 | 250 | #elif defined(CONFIG_CAM5200) |
78d620eb | 251 | # define CARRIER_NAME "CAM5200" |
6d3bc9b8 MB |
252 | #elif defined(CONFIG_FO300) |
253 | # define CARRIER_NAME "FO300" | |
5078cce8 | 254 | #else |
5196a7a0 | 255 | # error "UNKNOWN" |
b87dfd28 | 256 | #endif |
7e6bf358 | 257 | |
5078cce8 WD |
258 | puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n" |
259 | " on a " CARRIER_NAME " carrier board\n"); | |
260 | ||
56523f12 WD |
261 | return 0; |
262 | } | |
263 | ||
5078cce8 WD |
264 | #undef MODULE_NAME |
265 | #undef CARRIER_NAME | |
266 | ||
56523f12 WD |
267 | void flash_preinit(void) |
268 | { | |
269 | /* | |
270 | * Now, when we are in RAM, enable flash write | |
271 | * access for detection process. | |
272 | * Note that CS_BOOT cannot be cleared when | |
273 | * executing in flash. | |
274 | */ | |
56523f12 WD |
275 | *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ |
276 | } | |
277 | ||
278 | ||
279 | #ifdef CONFIG_PCI | |
280 | static struct pci_controller hose; | |
281 | ||
282 | extern void pci_mpc5xxx_init(struct pci_controller *); | |
283 | ||
284 | void pci_init_board(void) | |
285 | { | |
286 | pci_mpc5xxx_init(&hose); | |
287 | } | |
288 | #endif | |
289 | ||
d39b5741 | 290 | #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) |
56523f12 WD |
291 | |
292 | #if defined (CONFIG_MINIFAP) | |
293 | #define SM501_POWER_MODE0_GATE 0x00000040UL | |
294 | #define SM501_POWER_MODE1_GATE 0x00000048UL | |
295 | #define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL | |
296 | #define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL | |
297 | #define SM501_GPIO_DATA_HIGH 0x00010004UL | |
298 | #define SM501_GPIO_51 0x00080000UL | |
dae80f3c | 299 | #endif /* CONFIG MINIFAP */ |
56523f12 WD |
300 | |
301 | void init_ide_reset (void) | |
302 | { | |
303 | debug ("init_ide_reset\n"); | |
304 | ||
305 | #if defined (CONFIG_MINIFAP) | |
306 | /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */ | |
307 | ||
308 | /* enable GPIO control (in both power modes) */ | |
309 | *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |= | |
310 | POWER_MODE_GATE_GPIO_PWM_I2C; | |
311 | *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |= | |
312 | POWER_MODE_GATE_GPIO_PWM_I2C; | |
313 | /* configure GPIO51 as output */ | |
314 | *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= | |
315 | SM501_GPIO_51; | |
316 | #else | |
317 | /* Configure PSC1_4 as GPIO output for ATA reset */ | |
318 | *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; | |
319 | *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; | |
8f2a68a0 MK |
320 | |
321 | /* by default the ATA reset is de-asserted */ | |
322 | *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; | |
56523f12 WD |
323 | #endif |
324 | } | |
325 | ||
326 | void ide_set_reset (int idereset) | |
327 | { | |
328 | debug ("ide_reset(%d)\n", idereset); | |
329 | ||
330 | #if defined (CONFIG_MINIFAP) | |
331 | if (idereset) { | |
332 | *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= | |
333 | ~SM501_GPIO_51; | |
334 | } else { | |
335 | *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= | |
336 | SM501_GPIO_51; | |
337 | } | |
338 | #else | |
339 | if (idereset) { | |
dae80f3c | 340 | *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; |
56523f12 | 341 | } else { |
dae80f3c | 342 | *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; |
56523f12 WD |
343 | } |
344 | #endif | |
345 | } | |
d39b5741 | 346 | #endif |
56523f12 WD |
347 | |
348 | #ifdef CONFIG_POST | |
349 | /* | |
350 | * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3 | |
351 | * is left open, no keypress is detected. | |
352 | */ | |
353 | int post_hotkeys_pressed(void) | |
354 | { | |
1d92b2e5 | 355 | #ifdef CONFIG_STK52XX |
56523f12 WD |
356 | struct mpc5xxx_gpio *gpio; |
357 | ||
358 | gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO; | |
359 | ||
360 | /* | |
361 | * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in | |
362 | * CODEC or UART mode. Consumer IrDA should still be possible. | |
81050926 | 363 | */ |
56523f12 WD |
364 | gpio->port_config &= ~(0x07000000); |
365 | gpio->port_config |= 0x03000000; | |
366 | ||
367 | /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */ | |
368 | gpio->simple_gpioe |= 0x20000000; | |
369 | ||
370 | /* Configure GPIO_IRDA_1 as input */ | |
371 | gpio->simple_ddr &= ~(0x20000000); | |
372 | ||
373 | return ((gpio->simple_ival & 0x20000000) ? 0 : 1); | |
1d92b2e5 WD |
374 | #else |
375 | return 0; | |
376 | #endif | |
56523f12 WD |
377 | } |
378 | #endif | |
379 | ||
380 | #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) | |
381 | ||
382 | void post_word_store (ulong a) | |
383 | { | |
384 | volatile ulong *save_addr = | |
385 | (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); | |
386 | ||
387 | *save_addr = a; | |
388 | } | |
389 | ||
390 | ulong post_word_load (void) | |
391 | { | |
392 | volatile ulong *save_addr = | |
393 | (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); | |
394 | ||
395 | return *save_addr; | |
396 | } | |
56523f12 | 397 | #endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ |
7e6bf358 | 398 | |
7e6bf358 WD |
399 | #ifdef CONFIG_BOARD_EARLY_INIT_R |
400 | int board_early_init_r (void) | |
401 | { | |
6a40ef62 | 402 | |
409ecdc0 WD |
403 | extern int usb_cpu_init(void); |
404 | ||
245a362a | 405 | #ifdef CONFIG_PS2MULT |
7e6bf358 | 406 | ps2mult_early_init(); |
245a362a MB |
407 | #endif /* CONFIG_PS2MULT */ |
408 | ||
6d0f6bcf | 409 | #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) |
245a362a MB |
410 | /* Low level USB init, required for proper kernel operation */ |
411 | usb_cpu_init(); | |
412 | #endif | |
413 | ||
7e6bf358 WD |
414 | return (0); |
415 | } | |
416 | #endif | |
7e6bf358 | 417 | |
aeec782b WD |
418 | #ifdef CONFIG_FO300 |
419 | int silent_boot (void) | |
420 | { | |
421 | vu_long timer3_status; | |
422 | ||
423 | /* Configure GPT3 as GPIO input */ | |
424 | *(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004; | |
425 | ||
426 | /* Read in TIMER_3 pin status */ | |
427 | timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS; | |
428 | ||
429 | #ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED | |
430 | /* Force silent console mode if S1 switch | |
431 | * is in closed position (TIMER_3 pin status is LOW). */ | |
432 | if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0) | |
433 | return 1; | |
434 | #else | |
435 | /* Force silent console mode if S1 switch | |
436 | * is in open position (TIMER_3 pin status is HIGH). */ | |
437 | if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1) | |
438 | return 1; | |
439 | #endif | |
440 | ||
441 | return 0; | |
442 | } | |
443 | ||
444 | int board_early_init_f (void) | |
445 | { | |
aeec782b WD |
446 | if (silent_boot()) |
447 | gd->flags |= GD_FLG_SILENT; | |
448 | ||
449 | return 0; | |
450 | } | |
451 | #endif /* CONFIG_FO300 */ | |
452 | ||
7e6bf358 WD |
453 | int last_stage_init (void) |
454 | { | |
455 | /* | |
456 | * auto scan for really existing devices and re-set chip select | |
457 | * configuration. | |
458 | */ | |
459 | u16 save, tmp; | |
460 | int restore; | |
461 | ||
462 | /* | |
463 | * Check for SRAM and SRAM size | |
464 | */ | |
465 | ||
e8aa824e | 466 | /* save original SRAM content */ |
6d0f6bcf | 467 | save = *(volatile u16 *)CONFIG_SYS_CS2_START; |
7e6bf358 | 468 | restore = 1; |
efe2a4d5 | 469 | |
7e6bf358 | 470 | /* write test pattern to SRAM */ |
6d0f6bcf | 471 | *(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5; |
7e6bf358 WD |
472 | __asm__ volatile ("sync"); |
473 | /* | |
474 | * Put a different pattern on the data lines: otherwise they may float | |
475 | * long enough to read back what we wrote. | |
476 | */ | |
6d0f6bcf | 477 | tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; |
7e6bf358 WD |
478 | if (tmp == 0xA5A5) |
479 | puts ("!! possible error in SRAM detection\n"); | |
efe2a4d5 | 480 | |
6d0f6bcf | 481 | if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) { |
7e6bf358 WD |
482 | /* no SRAM at all, disable cs */ |
483 | *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18); | |
484 | *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF; | |
485 | *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF; | |
486 | restore = 0; | |
487 | __asm__ volatile ("sync"); | |
6d0f6bcf | 488 | } else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) { |
7e6bf358 | 489 | /* make sure that we access a mirrored address */ |
6d0f6bcf | 490 | *(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111; |
7e6bf358 | 491 | __asm__ volatile ("sync"); |
6d0f6bcf | 492 | if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) { |
7e6bf358 | 493 | /* SRAM size = 512 kByte */ |
6d0f6bcf | 494 | *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START, |
7e6bf358 WD |
495 | 0x80000); |
496 | __asm__ volatile ("sync"); | |
497 | puts ("SRAM: 512 kB\n"); | |
498 | } | |
499 | else | |
efe2a4d5 | 500 | puts ("!! possible error in SRAM detection\n"); |
e8aa824e | 501 | } else { |
efe2a4d5 | 502 | puts ("SRAM: 1 MB\n"); |
7e6bf358 WD |
503 | } |
504 | /* restore origianl SRAM content */ | |
505 | if (restore) { | |
6d0f6bcf | 506 | *(volatile u16 *)CONFIG_SYS_CS2_START = save; |
7e6bf358 WD |
507 | __asm__ volatile ("sync"); |
508 | } | |
efe2a4d5 | 509 | |
0fc0f91b | 510 | #ifndef CONFIG_TQM5200S /* The TQM5200S has no SM501 grafic controller */ |
efe2a4d5 | 511 | /* |
7e6bf358 WD |
512 | * Check for Grafic Controller |
513 | */ | |
514 | ||
515 | /* save origianl FB content */ | |
6d0f6bcf | 516 | save = *(volatile u16 *)CONFIG_SYS_CS1_START; |
7e6bf358 | 517 | restore = 1; |
efe2a4d5 | 518 | |
7e6bf358 | 519 | /* write test pattern to FB memory */ |
6d0f6bcf | 520 | *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5; |
7e6bf358 WD |
521 | __asm__ volatile ("sync"); |
522 | /* | |
523 | * Put a different pattern on the data lines: otherwise they may float | |
524 | * long enough to read back what we wrote. | |
525 | */ | |
6d0f6bcf | 526 | tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; |
7e6bf358 WD |
527 | if (tmp == 0xA5A5) |
528 | puts ("!! possible error in grafic controller detection\n"); | |
efe2a4d5 | 529 | |
6d0f6bcf | 530 | if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) { |
7e6bf358 WD |
531 | /* no grafic controller at all, disable cs */ |
532 | *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17); | |
533 | *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF; | |
534 | *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF; | |
535 | restore = 0; | |
536 | __asm__ volatile ("sync"); | |
e8aa824e | 537 | } else { |
efe2a4d5 | 538 | puts ("VGA: SMI501 (Voyager) with 8 MB\n"); |
7e6bf358 WD |
539 | } |
540 | /* restore origianl FB content */ | |
541 | if (restore) { | |
6d0f6bcf | 542 | *(volatile u16 *)CONFIG_SYS_CS1_START = save; |
7e6bf358 WD |
543 | __asm__ volatile ("sync"); |
544 | } | |
efe2a4d5 | 545 | |
aeec782b WD |
546 | #ifdef CONFIG_FO300 |
547 | if (silent_boot()) { | |
548 | setenv("bootdelay", "0"); | |
549 | disable_ctrlc(1); | |
550 | } | |
551 | #endif | |
409ecdc0 | 552 | #endif /* !CONFIG_TQM5200S */ |
aeec782b | 553 | |
7e6bf358 WD |
554 | return 0; |
555 | } | |
8f0b7cbe WD |
556 | |
557 | #ifdef CONFIG_VIDEO_SM501 | |
558 | ||
6d3bc9b8 MB |
559 | #ifdef CONFIG_FO300 |
560 | #define DISPLAY_WIDTH 800 | |
561 | #else | |
8f0b7cbe | 562 | #define DISPLAY_WIDTH 640 |
6d3bc9b8 | 563 | #endif |
8f0b7cbe WD |
564 | #define DISPLAY_HEIGHT 480 |
565 | ||
566 | #ifdef CONFIG_VIDEO_SM501_8BPP | |
567 | #error CONFIG_VIDEO_SM501_8BPP not supported. | |
568 | #endif /* CONFIG_VIDEO_SM501_8BPP */ | |
569 | ||
570 | #ifdef CONFIG_VIDEO_SM501_16BPP | |
571 | #error CONFIG_VIDEO_SM501_16BPP not supported. | |
572 | #endif /* CONFIG_VIDEO_SM501_16BPP */ | |
573 | #ifdef CONFIG_VIDEO_SM501_32BPP | |
574 | static const SMI_REGS init_regs [] = | |
575 | { | |
576 | #if 0 /* CRT only */ | |
577 | {0x00004, 0x0}, | |
578 | {0x00048, 0x00021807}, | |
579 | {0x0004C, 0x10090a01}, | |
580 | {0x00054, 0x1}, | |
581 | {0x00040, 0x00021807}, | |
582 | {0x00044, 0x10090a01}, | |
583 | {0x00054, 0x0}, | |
584 | {0x80200, 0x00010000}, | |
585 | {0x80204, 0x0}, | |
586 | {0x80208, 0x0A000A00}, | |
587 | {0x8020C, 0x02fa027f}, | |
588 | {0x80210, 0x004a028b}, | |
589 | {0x80214, 0x020c01df}, | |
590 | {0x80218, 0x000201e9}, | |
591 | {0x80200, 0x00013306}, | |
592 | #else /* panel + CRT */ | |
6d3bc9b8 MB |
593 | #ifdef CONFIG_FO300 |
594 | {0x00004, 0x0}, | |
595 | {0x00048, 0x00021807}, | |
596 | {0x0004C, 0x301a0a01}, | |
597 | {0x00054, 0x1}, | |
598 | {0x00040, 0x00021807}, | |
599 | {0x00044, 0x091a0a01}, | |
600 | {0x00054, 0x0}, | |
601 | {0x80000, 0x0f013106}, | |
602 | {0x80004, 0xc428bb17}, | |
603 | {0x8000C, 0x00000000}, | |
604 | {0x80010, 0x0C800C80}, | |
605 | {0x80014, 0x03200000}, | |
606 | {0x80018, 0x01e00000}, | |
607 | {0x8001C, 0x00000000}, | |
608 | {0x80020, 0x01e00320}, | |
609 | {0x80024, 0x042a031f}, | |
610 | {0x80028, 0x0086034a}, | |
611 | {0x8002C, 0x020c01df}, | |
612 | {0x80030, 0x000201ea}, | |
613 | {0x80200, 0x00010000}, | |
614 | #else | |
8f0b7cbe WD |
615 | {0x00004, 0x0}, |
616 | {0x00048, 0x00021807}, | |
617 | {0x0004C, 0x091a0a01}, | |
618 | {0x00054, 0x1}, | |
619 | {0x00040, 0x00021807}, | |
620 | {0x00044, 0x091a0a01}, | |
621 | {0x00054, 0x0}, | |
622 | {0x80000, 0x0f013106}, | |
623 | {0x80004, 0xc428bb17}, | |
624 | {0x8000C, 0x00000000}, | |
625 | {0x80010, 0x0a000a00}, | |
626 | {0x80014, 0x02800000}, | |
627 | {0x80018, 0x01e00000}, | |
628 | {0x8001C, 0x00000000}, | |
629 | {0x80020, 0x01e00280}, | |
630 | {0x80024, 0x02fa027f}, | |
631 | {0x80028, 0x004a028b}, | |
632 | {0x8002C, 0x020c01df}, | |
633 | {0x80030, 0x000201e9}, | |
634 | {0x80200, 0x00010000}, | |
6d3bc9b8 | 635 | #endif /* #ifdef CONFIG_FO300 */ |
8f0b7cbe WD |
636 | #endif |
637 | {0, 0} | |
638 | }; | |
639 | #endif /* CONFIG_VIDEO_SM501_32BPP */ | |
640 | ||
641 | #ifdef CONFIG_CONSOLE_EXTRA_INFO | |
642 | /* | |
643 | * Return text to be printed besides the logo. | |
644 | */ | |
645 | void video_get_info_str (int line_number, char *info) | |
646 | { | |
647 | if (line_number == 1) { | |
cd65a3dc | 648 | strcpy (info, " Board: TQM5200 (TQ-Components GmbH)"); |
6d3bc9b8 | 649 | #if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200) || defined(CONFIG_FO300) |
8f0b7cbe | 650 | } else if (line_number == 2) { |
b87dfd28 | 651 | #if defined (CONFIG_STK52XX) |
5078cce8 | 652 | strcpy (info, " on a STK52xx carrier board"); |
b87dfd28 WD |
653 | #endif |
654 | #if defined (CONFIG_TB5200) | |
5078cce8 | 655 | strcpy (info, " on a TB5200 carrier board"); |
b87dfd28 | 656 | #endif |
6d3bc9b8 MB |
657 | #if defined (CONFIG_FO300) |
658 | strcpy (info, " on a FO300 carrier board"); | |
659 | #endif | |
8f0b7cbe WD |
660 | #endif |
661 | } | |
662 | else { | |
663 | info [0] = '\0'; | |
664 | } | |
665 | } | |
666 | #endif | |
667 | ||
668 | /* | |
e8aa824e WD |
669 | * Returns SM501 register base address. First thing called in the |
670 | * driver. Checks if SM501 is physically present. | |
8f0b7cbe WD |
671 | */ |
672 | unsigned int board_video_init (void) | |
673 | { | |
e8aa824e WD |
674 | u16 save, tmp; |
675 | int restore, ret; | |
676 | ||
677 | /* | |
678 | * Check for Grafic Controller | |
679 | */ | |
680 | ||
681 | /* save origianl FB content */ | |
6d0f6bcf | 682 | save = *(volatile u16 *)CONFIG_SYS_CS1_START; |
e8aa824e WD |
683 | restore = 1; |
684 | ||
685 | /* write test pattern to FB memory */ | |
6d0f6bcf | 686 | *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5; |
e8aa824e WD |
687 | __asm__ volatile ("sync"); |
688 | /* | |
689 | * Put a different pattern on the data lines: otherwise they may float | |
690 | * long enough to read back what we wrote. | |
691 | */ | |
6d0f6bcf | 692 | tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; |
e8aa824e WD |
693 | if (tmp == 0xA5A5) |
694 | puts ("!! possible error in grafic controller detection\n"); | |
695 | ||
6d0f6bcf | 696 | if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) { |
e8aa824e WD |
697 | /* no grafic controller found */ |
698 | restore = 0; | |
699 | ret = 0; | |
700 | } else { | |
701 | ret = SM501_MMIO_BASE; | |
702 | } | |
703 | ||
704 | if (restore) { | |
6d0f6bcf | 705 | *(volatile u16 *)CONFIG_SYS_CS1_START = save; |
e8aa824e WD |
706 | __asm__ volatile ("sync"); |
707 | } | |
708 | return ret; | |
8f0b7cbe WD |
709 | } |
710 | ||
711 | /* | |
712 | * Returns SM501 framebuffer address | |
713 | */ | |
714 | unsigned int board_video_get_fb (void) | |
715 | { | |
716 | return SM501_FB_BASE; | |
717 | } | |
718 | ||
719 | /* | |
720 | * Called after initializing the SM501 and before clearing the screen. | |
721 | */ | |
722 | void board_validate_screen (unsigned int base) | |
723 | { | |
724 | } | |
725 | ||
726 | /* | |
727 | * Return a pointer to the initialization sequence. | |
728 | */ | |
729 | const SMI_REGS *board_get_regs (void) | |
730 | { | |
731 | return init_regs; | |
732 | } | |
733 | ||
734 | int board_get_width (void) | |
735 | { | |
736 | return DISPLAY_WIDTH; | |
737 | } | |
738 | ||
739 | int board_get_height (void) | |
740 | { | |
741 | return DISPLAY_HEIGHT; | |
742 | } | |
743 | ||
744 | #endif /* CONFIG_VIDEO_SM501 */ | |
8f8416fa | 745 | |
cf2817a8 | 746 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) |
8f8416fa BS |
747 | void ft_board_setup(void *blob, bd_t *bd) |
748 | { | |
749 | ft_cpu_setup(blob, bd); | |
44ceec25 | 750 | fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); |
8f8416fa | 751 | } |
cf2817a8 | 752 | #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ |
19403633 BW |
753 | |
754 | int board_eth_init(bd_t *bis) | |
755 | { | |
e1d7480b | 756 | cpu_eth_init(bis); /* Built in FEC comes first */ |
19403633 BW |
757 | return pci_eth_init(bis); |
758 | } |