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a6f2e455 HS |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <ioports.h> | |
26 | #include <mpc8260.h> | |
27 | ||
28 | #include "tqm8272.h" | |
29 | ||
30 | /* UPM pattern for bus clock = 66.7 MHz */ | |
31 | static const uint upmTable67[] = | |
32 | { | |
33 | /* Offset UPM Read Single RAM array entry -> NAND Read Data */ | |
34 | /* 0x00 */ 0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000, | |
35 | /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, | |
36 | ||
37 | /* UPM Read Burst RAM array entry -> unused */ | |
38 | /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
39 | /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
40 | ||
41 | /* UPM Read Burst RAM array entry -> unused */ | |
42 | /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
43 | /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
44 | ||
45 | /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ | |
46 | /* 0x18 */ 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, | |
47 | /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, | |
48 | ||
49 | /* UPM Write Burst RAM array entry -> unused */ | |
50 | /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
51 | /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
52 | /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
53 | /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
54 | ||
55 | /* UPM Refresh Timer RAM array entry -> unused */ | |
56 | /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
57 | /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
58 | /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
59 | ||
60 | /* UPM Exception RAM array entry -> unsused */ | |
61 | /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
62 | }; | |
63 | ||
64 | /* UPM pattern for bus clock = 100 MHz */ | |
65 | static const uint upmTable100[] = | |
66 | { | |
67 | /* Offset UPM Read Single RAM array entry -> NAND Read Data */ | |
68 | /* 0x00 */ 0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000, | |
69 | /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, | |
70 | ||
71 | /* UPM Read Burst RAM array entry -> unused */ | |
72 | /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
73 | /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
74 | ||
75 | /* UPM Read Burst RAM array entry -> unused */ | |
76 | /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
77 | /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
78 | ||
79 | /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ | |
80 | /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00, | |
81 | /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, | |
82 | ||
83 | /* UPM Write Burst RAM array entry -> unused */ | |
84 | /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
85 | /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
86 | /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
87 | /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
88 | ||
89 | /* UPM Refresh Timer RAM array entry -> unused */ | |
90 | /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
91 | /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
92 | /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
93 | ||
94 | /* UPM Exception RAM array entry -> unsused */ | |
95 | /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
96 | }; | |
97 | ||
98 | /* UPM pattern for bus clock = 133.3 MHz */ | |
99 | static const uint upmTable133[] = | |
100 | { | |
101 | /* Offset UPM Read Single RAM array entry -> NAND Read Data */ | |
102 | /* 0x00 */ 0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000, | |
103 | /* 0x04 */ 0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00, | |
104 | ||
105 | /* UPM Read Burst RAM array entry -> unused */ | |
106 | /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
107 | /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
108 | ||
109 | /* UPM Read Burst RAM array entry -> unused */ | |
110 | /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
111 | /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
112 | ||
113 | /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ | |
114 | /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00, | |
115 | /* 0x1C */ 0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, | |
116 | ||
117 | /* UPM Write Burst RAM array entry -> unused */ | |
118 | /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
119 | /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
120 | /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
121 | /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
122 | ||
123 | /* UPM Refresh Timer RAM array entry -> unused */ | |
124 | /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
125 | /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
126 | /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
127 | ||
128 | /* UPM Exception RAM array entry -> unsused */ | |
129 | /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
130 | }; | |
131 | ||
132 | static int chipsel = 0; | |
133 | ||
134 | #if defined(CONFIG_CMD_NAND) | |
135 | ||
136 | #include <nand.h> | |
137 | #include <linux/mtd/mtd.h> | |
138 | ||
139 | static u8 hwctl = 0; | |
140 | ||
141 | static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte) | |
142 | { | |
143 | struct nand_chip *this = mtdinfo->priv; | |
6d0f6bcf | 144 | ulong base = (ulong) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); |
a6f2e455 HS |
145 | |
146 | if (hwctl & 0x1) { | |
6d0f6bcf | 147 | WRITE_NAND_UPM(byte, base, CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS); |
a6f2e455 | 148 | } else if (hwctl & 0x2) { |
6d0f6bcf | 149 | WRITE_NAND_UPM(byte, base, CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS); |
a6f2e455 HS |
150 | } else { |
151 | WRITE_NAND(byte, base); | |
152 | } | |
153 | } | |
154 | ||
155 | static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |
156 | { | |
157 | if (ctrl & NAND_CTRL_CHANGE) { | |
158 | if ( ctrl & NAND_CLE ) | |
159 | hwctl |= 0x1; | |
160 | else | |
161 | hwctl &= ~0x1; | |
162 | if ( ctrl & NAND_ALE ) | |
163 | hwctl |= 0x2; | |
164 | else | |
165 | hwctl &= ~0x2; | |
166 | } | |
167 | if (cmd != NAND_CMD_NONE) | |
168 | upmnand_write_byte (mtd, cmd); | |
169 | } | |
170 | ||
171 | static u_char upmnand_read_byte(struct mtd_info *mtdinfo) | |
172 | { | |
173 | struct nand_chip *this = mtdinfo->priv; | |
6d0f6bcf | 174 | ulong base = (ulong) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); |
a6f2e455 HS |
175 | |
176 | return READ_NAND(base); | |
177 | } | |
178 | ||
179 | static int tqm8272_dev_ready(struct mtd_info *mtdinfo) | |
180 | { | |
181 | /* constant delay (see also tR in the datasheet) */ | |
182 | udelay(12); \ | |
183 | return 1; | |
184 | } | |
185 | ||
186 | #ifndef CONFIG_NAND_SPL | |
187 | static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) | |
188 | { | |
189 | struct nand_chip *this = mtdinfo->priv; | |
6d0f6bcf | 190 | unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); |
a6f2e455 HS |
191 | int i; |
192 | ||
193 | for (i = 0; i< len; i++) | |
194 | buf[i] = *base; | |
195 | } | |
196 | ||
197 | static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) | |
198 | { | |
199 | struct nand_chip *this = mtdinfo->priv; | |
6d0f6bcf | 200 | unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); |
a6f2e455 HS |
201 | int i; |
202 | ||
203 | for (i = 0; i< len; i++) | |
204 | *base = buf[i]; | |
205 | } | |
206 | ||
207 | static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) | |
208 | { | |
209 | struct nand_chip *this = mtdinfo->priv; | |
6d0f6bcf | 210 | unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); |
a6f2e455 HS |
211 | int i; |
212 | ||
213 | for (i = 0; i < len; i++) | |
214 | if (buf[i] != *base) | |
215 | return -1; | |
216 | return 0; | |
217 | } | |
218 | #endif /* #ifndef CONFIG_NAND_SPL */ | |
219 | ||
220 | void board_nand_select_device(struct nand_chip *nand, int chip) | |
221 | { | |
222 | chipsel = chip; | |
223 | } | |
224 | ||
225 | int board_nand_init(struct nand_chip *nand) | |
226 | { | |
227 | static int UpmInit = 0; | |
6d0f6bcf | 228 | volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR; |
a6f2e455 HS |
229 | volatile memctl8260_t *memctl = &immr->im_memctl; |
230 | ||
231 | if (hwinf.nand == 0) return -1; | |
232 | ||
233 | /* Setup the UPM */ | |
234 | if (UpmInit == 0) { | |
235 | switch (hwinf.busclk_real) { | |
236 | case 100000000: | |
237 | upmconfig (UPMB, (uint *) upmTable100, | |
238 | sizeof (upmTable100) / sizeof (uint)); | |
239 | break; | |
240 | case 133333333: | |
241 | upmconfig (UPMB, (uint *) upmTable133, | |
242 | sizeof (upmTable133) / sizeof (uint)); | |
243 | break; | |
244 | default: | |
245 | upmconfig (UPMB, (uint *) upmTable67, | |
246 | sizeof (upmTable67) / sizeof (uint)); | |
247 | break; | |
248 | } | |
249 | UpmInit = 1; | |
250 | } | |
251 | ||
252 | /* Setup the memctrl */ | |
6d0f6bcf JCPV |
253 | memctl->memc_or3 = CONFIG_SYS_NAND_OR; |
254 | memctl->memc_br3 = CONFIG_SYS_NAND_BR; | |
a6f2e455 HS |
255 | memctl->memc_mbmr = (MxMR_OP_NORM); |
256 | ||
257 | nand->ecc.mode = NAND_ECC_SOFT; | |
258 | ||
259 | nand->cmd_ctrl = upmnand_hwcontrol; | |
260 | nand->read_byte = upmnand_read_byte; | |
261 | nand->dev_ready = tqm8272_dev_ready; | |
262 | ||
263 | #ifndef CONFIG_NAND_SPL | |
264 | nand->write_buf = tqm8272_write_buf; | |
265 | nand->read_buf = tqm8272_read_buf; | |
266 | nand->verify_buf = tqm8272_verify_buf; | |
267 | #endif | |
268 | ||
269 | /* | |
270 | * Select required NAND chip | |
271 | */ | |
272 | board_nand_select_device(nand, 0); | |
273 | return 0; | |
274 | } | |
275 | ||
276 | #endif |