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fa230445 HS |
1 | /* |
2 | * (C) Copyright 2006 | |
3 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
fa230445 HS |
6 | */ |
7 | ||
8 | #include <common.h> | |
9 | #include <ioports.h> | |
10 | #include <mpc8260.h> | |
11 | ||
12 | #include <command.h> | |
10efa024 | 13 | #include <netdev.h> |
fa230445 HS |
14 | #ifdef CONFIG_PCI |
15 | #include <pci.h> | |
16 | #include <asm/m8260_pci.h> | |
17 | #endif | |
a6f2e455 | 18 | #include "tqm8272.h" |
fa230445 HS |
19 | |
20 | #if 0 | |
21 | #define deb_printf(fmt,arg...) \ | |
22 | printf ("TQM8272 %s %s: " fmt,__FILE__, __FUNCTION__, ##arg) | |
23 | #else | |
24 | #define deb_printf(fmt,arg...) \ | |
9c0f42ec | 25 | do { } while (0) |
fa230445 HS |
26 | #endif |
27 | ||
28 | #if defined(CONFIG_BOARD_GET_CPU_CLK_F) | |
29 | unsigned long board_get_cpu_clk_f (void); | |
30 | #endif | |
31 | ||
32 | /* | |
33 | * I/O Port configuration table | |
34 | * | |
35 | * if conf is 1, then that port pin will be configured at boot time | |
36 | * according to the five values podr/pdir/ppar/psor/pdat for that entry | |
37 | */ | |
38 | ||
39 | const iop_conf_t iop_conf_tab[4][32] = { | |
40 | ||
41 | /* Port A configuration */ | |
42 | { /* conf ppar psor pdir podr pdat */ | |
9c0f42ec WD |
43 | /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */ |
44 | /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */ | |
45 | /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */ | |
46 | /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */ | |
47 | /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */ | |
48 | /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */ | |
49 | /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ | |
50 | /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ | |
51 | /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ | |
52 | /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ | |
53 | /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ | |
54 | /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ | |
55 | /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ | |
56 | /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ | |
57 | /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */ | |
58 | /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */ | |
59 | /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */ | |
60 | /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */ | |
61 | /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */ | |
62 | /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */ | |
63 | /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */ | |
64 | /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */ | |
65 | /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ | |
66 | /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ | |
67 | /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ | |
68 | /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ | |
69 | /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ | |
70 | /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ | |
71 | /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ | |
72 | /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ | |
73 | /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ | |
74 | /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ | |
fa230445 HS |
75 | }, |
76 | ||
77 | /* Port B configuration */ | |
9c0f42ec WD |
78 | { /* conf ppar psor pdir podr pdat */ |
79 | /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ | |
80 | /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ | |
81 | /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ | |
82 | /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ | |
83 | /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ | |
84 | /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ | |
85 | /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ | |
86 | /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ | |
87 | /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ | |
88 | /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ | |
89 | /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ | |
90 | /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ | |
91 | /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ | |
92 | /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ | |
93 | /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ | |
94 | /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ | |
95 | /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ | |
96 | /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ | |
97 | /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ | |
98 | /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ | |
99 | /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ | |
100 | /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ | |
101 | /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ | |
102 | /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ | |
103 | /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ | |
104 | /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ | |
105 | /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ | |
106 | /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ | |
107 | /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
108 | /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
109 | /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
110 | /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ | |
fa230445 HS |
111 | }, |
112 | ||
113 | /* Port C */ | |
9c0f42ec WD |
114 | { /* conf ppar psor pdir podr pdat */ |
115 | /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ | |
116 | /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ | |
117 | /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ | |
118 | /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ | |
119 | /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ | |
120 | /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ | |
121 | /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ | |
122 | /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ | |
123 | /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ | |
124 | /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ | |
125 | /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ | |
126 | /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ | |
127 | /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ | |
128 | /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ | |
129 | /* PC17 */ { 1, 0, 0, 1, 0, 0 }, /* PC17 MDC */ | |
130 | /* PC16 */ { 1, 0, 0, 0, 0, 0 }, /* PC16 MDIO*/ | |
131 | /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ | |
132 | /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ | |
133 | /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ | |
134 | /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */ | |
135 | /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */ | |
136 | /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* PC10 */ | |
137 | /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* PC9 */ | |
138 | /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ | |
139 | /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ | |
140 | /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ | |
141 | /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* PC5 SMC1 TXD */ | |
142 | /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* PC4 SMC1 RXD */ | |
143 | /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ | |
144 | /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ | |
145 | /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ | |
146 | /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ | |
fa230445 HS |
147 | }, |
148 | ||
149 | /* Port D */ | |
9c0f42ec WD |
150 | { /* conf ppar psor pdir podr pdat */ |
151 | /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ | |
152 | /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ | |
153 | /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ | |
154 | /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ | |
155 | /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */ | |
156 | /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ | |
157 | /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ | |
158 | /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ | |
159 | /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ | |
160 | /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ | |
161 | /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ | |
162 | /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ | |
163 | /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ | |
164 | /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ | |
165 | /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ | |
166 | /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ | |
fa230445 | 167 | #if defined(CONFIG_SOFT_I2C) |
9c0f42ec WD |
168 | /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ |
169 | /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ | |
fa230445 HS |
170 | #else |
171 | #if defined(CONFIG_HARD_I2C) | |
9c0f42ec WD |
172 | /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ |
173 | /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ | |
fa230445 | 174 | #else /* normal I/O port pins */ |
9c0f42ec WD |
175 | /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ |
176 | /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ | |
fa230445 HS |
177 | #endif |
178 | #endif | |
9c0f42ec WD |
179 | /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ |
180 | /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ | |
181 | /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ | |
182 | /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ | |
183 | /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ | |
184 | /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ | |
185 | /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ | |
186 | /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ | |
187 | /* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PD5 */ | |
188 | /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ | |
189 | /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
190 | /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
191 | /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
192 | /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ | |
fa230445 HS |
193 | } |
194 | }; | |
195 | ||
fa230445 HS |
196 | /* UPM pattern for slow init */ |
197 | static const uint upmTableSlow[] = | |
198 | { | |
9c0f42ec WD |
199 | /* Offset UPM Read Single RAM array entry */ |
200 | /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcf00, 0x00ffdc00, | |
201 | /* 0x04 */ 0x00ffce80, 0x00ffcc00, 0x00ffee00, 0x3fffcc07, | |
202 | ||
203 | /* UPM Read Burst RAM array entry -> unused */ | |
204 | /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
205 | /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
206 | ||
207 | /* UPM Read Burst RAM array entry -> unused */ | |
208 | /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
209 | /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
210 | ||
211 | /* UPM Write Single RAM array entry */ | |
212 | /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffef00, 0x00fffc80, | |
213 | /* 0x1C */ 0x00fffe00, 0x00ffec00, 0x0fffef00, 0x3fffec05, | |
214 | ||
215 | /* UPM Write Burst RAM array entry -> unused */ | |
216 | /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
217 | /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
218 | /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
219 | /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
220 | ||
221 | /* UPM Refresh Timer RAM array entry -> unused */ | |
222 | /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
223 | /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
224 | /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
225 | ||
226 | /* UPM Exception RAM array entry -> unused */ | |
227 | /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
fa230445 HS |
228 | }; |
229 | ||
230 | /* UPM pattern for fast init */ | |
231 | static const uint upmTableFast[] = | |
232 | { | |
9c0f42ec WD |
233 | /* Offset UPM Read Single RAM array entry */ |
234 | /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcd80, 0x00ffdc00, | |
235 | /* 0x04 */ 0x00ffdc00, 0x00ffcf00, 0x00ffec00, 0x3fffcc07, | |
236 | ||
237 | /* UPM Read Burst RAM array entry -> unused */ | |
238 | /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
239 | /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
240 | ||
241 | /* UPM Read Burst RAM array entry -> unused */ | |
242 | /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
243 | /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
244 | ||
245 | /* UPM Write Single RAM array entry */ | |
246 | /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffee80, 0x00fffc00, | |
247 | /* 0x1C */ 0x00fffc00, 0x00ffec00, 0x0fffef00, 0x3fffec05, | |
248 | ||
249 | /* UPM Write Burst RAM array entry -> unused */ | |
250 | /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
251 | /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
252 | /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
253 | /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
254 | ||
255 | /* UPM Refresh Timer RAM array entry -> unused */ | |
256 | /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
257 | /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
258 | /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
259 | ||
260 | /* UPM Exception RAM array entry -> unused */ | |
261 | /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
fa230445 HS |
262 | }; |
263 | ||
264 | ||
265 | /* ------------------------------------------------------------------------- */ | |
266 | ||
267 | /* Check Board Identity: | |
268 | */ | |
269 | int checkboard (void) | |
270 | { | |
271 | char *p = (char *) HWIB_INFO_START_ADDR; | |
272 | ||
273 | puts ("Board: "); | |
6d0f6bcf | 274 | if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { |
fa230445 HS |
275 | puts (p); |
276 | } else { | |
277 | puts ("No HWIB assuming TQM8272"); | |
278 | } | |
279 | putc ('\n'); | |
280 | ||
281 | return 0; | |
282 | } | |
283 | ||
284 | /* ------------------------------------------------------------------------- */ | |
285 | #if defined(CONFIG_BOARD_GET_CPU_CLK_F) | |
286 | static int get_cas_latency (void) | |
287 | { | |
288 | /* get it from the option -ts in CIB */ | |
289 | /* default is 3 */ | |
290 | int ret = 3; | |
291 | int pos = 0; | |
292 | char *p = (char *) CIB_INFO_START_ADDR; | |
293 | ||
294 | while ((*p != '\0') && (pos < CIB_INFO_LEN)) { | |
295 | if (*p < ' ' || *p > '~') { /* ASCII strings! */ | |
296 | return ret; | |
297 | } | |
298 | if (*p == '-') { | |
299 | if ((p[1] == 't') && (p[2] == 's')) { | |
300 | return (p[4] - '0'); | |
301 | } | |
302 | } | |
303 | p++; | |
304 | pos++; | |
305 | } | |
306 | return ret; | |
307 | } | |
308 | #endif | |
309 | ||
310 | static ulong set_sdram_timing (volatile uint *sdmr_ptr, ulong sdmr, int col) | |
311 | { | |
312 | #if defined(CONFIG_BOARD_GET_CPU_CLK_F) | |
313 | int clk = board_get_cpu_clk_f (); | |
6d0f6bcf | 314 | volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
fa230445 HS |
315 | int busmode = (immr->im_siu_conf.sc_bcr & BCR_EBM ? 1 : 0); |
316 | int cas; | |
317 | ||
318 | sdmr = sdmr & ~(PSDMR_RFRC_MSK | PSDMR_PRETOACT_MSK | PSDMR_WRC_MSK | \ | |
319 | PSDMR_BUFCMD); | |
320 | if (busmode) { | |
321 | switch (clk) { | |
322 | case 66666666: | |
323 | sdmr |= (PSDMR_RFRC_66MHZ_60X | \ | |
324 | PSDMR_PRETOACT_66MHZ_60X | \ | |
325 | PSDMR_WRC_66MHZ_60X | \ | |
326 | PSDMR_BUFCMD_66MHZ_60X); | |
327 | break; | |
328 | case 100000000: | |
329 | sdmr |= (PSDMR_RFRC_100MHZ_60X | \ | |
330 | PSDMR_PRETOACT_100MHZ_60X | \ | |
331 | PSDMR_WRC_100MHZ_60X | \ | |
332 | PSDMR_BUFCMD_100MHZ_60X); | |
333 | break; | |
334 | ||
335 | } | |
336 | } else { | |
337 | switch (clk) { | |
338 | case 66666666: | |
339 | sdmr |= (PSDMR_RFRC_66MHZ_SINGLE | \ | |
340 | PSDMR_PRETOACT_66MHZ_SINGLE | \ | |
341 | PSDMR_WRC_66MHZ_SINGLE | \ | |
342 | PSDMR_BUFCMD_66MHZ_SINGLE); | |
343 | break; | |
344 | case 100000000: | |
345 | sdmr |= (PSDMR_RFRC_100MHZ_SINGLE | \ | |
346 | PSDMR_PRETOACT_100MHZ_SINGLE | \ | |
347 | PSDMR_WRC_100MHZ_SINGLE | \ | |
348 | PSDMR_BUFCMD_100MHZ_SINGLE); | |
349 | break; | |
350 | case 133333333: | |
351 | sdmr |= (PSDMR_RFRC_133MHZ_SINGLE | \ | |
352 | PSDMR_PRETOACT_133MHZ_SINGLE | \ | |
353 | PSDMR_WRC_133MHZ_SINGLE | \ | |
354 | PSDMR_BUFCMD_133MHZ_SINGLE); | |
355 | break; | |
356 | } | |
357 | } | |
358 | cas = get_cas_latency(); | |
359 | sdmr &=~ (PSDMR_CL_MSK | PSDMR_LDOTOPRE_MSK); | |
360 | sdmr |= cas; | |
361 | sdmr |= ((cas - 1) << 6); | |
362 | return sdmr; | |
363 | #else | |
364 | return sdmr; | |
365 | #endif | |
366 | } | |
367 | ||
368 | /* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx | |
369 | * | |
370 | * This routine performs standard 8260 initialization sequence | |
371 | * and calculates the available memory size. It may be called | |
372 | * several times to try different SDRAM configurations on both | |
373 | * 60x and local buses. | |
374 | */ | |
375 | static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, | |
376 | ulong orx, volatile uchar * base, int col) | |
377 | { | |
378 | volatile uchar c = 0xff; | |
379 | volatile uint *sdmr_ptr; | |
380 | volatile uint *orx_ptr; | |
381 | ulong maxsize, size; | |
382 | int i; | |
383 | ||
384 | /* We must be able to test a location outsize the maximum legal size | |
385 | * to find out THAT we are outside; but this address still has to be | |
386 | * mapped by the controller. That means, that the initial mapping has | |
387 | * to be (at least) twice as large as the maximum expected size. | |
388 | */ | |
389 | maxsize = (1 + (~orx | 0x7fff)) / 2; | |
390 | ||
6d0f6bcf | 391 | /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that |
fa230445 HS |
392 | * we are configuring CS1 if base != 0 |
393 | */ | |
394 | sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; | |
395 | orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1; | |
396 | ||
397 | *orx_ptr = orx; | |
398 | sdmr = set_sdram_timing (sdmr_ptr, sdmr, col); | |
399 | /* | |
400 | * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): | |
401 | * | |
402 | * "At system reset, initialization software must set up the | |
403 | * programmable parameters in the memory controller banks registers | |
404 | * (ORx, BRx, P/LSDMR). After all memory parameters are configured, | |
405 | * system software should execute the following initialization sequence | |
406 | * for each SDRAM device. | |
407 | * | |
408 | * 1. Issue a PRECHARGE-ALL-BANKS command | |
409 | * 2. Issue eight CBR REFRESH commands | |
410 | * 3. Issue a MODE-SET command to initialize the mode register | |
411 | * | |
412 | * The initial commands are executed by setting P/LSDMR[OP] and | |
413 | * accessing the SDRAM with a single-byte transaction." | |
414 | * | |
415 | * The appropriate BRx/ORx registers have already been set when we | |
6d0f6bcf | 416 | * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. |
fa230445 HS |
417 | */ |
418 | ||
419 | *sdmr_ptr = sdmr | PSDMR_OP_PREA; | |
420 | *base = c; | |
421 | ||
422 | *sdmr_ptr = sdmr | PSDMR_OP_CBRR; | |
423 | for (i = 0; i < 8; i++) | |
424 | *base = c; | |
425 | ||
426 | *sdmr_ptr = sdmr | PSDMR_OP_MRW; | |
6d0f6bcf | 427 | *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ |
fa230445 HS |
428 | |
429 | *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; | |
430 | *base = c; | |
431 | ||
432 | size = get_ram_size((long *)base, maxsize); | |
433 | *orx_ptr = orx | ~(size - 1); | |
434 | ||
435 | return (size); | |
436 | } | |
437 | ||
9973e3c6 | 438 | phys_size_t initdram (int board_type) |
fa230445 | 439 | { |
6d0f6bcf | 440 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
fa230445 HS |
441 | volatile memctl8260_t *memctl = &immap->im_memctl; |
442 | ||
6d0f6bcf | 443 | #ifndef CONFIG_SYS_RAMBOOT |
fa230445 HS |
444 | long size8, size9; |
445 | #endif | |
1f884334 | 446 | long psize; |
fa230445 HS |
447 | |
448 | psize = 16 * 1024 * 1024; | |
fa230445 | 449 | |
6d0f6bcf JCPV |
450 | memctl->memc_psrt = CONFIG_SYS_PSRT; |
451 | memctl->memc_mptpr = CONFIG_SYS_MPTPR; | |
fa230445 | 452 | |
6d0f6bcf | 453 | #ifndef CONFIG_SYS_RAMBOOT |
fa230445 HS |
454 | /* 60x SDRAM setup: |
455 | */ | |
6d0f6bcf JCPV |
456 | size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, |
457 | (uchar *) CONFIG_SYS_SDRAM_BASE, 8); | |
458 | size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL, | |
459 | (uchar *) CONFIG_SYS_SDRAM_BASE, 9); | |
fa230445 HS |
460 | |
461 | if (size8 < size9) { | |
462 | psize = size9; | |
463 | printf ("(60x:9COL - %ld MB, ", psize >> 20); | |
464 | } else { | |
6d0f6bcf JCPV |
465 | psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, |
466 | (uchar *) CONFIG_SYS_SDRAM_BASE, 8); | |
fa230445 HS |
467 | printf ("(60x:8COL - %ld MB, ", psize >> 20); |
468 | } | |
469 | ||
6d0f6bcf | 470 | #endif /* CONFIG_SYS_RAMBOOT */ |
fa230445 HS |
471 | |
472 | icache_enable (); | |
473 | ||
474 | return (psize); | |
475 | } | |
476 | ||
477 | ||
478 | static inline int scanChar (char *p, int len, unsigned long *number) | |
479 | { | |
480 | int akt = 0; | |
481 | ||
482 | *number = 0; | |
9c0f42ec | 483 | while (akt < len) { |
fa230445 HS |
484 | if ((*p >= '0') && (*p <= '9')) { |
485 | *number *= 10; | |
486 | *number += *p - '0'; | |
487 | p += 1; | |
488 | } else { | |
489 | if (*p == '-') return akt; | |
490 | return -1; | |
491 | } | |
492 | akt ++; | |
493 | } | |
494 | return akt; | |
495 | } | |
496 | ||
fa230445 HS |
497 | static int dump_hwib(void) |
498 | { | |
499 | HWIB_INFO *hw = &hwinf; | |
f0c0b3a9 WD |
500 | char buf[64]; |
501 | int i = getenv_f("serial#", buf, sizeof(buf)); | |
6d0f6bcf | 502 | volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
f0c0b3a9 WD |
503 | |
504 | if (i < 0) | |
505 | buf[0] = '\0'; | |
fa230445 HS |
506 | |
507 | if (hw->OK) { | |
508 | printf ("HWIB on %x\n", HWIB_INFO_START_ADDR); | |
f0c0b3a9 | 509 | printf ("serial : %s\n", buf); |
fa230445 | 510 | printf ("ethaddr: %s\n", hw->ethaddr); |
9c0f42ec WD |
511 | printf ("FLASH : %x nr:%d\n", hw->flash, hw->flash_nr); |
512 | printf ("RAM : %x cs:%d\n", hw->ram, hw->ram_cs); | |
9b55a253 | 513 | printf ("CPU : %lu\n", hw->cpunr); |
9c0f42ec | 514 | printf ("CAN : %d\n", hw->can); |
fa230445 HS |
515 | if (hw->eeprom) printf ("EEprom : %x\n", hw->eeprom); |
516 | else printf ("No EEprom\n"); | |
517 | if (hw->nand) { | |
9c0f42ec | 518 | printf ("NAND : %x\n", hw->nand); |
fa230445 HS |
519 | printf ("NAND CS: %d\n", hw->nand_cs); |
520 | } else { printf ("No NAND\n");} | |
521 | printf ("Bus %s mode.\n", (hw->Bus ? "60x" : "Single PQII")); | |
522 | printf (" real : %s\n", (immr->im_siu_conf.sc_bcr & BCR_EBM ? \ | |
523 | "60x" : "Single PQII")); | |
9b55a253 | 524 | printf ("Option : %lx\n", hw->option); |
fa230445 HS |
525 | printf ("%s Security Engine\n", (hw->SecEng ? "with" : "no")); |
526 | printf ("CPM Clk: %d\n", hw->cpmcl); | |
527 | printf ("CPU Clk: %d\n", hw->cpucl); | |
528 | printf ("Bus Clk: %d\n", hw->buscl); | |
529 | if (hw->busclk_real_ok) { | |
530 | printf (" real Clk: %d\n", hw->busclk_real); | |
531 | } | |
9c0f42ec | 532 | printf ("CAS : %d\n", get_cas_latency()); |
fa230445 HS |
533 | } else { |
534 | printf("HWIB @%x not OK\n", HWIB_INFO_START_ADDR); | |
535 | } | |
536 | return 0; | |
537 | } | |
538 | ||
539 | static inline int search_real_busclk (int *clk) | |
540 | { | |
541 | int part = 0, pos = 0; | |
542 | char *p = (char *) CIB_INFO_START_ADDR; | |
543 | int ok = 0; | |
544 | ||
545 | while ((*p != '\0') && (pos < CIB_INFO_LEN)) { | |
546 | if (*p < ' ' || *p > '~') { /* ASCII strings! */ | |
547 | return 0; | |
548 | } | |
549 | switch (part) { | |
550 | default: | |
551 | if (*p == '-') { | |
552 | ++part; | |
553 | } | |
554 | break; | |
555 | case 3: | |
556 | if (*p == '-') { | |
557 | ++part; | |
558 | break; | |
559 | } | |
560 | if (*p == 'b') { | |
561 | ok = 1; | |
562 | p++; | |
563 | break; | |
564 | } | |
565 | if (ok) { | |
566 | switch (*p) { | |
567 | case '6': | |
568 | *clk = 66666666; | |
569 | return 1; | |
570 | break; | |
571 | case '1': | |
572 | if (p[1] == '3') { | |
573 | *clk = 133333333; | |
574 | } else { | |
575 | *clk = 100000000; | |
576 | } | |
577 | return 1; | |
578 | break; | |
579 | } | |
580 | } | |
581 | break; | |
582 | } | |
583 | p++; | |
584 | } | |
585 | return 0; | |
586 | } | |
587 | ||
588 | int analyse_hwib (void) | |
589 | { | |
590 | char *p = (char *) HWIB_INFO_START_ADDR; | |
591 | int anz; | |
592 | int part = 1, i = 0, pos = 0; | |
593 | HWIB_INFO *hw = &hwinf; | |
594 | ||
595 | deb_printf(" %s pointer: %p\n", __FUNCTION__, p); | |
596 | /* Head = TQM */ | |
6d0f6bcf | 597 | if (*((unsigned long *)p) != (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { |
fa230445 HS |
598 | deb_printf("No HWIB\n"); |
599 | return -1; | |
600 | } | |
601 | p += 3; | |
602 | if (scanChar (p, 4, &hw->cpunr) < 0) { | |
603 | deb_printf("No CPU\n"); | |
604 | return -2; | |
605 | } | |
606 | p +=4; | |
607 | ||
608 | hw->flash = 0x200000 << (*p - 'A'); | |
609 | p++; | |
610 | hw->flash_nr = *p - '0'; | |
611 | p++; | |
612 | ||
613 | hw->ram = 0x2000000 << (*p - 'A'); | |
614 | p++; | |
615 | if (*p == '2') { | |
616 | hw->ram_cs = 2; | |
617 | p++; | |
618 | } | |
619 | ||
9c0f42ec WD |
620 | if (*p == 'A') hw->can = 1; |
621 | if (*p == 'B') hw->can = 2; | |
fa230445 HS |
622 | p +=1; |
623 | p +=1; /* connector */ | |
624 | if (*p != '0') { | |
07e82cb2 | 625 | hw->eeprom = 0x1000 << (*p - 'A'); |
fa230445 HS |
626 | } |
627 | p++; | |
9c0f42ec WD |
628 | |
629 | if ((*p < '0') || (*p > '9')) { | |
fa230445 HS |
630 | /* NAND before z-option */ |
631 | hw->nand = 0x8000000 << (*p - 'A'); | |
632 | p++; | |
633 | hw->nand_cs = *p - '0'; | |
634 | p += 2; | |
635 | } | |
636 | /* z-option */ | |
637 | anz = scanChar (p, 4, &hw->option); | |
638 | if (anz < 0) { | |
639 | deb_printf("No option\n"); | |
640 | return -3; | |
641 | } | |
642 | if (hw->option & 0x8) hw->Bus = 1; | |
643 | p += anz; | |
644 | if (*p != '-') { | |
645 | deb_printf("No -\n"); | |
646 | return -4; | |
647 | } | |
648 | p++; | |
649 | /* C option */ | |
650 | if (*p == 'E') { | |
651 | hw->SecEng = 1; | |
652 | p++; | |
653 | } | |
654 | switch (*p) { | |
655 | case 'M': hw->cpucl = 266666666; | |
656 | break; | |
657 | case 'P': hw->cpucl = 300000000; | |
658 | break; | |
659 | case 'T': hw->cpucl = 400000000; | |
660 | break; | |
661 | default: | |
662 | deb_printf("No CPU Clk: %c\n", *p); | |
663 | return -5; | |
664 | break; | |
665 | } | |
666 | p++; | |
667 | switch (*p) { | |
668 | case 'I': hw->cpmcl = 200000000; | |
669 | break; | |
670 | case 'M': hw->cpmcl = 300000000; | |
671 | break; | |
672 | default: | |
673 | deb_printf("No CPM Clk\n"); | |
674 | return -6; | |
675 | break; | |
676 | } | |
677 | p++; | |
678 | switch (*p) { | |
679 | case 'B': hw->buscl = 66666666; | |
680 | break; | |
681 | case 'E': hw->buscl = 100000000; | |
682 | break; | |
683 | case 'F': hw->buscl = 133333333; | |
684 | break; | |
685 | default: | |
686 | deb_printf("No BUS Clk\n"); | |
687 | return -7; | |
688 | break; | |
689 | } | |
690 | p++; | |
691 | ||
692 | hw->OK = 1; | |
693 | /* search MAC Address */ | |
6d0f6bcf | 694 | while ((*p != '\0') && (pos < CONFIG_SYS_HWINFO_SIZE)) { |
fa230445 HS |
695 | if (*p < ' ' || *p > '~') { /* ASCII strings! */ |
696 | return 0; | |
697 | } | |
698 | switch (part) { | |
699 | default: | |
700 | if (*p == ' ') { | |
701 | ++part; | |
702 | i = 0; | |
703 | } | |
704 | break; | |
705 | case 3: /* Copy MAC address */ | |
706 | if (*p == ' ') { | |
707 | ++part; | |
708 | i = 0; | |
709 | break; | |
710 | } | |
711 | hw->ethaddr[i++] = *p; | |
712 | if ((i % 3) == 2) | |
713 | hw->ethaddr[i++] = ':'; | |
714 | break; | |
715 | ||
716 | } | |
717 | p++; | |
718 | } | |
719 | ||
720 | hw->busclk_real_ok = search_real_busclk (&hw->busclk_real); | |
721 | return 0; | |
722 | } | |
723 | ||
724 | #if defined(CONFIG_GET_CPU_STR_F) | |
725 | /* !! This routine runs from Flash */ | |
726 | char get_cpu_str_f (char *buf) | |
727 | { | |
728 | char *p = (char *) HWIB_INFO_START_ADDR; | |
729 | int i = 0; | |
730 | ||
731 | buf[i++] = 'M'; | |
732 | buf[i++] = 'P'; | |
733 | buf[i++] = 'C'; | |
6d0f6bcf | 734 | if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { |
fa230445 HS |
735 | buf[i++] = *&p[3]; |
736 | buf[i++] = *&p[4]; | |
737 | buf[i++] = *&p[5]; | |
738 | buf[i++] = *&p[6]; | |
739 | } else { | |
740 | buf[i++] = '8'; | |
741 | buf[i++] = '2'; | |
742 | buf[i++] = '7'; | |
743 | buf[i++] = 'x'; | |
744 | } | |
745 | buf[i++] = 0; | |
746 | return 0; | |
747 | } | |
748 | #endif | |
749 | ||
750 | #if defined(CONFIG_BOARD_GET_CPU_CLK_F) | |
751 | /* !! This routine runs from Flash */ | |
752 | unsigned long board_get_cpu_clk_f (void) | |
753 | { | |
754 | char *p = (char *) HWIB_INFO_START_ADDR; | |
755 | int i = 0; | |
756 | ||
6d0f6bcf | 757 | if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { |
fa230445 HS |
758 | if (search_real_busclk (&i)) |
759 | return i; | |
760 | } | |
761 | return CONFIG_8260_CLKIN; | |
762 | } | |
763 | #endif | |
764 | ||
765 | #if CONFIG_BOARD_EARLY_INIT_R | |
766 | ||
767 | static int can_test (unsigned long off) | |
768 | { | |
6d0f6bcf | 769 | volatile unsigned char *base = (unsigned char *) (CONFIG_SYS_CAN_BASE + off); |
fa230445 HS |
770 | |
771 | *(base + 0x17) = 'T'; | |
772 | *(base + 0x18) = 'Q'; | |
773 | *(base + 0x19) = 'M'; | |
774 | if ((*(base + 0x17) != 'T') || | |
775 | (*(base + 0x18) != 'Q') || | |
776 | (*(base + 0x19) != 'M')) { | |
777 | return 0; | |
778 | } | |
779 | return 1; | |
780 | } | |
781 | ||
782 | static int can_config_one (unsigned long off) | |
783 | { | |
6d0f6bcf JCPV |
784 | volatile unsigned char *ctrl = (unsigned char *) (CONFIG_SYS_CAN_BASE + off); |
785 | volatile unsigned char *cpu_if = (unsigned char *) (CONFIG_SYS_CAN_BASE + off + 0x02); | |
786 | volatile unsigned char *clkout = (unsigned char *) (CONFIG_SYS_CAN_BASE + off + 0x1f); | |
fa230445 HS |
787 | unsigned char temp; |
788 | ||
9c0f42ec | 789 | *cpu_if = 0x45; |
fa230445 HS |
790 | temp = *ctrl; |
791 | temp |= 0x40; | |
792 | *ctrl = temp; | |
9c0f42ec | 793 | *clkout = 0x20; |
fa230445 HS |
794 | temp = *ctrl; |
795 | temp &= ~0x40; | |
796 | *ctrl = temp; | |
797 | return 0; | |
798 | } | |
799 | ||
800 | static int can_config (void) | |
801 | { | |
802 | int ret = 0; | |
803 | can_config_one (0); | |
804 | if (hwinf.can == 2) { | |
805 | can_config_one (0x100); | |
806 | } | |
807 | /* make Test if they really there */ | |
808 | ret += can_test (0); | |
809 | ret += can_test (0x100); | |
810 | return ret; | |
811 | } | |
812 | ||
813 | static int init_can (void) | |
814 | { | |
6d0f6bcf | 815 | volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR; |
fa230445 HS |
816 | volatile memctl8260_t *memctl = &immr->im_memctl; |
817 | int count = 0; | |
818 | ||
819 | if ((hwinf.OK) && (hwinf.can)) { | |
6d0f6bcf JCPV |
820 | memctl->memc_or4 = CONFIG_SYS_CAN_OR; |
821 | memctl->memc_br4 = CONFIG_SYS_CAN_BR; | |
fa230445 HS |
822 | /* upm Init */ |
823 | upmconfig (UPMC, (uint *) upmTableFast, | |
824 | sizeof (upmTableFast) / sizeof (uint)); | |
825 | memctl->memc_mcmr = (MxMR_DSx_3_CYCL | | |
826 | MxMR_GPL_x4DIS | | |
827 | MxMR_RLFx_2X | | |
828 | MxMR_WLFx_2X | | |
829 | MxMR_OP_NORM); | |
830 | /* can configure */ | |
831 | count = can_config (); | |
6d0f6bcf | 832 | printf ("CAN: %d @ %x\n", count, CONFIG_SYS_CAN_BASE); |
fa230445 HS |
833 | if (hwinf.can != count) printf("!!! difference to HWIB\n"); |
834 | } else { | |
9c0f42ec | 835 | printf ("CAN: No\n"); |
fa230445 HS |
836 | } |
837 | return 0; | |
838 | } | |
839 | ||
840 | int board_early_init_r(void) | |
841 | { | |
842 | analyse_hwib (); | |
843 | init_can (); | |
844 | return 0; | |
845 | } | |
846 | #endif | |
847 | ||
54841ab5 | 848 | int do_hwib_dump (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) |
fa230445 HS |
849 | { |
850 | dump_hwib (); | |
851 | return 0; | |
852 | } | |
853 | ||
854 | U_BOOT_CMD( | |
9c0f42ec | 855 | hwib, 1, 1, do_hwib_dump, |
2fb2604d | 856 | "dump HWIB'", |
a89c33db | 857 | "" |
fa230445 HS |
858 | ); |
859 | ||
6d0f6bcf | 860 | #ifdef CONFIG_SYS_UPDATE_FLASH_SIZE |
fa230445 HS |
861 | static int get_flash_timing (void) |
862 | { | |
863 | /* get it from the option -tf in CIB */ | |
864 | /* default is 0x00000c84 */ | |
865 | int ret = 0x00000c84; | |
866 | int pos = 0; | |
867 | int nr = 0; | |
868 | char *p = (char *) CIB_INFO_START_ADDR; | |
869 | ||
870 | while ((*p != '\0') && (pos < CIB_INFO_LEN)) { | |
871 | if (*p < ' ' || *p > '~') { /* ASCII strings! */ | |
872 | return ret; | |
873 | } | |
874 | if (*p == '-') { | |
875 | if ((p[1] == 't') && (p[2] == 'f')) { | |
876 | p += 6; | |
877 | ret = 0; | |
878 | while (nr < 8) { | |
879 | if ((*p >= '0') && (*p <= '9')) { | |
880 | ret *= 0x10; | |
881 | ret += *p - '0'; | |
882 | p += 1; | |
883 | nr ++; | |
884 | } else if ((*p >= 'A') && (*p <= 'F')) { | |
885 | ret *= 10; | |
886 | ret += *p - '7'; | |
887 | p += 1; | |
888 | nr ++; | |
889 | } else { | |
890 | if (nr < 8) return 0x00000c84; | |
891 | return ret; | |
892 | } | |
893 | } | |
894 | } | |
895 | } | |
896 | p++; | |
897 | pos++; | |
898 | } | |
899 | return ret; | |
900 | } | |
901 | ||
902 | /* Update the Flash_Size and the Flash Timing */ | |
903 | int update_flash_size (int flash_size) | |
904 | { | |
6d0f6bcf | 905 | volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR; |
fa230445 HS |
906 | volatile memctl8260_t *memctl = &immr->im_memctl; |
907 | unsigned long reg; | |
908 | unsigned long tim; | |
909 | ||
910 | /* I must use reg, otherwise the board hang */ | |
911 | reg = memctl->memc_or0; | |
912 | reg &= ~ORxU_AM_MSK; | |
913 | reg |= MEG_TO_AM(flash_size >> 20); | |
914 | tim = get_flash_timing (); | |
915 | reg &= ~0xfff; | |
916 | reg |= (tim & 0xfff); | |
917 | memctl->memc_or0 = reg; | |
918 | return 0; | |
919 | } | |
920 | #endif | |
921 | ||
fa230445 HS |
922 | #ifdef CONFIG_PCI |
923 | struct pci_controller hose; | |
924 | ||
925 | int board_early_init_f (void) | |
926 | { | |
6d0f6bcf | 927 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
fa230445 HS |
928 | |
929 | immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN; | |
930 | return 0; | |
931 | } | |
932 | ||
933 | extern void pci_mpc8250_init(struct pci_controller *); | |
934 | ||
935 | void pci_init_board(void) | |
936 | { | |
937 | pci_mpc8250_init(&hose); | |
938 | } | |
939 | #endif | |
10efa024 BW |
940 | |
941 | int board_eth_init(bd_t *bis) | |
942 | { | |
943 | return pci_eth_init(bis); | |
944 | } |