[people/ms/u-boot.git] / board / tqc / tqm85xx / law.c

/*
 * Copyright 2008 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>

/*
 * LAW(Local Access Window) configuration:
 *
 * Standard mapping:
 *
 * 0x0000_0000	   0x7fff_ffff	   DDR			   2G
 * 0x8000_0000	   0x9fff_ffff	   PCI1 MEM		   512M
 * 0xc000_0000	   0xdfff_ffff	   RapidIO or PCI express  512M
 * 0xe000_0000	   0xe000_ffff	   CCSR			   1M
 * 0xe200_0000	   0xe2ff_ffff	   PCI1 IO		   16M
 * 0xe300_0000	   0xe3ff_ffff	   CAN and NAND Flash	   16M
 * 0xef00_0000	   0xefff_ffff     PCI express IO          16M
 * 0xfc00_0000	   0xffff_ffff	   FLASH (boot bank)	   128M
 *
 * Big FLASH mapping:
 *
 * 0x0000_0000	   0x7fff_ffff	   DDR			   2G
 * 0x8000_0000	   0x9fff_ffff	   PCI1 MEM		   512M
 * 0xa000_0000	   0xa000_ffff	   CCSR			   1M
 * 0xa200_0000	   0xa2ff_ffff	   PCI1 IO		   16M
 * 0xa300_0000	   0xa3ff_ffff	   CAN and NAND Flash	   16M
 * 0xaf00_0000	   0xafff_ffff     PCI express IO          16M
 * 0xb000_0000	   0xbfff_ffff	   RapidIO or PCI express  256M
 * 0xc000_0000	   0xffff_ffff	   FLASH (boot bank)	   1G
 *
 * Notes:
 *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
 *    If flash is 8M at default position (last 8M), no LAW needed.
 */

#ifdef CONFIG_TQM_BIGFLASH
#define LAW_3_SIZE LAW_SIZE_1G
#define LAW_5_SIZE LAW_SIZE_256M
#else
#define LAW_3_SIZE LAW_SIZE_128M
#define LAW_5_SIZE LAW_SIZE_512M
#endif

struct law_entry law_table[] = {
	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
	SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
#ifdef CONFIG_PCIE1
	SET_LAW(CONFIG_SYS_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1),
#else /* !CONFIG_PCIE1 */
	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO),
#endif /* CONFIG_PCIE1 */
#if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND)
	SET_LAW(CONFIG_SYS_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
#endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */
#ifdef CONFIG_PCIE1
	SET_LAW(CONFIG_SYS_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1),
#endif /* CONFIG_PCIE */
};

int num_law_entries = ARRAY_SIZE (law_table);
Commit	Line	Data
4d3521cc KG	1	/*
	2	* Copyright 2008 Freescale Semiconductor, Inc.
	3	*
	4	* (C) Copyright 2000
	5	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#include <common.h>
	27	#include <asm/fsl_law.h>
	28	#include <asm/mmu.h>
	29
	30	/*
	31	* LAW(Local Access Window) configuration:
	32	*
e8cc3f04 WG	33	* Standard mapping:
e8cc3f04 WG	34	*
4d3521cc KG	35	* 0x0000_0000 0x7fff_ffff DDR 2G
4d3521cc KG	36	* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
b9e8078b	37	* 0xc000_0000 0xdfff_ffff RapidIO or PCI express 512M
4d3521cc KG	38	* 0xe000_0000 0xe000_ffff CCSR 1M
4d3521cc KG	39	* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
1c2deff2	40	* 0xe300_0000 0xe3ff_ffff CAN and NAND Flash 16M
b9e8078b	41	* 0xef00_0000 0xefff_ffff PCI express IO 16M
e8cc3f04 WG	42	* 0xfc00_0000 0xffff_ffff FLASH (boot bank) 128M
	43	*
	44	* Big FLASH mapping:
	45	*
	46	* 0x0000_0000 0x7fff_ffff DDR 2G
	47	* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
	48	* 0xa000_0000 0xa000_ffff CCSR 1M
	49	* 0xa200_0000 0xa2ff_ffff PCI1 IO 16M
	50	* 0xa300_0000 0xa3ff_ffff CAN and NAND Flash 16M
	51	* 0xaf00_0000 0xafff_ffff PCI express IO 16M
	52	* 0xb000_0000 0xbfff_ffff RapidIO or PCI express 256M
	53	* 0xc000_0000 0xffff_ffff FLASH (boot bank) 1G
4d3521cc KG	54	*
	55	* Notes:
	56	* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
	57	* If flash is 8M at default position (last 8M), no LAW needed.
	58	*/
	59
e8cc3f04 WG	60	#ifdef CONFIG_TQM_BIGFLASH
	61	#define LAW_3_SIZE LAW_SIZE_1G
	62	#define LAW_5_SIZE LAW_SIZE_256M
	63	#else
	64	#define LAW_3_SIZE LAW_SIZE_128M
	65	#define LAW_5_SIZE LAW_SIZE_512M
	66	#endif
	67
4d3521cc	68	struct law_entry law_table[] = {
6d0f6bcf JCPV	69	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
	70	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
	71	SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
	72	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
b9e8078b	73	#ifdef CONFIG_PCIE1
6d0f6bcf	74	SET_LAW(CONFIG_SYS_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1),
b9e8078b	75	#else /* !CONFIG_PCIE1 */
6d0f6bcf	76	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO),
b9e8078b	77	#endif /* CONFIG_PCIE1 */
1c2deff2	78	#if defined(CONFIG_CAN_DRIVER) \|\| defined(CONFIG_NAND)
6d0f6bcf	79	SET_LAW(CONFIG_SYS_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
1c2deff2	80	#endif /* CONFIG_CAN_DRIVER \|\| CONFIG_NAND */
b9e8078b	81	#ifdef CONFIG_PCIE1
6d0f6bcf	82	SET_LAW(CONFIG_SYS_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1),
b9e8078b	83	#endif /* CONFIG_PCIE */
4d3521cc KG	84	};
4d3521cc KG	85
b99ba167	86	int num_law_entries = ARRAY_SIZE (law_table);