[people/ms/u-boot.git] / board / tqm8xx / tqm8xx.c

/*
 * (C) Copyright 2000-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#if 0
#define DEBUG
#endif

#include <common.h>
#include <mpc8xx.h>
#ifdef CONFIG_PS2MULT
#include <ps2mult.h>
#endif

/* ------------------------------------------------------------------------- */

static long int dram_size (long int, long int *, long int);

/* ------------------------------------------------------------------------- */

#define	_NOT_USED_	0xFFFFFFFF

const uint sdram_table[] =
{
	/*
	 * Single Read. (Offset 0 in UPMA RAM)
	 */
	0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
	0x1FF5FC47, /* last */
	/*
	 * SDRAM Initialization (offset 5 in UPMA RAM)
	 *
	 * This is no UPM entry point. The following definition uses
	 * the remaining space to establish an initialization
	 * sequence, which is executed by a RUN command.
	 *
	 */
		    0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
	/*
	 * Burst Read. (Offset 8 in UPMA RAM)
	 */
	0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
	0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Single Write. (Offset 18 in UPMA RAM)
	 */
	0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Burst Write. (Offset 20 in UPMA RAM)
	 */
	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
	0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
					    _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Refresh  (Offset 30 in UPMA RAM)
	 */
	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	0xFFFFFC84, 0xFFFFFC07, /* last */
				_NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Exception. (Offset 3c in UPMA RAM)
	 */
	0x7FFFFC07, /* last */
		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
};

/* ------------------------------------------------------------------------- */


/*
 * Check Board Identity:
 *
 * Test TQ ID string (TQM8xx...)
 * If present, check for "L" type (no second DRAM bank),
 * otherwise "L" type is assumed as default.
 *
 * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else.
 */

int checkboard (void)
{
	DECLARE_GLOBAL_DATA_PTR;

	unsigned char *s = getenv ("serial#");

	puts ("Board: ");

	if (!s || strncmp (s, "TQM8", 4)) {
		puts ("### No HW ID - assuming TQM8xxL\n");
		return (0);
	}

	if ((*(s + 6) == 'L')) {	/* a TQM8xxL type */
		gd->board_type = 'L';
	}

	if ((*(s + 6) == 'M')) {	/* a TQM8xxM type */
		gd->board_type = 'M';
	}

	for (; *s; ++s) {
		if (*s == ' ')
			break;
		putc (*s);
	}
	putc ('\n');

	return (0);
}

/* ------------------------------------------------------------------------- */

long int initdram (int board_type)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	long int size8, size9;
	long int size_b0 = 0;
	long int size_b1 = 0;

	upmconfig (UPMA, (uint *) sdram_table,
			   sizeof (sdram_table) / sizeof (uint));

	/*
	 * Preliminary prescaler for refresh (depends on number of
	 * banks): This value is selected for four cycles every 62.4 us
	 * with two SDRAM banks or four cycles every 31.2 us with one
	 * bank. It will be adjusted after memory sizing.
	 */
	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;

	/*
	 * The following value is used as an address (i.e. opcode) for
	 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
	 * the port size is 32bit the SDRAM does NOT "see" the lower two
	 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
	 * MICRON SDRAMs:
	 * ->    0 00 010 0 010
	 *       |  |   | |   +- Burst Length = 4
	 *       |  |   | +----- Burst Type   = Sequential
	 *       |  |   +------- CAS Latency  = 2
	 *       |  +----------- Operating Mode = Standard
	 *       +-------------- Write Burst Mode = Programmed Burst Length
	 */
	memctl->memc_mar = 0x00000088;

	/*
	 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
	 * preliminary addresses - these have to be modified after the
	 * SDRAM size has been determined.
	 */
	memctl->memc_or2 = CFG_OR2_PRELIM;
	memctl->memc_br2 = CFG_BR2_PRELIM;

#ifndef	CONFIG_CAN_DRIVER
	if ((board_type != 'L') &&
	    (board_type != 'M') ) {	/* "L" and "M" type boards have only one bank SDRAM */
		memctl->memc_or3 = CFG_OR3_PRELIM;
		memctl->memc_br3 = CFG_BR3_PRELIM;
	}
#endif							/* CONFIG_CAN_DRIVER */

	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */

	udelay (200);

	/* perform SDRAM initializsation sequence */

	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 0 */
	udelay (1);
	memctl->memc_mcr = 0x80004230;	/* SDRAM bank 0 - execute twice */
	udelay (1);

#ifndef	CONFIG_CAN_DRIVER
	if ((board_type != 'L') &&
	    (board_type != 'M') ) {	/* "L" and "M" type boards have only one bank SDRAM */
		memctl->memc_mcr = 0x80006105;	/* SDRAM bank 1 */
		udelay (1);
		memctl->memc_mcr = 0x80006230;	/* SDRAM bank 1 - execute twice */
		udelay (1);
	}
#endif							/* CONFIG_CAN_DRIVER */

	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */

	udelay (1000);

	/*
	 * Check Bank 0 Memory Size for re-configuration
	 *
	 * try 8 column mode
	 */
	size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE2_PRELIM,
					   SDRAM_MAX_SIZE);
	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);

	udelay (1000);

	/*
	 * try 9 column mode
	 */
	size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE2_PRELIM,
					   SDRAM_MAX_SIZE);
	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);

	if (size8 < size9) {		/* leave configuration at 9 columns */
		size_b0 = size9;
	} else {					/* back to 8 columns            */
		size_b0 = size8;
		memctl->memc_mamr = CFG_MAMR_8COL;
		udelay (500);
	}
	debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);

#ifndef	CONFIG_CAN_DRIVER
	if ((board_type != 'L') &&
	    (board_type != 'M') ) {	/* "L" and "M" type boards have only one bank SDRAM */
		/*
		 * Check Bank 1 Memory Size
		 * use current column settings
		 * [9 column SDRAM may also be used in 8 column mode,
		 *  but then only half the real size will be used.]
		 */
		size_b1 = dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE3_PRELIM,
				     SDRAM_MAX_SIZE);
		debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
	} else {
		size_b1 = 0;
	}
#endif	/* CONFIG_CAN_DRIVER */

	udelay (1000);

	/*
	 * Adjust refresh rate depending on SDRAM type, both banks
	 * For types > 128 MBit leave it at the current (fast) rate
	 */
	if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
		/* reduce to 15.6 us (62.4 us / quad) */
		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
		udelay (1000);
	}

	/*
	 * Final mapping: map bigger bank first
	 */
	if (size_b1 > size_b0) {	/* SDRAM Bank 1 is bigger - map first   */

		memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
		memctl->memc_br3 =
				(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;

		if (size_b0 > 0) {
			/*
			 * Position Bank 0 immediately above Bank 1
			 */
			memctl->memc_or2 =
					((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
			memctl->memc_br2 =
					((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
					+ size_b1;
		} else {
			unsigned long reg;

			/*
			 * No bank 0
			 *
			 * invalidate bank
			 */
			memctl->memc_br2 = 0;

			/* adjust refresh rate depending on SDRAM type, one bank */
			reg = memctl->memc_mptpr;
			reg >>= 1;			/* reduce to CFG_MPTPR_1BK_8K / _4K */
			memctl->memc_mptpr = reg;
		}

	} else {					/* SDRAM Bank 0 is bigger - map first   */

		memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
		memctl->memc_br2 =
				(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;

		if (size_b1 > 0) {
			/*
			 * Position Bank 1 immediately above Bank 0
			 */
			memctl->memc_or3 =
					((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
			memctl->memc_br3 =
					((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
					+ size_b0;
		} else {
			unsigned long reg;

#ifndef	CONFIG_CAN_DRIVER
			/*
			 * No bank 1
			 *
			 * invalidate bank
			 */
			memctl->memc_br3 = 0;
#endif							/* CONFIG_CAN_DRIVER */

			/* adjust refresh rate depending on SDRAM type, one bank */
			reg = memctl->memc_mptpr;
			reg >>= 1;			/* reduce to CFG_MPTPR_1BK_8K / _4K */
			memctl->memc_mptpr = reg;
		}
	}

	udelay (10000);

#ifdef	CONFIG_CAN_DRIVER
	/* Initialize OR3 / BR3 */
	memctl->memc_or3 = CFG_OR3_CAN;
	memctl->memc_br3 = CFG_BR3_CAN;

	/* Initialize MBMR */
	memctl->memc_mbmr = MBMR_GPL_B4DIS;	/* GPL_B4 ouput line Disable */

	/* Initialize UPMB for CAN: single read */
	memctl->memc_mdr = 0xFFFFC004;
	memctl->memc_mcr = 0x0100 | UPMB;

	memctl->memc_mdr = 0x0FFFD004;
	memctl->memc_mcr = 0x0101 | UPMB;

	memctl->memc_mdr = 0x0FFFC000;
	memctl->memc_mcr = 0x0102 | UPMB;

	memctl->memc_mdr = 0x3FFFC004;
	memctl->memc_mcr = 0x0103 | UPMB;

	memctl->memc_mdr = 0xFFFFDC05;
	memctl->memc_mcr = 0x0104 | UPMB;

	/* Initialize UPMB for CAN: single write */
	memctl->memc_mdr = 0xFFFCC004;
	memctl->memc_mcr = 0x0118 | UPMB;

	memctl->memc_mdr = 0xCFFCD004;
	memctl->memc_mcr = 0x0119 | UPMB;

	memctl->memc_mdr = 0x0FFCC000;
	memctl->memc_mcr = 0x011A | UPMB;

	memctl->memc_mdr = 0x7FFCC004;
	memctl->memc_mcr = 0x011B | UPMB;

	memctl->memc_mdr = 0xFFFDCC05;
	memctl->memc_mcr = 0x011C | UPMB;
#endif							/* CONFIG_CAN_DRIVER */

#ifdef	CONFIG_ISP1362_USB
	/* Initialize OR5 / BR5 */
	memctl->memc_or5 = CFG_OR5_ISP1362;
	memctl->memc_br5 = CFG_BR5_ISP1362;
#endif							/* CONFIG_ISP1362_USB */


	return (size_b0 + size_b1);
}

/* ------------------------------------------------------------------------- */

/*
 * Check memory range for valid RAM. A simple memory test determines
 * the actually available RAM size between addresses `base' and
 * `base + maxsize'. Some (not all) hardware errors are detected:
 * - short between address lines
 * - short between data lines
 */

static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;

	memctl->memc_mamr = mamr_value;

	return (get_ram_size(base, maxsize));
}

/* ------------------------------------------------------------------------- */

#ifdef CONFIG_PS2MULT

#ifdef CONFIG_BMS2003
#define BASE_BAUD ( 1843200 / 16 )
struct serial_state rs_table[] = {
	{ BASE_BAUD, 4,  (void*)0xec140000 },
	{ BASE_BAUD, 2,  (void*)0xec150000 },
	{ BASE_BAUD, 6,  (void*)0xec160000 },
	{ BASE_BAUD, 10, (void*)0xec170000 },
};

#ifdef CONFIG_BOARD_EARLY_INIT_R
int board_early_init_r (void)
{
	ps2mult_early_init();
	return (0);
}
#endif
#endif /* CONFIG_BMS2003 */

#endif /* CONFIG_PS2MULT */

/* ------------------------------------------------------------------------- */
#ifdef CONFIG_BMS2003

int misc_init_r (void)
{
#ifdef CONFIG_IDE_LED
	volatile immap_t *immap = (immap_t *) CFG_IMMR;

	/* Configure PA15 as output port */
	immap->im_ioport.iop_padir |= 0x0001;
	immap->im_ioport.iop_paodr |= 0x0001;
	immap->im_ioport.iop_papar &= ~0x0001;
	immap->im_ioport.iop_padat &= ~0x0001;	/* turn it off */
#endif
	return (0);
}

#ifdef CONFIG_IDE_LED
void ide_led (uchar led, uchar status)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;

	/* We have one led for both pcmcia slots */
	if (status) {				/* led on */
		immap->im_ioport.iop_padat |= 0x0001;
	} else {
		immap->im_ioport.iop_padat &= ~0x0001;
	}
}
#endif

#endif /* CONFIG_BMS2003 */
/* ------------------------------------------------------------------------- */
Commit	Line	Data
f8cac651	1	/*
d4ca31c4	2	* (C) Copyright 2000-2004
f8cac651 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
d4ca31c4 WD	24	#if 0
	25	#define DEBUG
	26	#endif
	27
f8cac651 WD	28	#include <common.h>
f8cac651 WD	29	#include <mpc8xx.h>
1c43771b WD	30	#ifdef CONFIG_PS2MULT
	31	#include <ps2mult.h>
	32	#endif
f8cac651 WD	33
	34	/* ------------------------------------------------------------------------- */
	35
	36	static long int dram_size (long int, long int *, long int);
	37
	38	/* ------------------------------------------------------------------------- */
	39
	40	#define _NOT_USED_ 0xFFFFFFFF
	41
	42	const uint sdram_table[] =
	43	{
	44	/*
	45	* Single Read. (Offset 0 in UPMA RAM)
	46	*/
	47	0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
	48	0x1FF5FC47, /* last */
	49	/*
	50	* SDRAM Initialization (offset 5 in UPMA RAM)
	51	*
	52	* This is no UPM entry point. The following definition uses
	53	* the remaining space to establish an initialization
	54	* sequence, which is executed by a RUN command.
	55	*
	56	*/
	57	0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
	58	/*
	59	* Burst Read. (Offset 8 in UPMA RAM)
	60	*/
	61	0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
	62	0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
	63	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	64	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	65	/*
	66	* Single Write. (Offset 18 in UPMA RAM)
	67	*/
	68	0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
	69	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	70	/*
	71	* Burst Write. (Offset 20 in UPMA RAM)
	72	*/
	73	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
	74	0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
	75	_NOT_USED_,
	76	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	77	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	78	/*
	79	* Refresh (Offset 30 in UPMA RAM)
	80	*/
	81	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	82	0xFFFFFC84, 0xFFFFFC07, /* last */
	83	_NOT_USED_, _NOT_USED_,
	84	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	85	/*
	86	* Exception. (Offset 3c in UPMA RAM)
	87	*/
	88	0x7FFFFC07, /* last */
	89	_NOT_USED_, _NOT_USED_, _NOT_USED_,
	90	};
	91
	92	/* ------------------------------------------------------------------------- */
	93
	94
	95	/*
	96	* Check Board Identity:
97	*
98	* Test TQ ID string (TQM8xx...)
99	* If present, check for "L" type (no second DRAM bank),
100	* otherwise "L" type is assumed as default.
101	*
d4ca31c4	102	* Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else.
f8cac651 WD	103	*/
	104
	105	int checkboard (void)
	106	{
	107	DECLARE_GLOBAL_DATA_PTR;
	108
	109	unsigned char *s = getenv ("serial#");
	110
	111	puts ("Board: ");
	112
	113	if (!s \|\| strncmp (s, "TQM8", 4)) {
	114	puts ("### No HW ID - assuming TQM8xxL\n");
	115	return (0);
	116	}
	117
	118	if (((s + 6) == 'L')) { / a TQM8xxL type */
	119	gd->board_type = 'L';
	120	}
	121
d4ca31c4 WD	122	if (((s + 6) == 'M')) { / a TQM8xxM type */
	123	gd->board_type = 'M';
	124	}
	125
f8cac651 WD	126	for (; *s; ++s) {
	127	if (*s == ' ')
	128	break;
	129	putc (*s);
	130	}
	131	putc ('\n');
	132
	133	return (0);
	134	}
	135
	136	/* ------------------------------------------------------------------------- */
	137
	138	long int initdram (int board_type)
	139	{
	140	volatile immap_t immap = (immap_t ) CFG_IMMR;
	141	volatile memctl8xx_t *memctl = &immap->im_memctl;
	142	long int size8, size9;
	143	long int size_b0 = 0;
	144	long int size_b1 = 0;
	145
	146	upmconfig (UPMA, (uint *) sdram_table,
	147	sizeof (sdram_table) / sizeof (uint));
	148
	149	/*
	150	* Preliminary prescaler for refresh (depends on number of
	151	* banks): This value is selected for four cycles every 62.4 us
	152	* with two SDRAM banks or four cycles every 31.2 us with one
	153	* bank. It will be adjusted after memory sizing.
	154	*/
	155	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
	156
	157	/*
	158	* The following value is used as an address (i.e. opcode) for
	159	* the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
	160	* the port size is 32bit the SDRAM does NOT "see" the lower two
	161	* address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
	162	* MICRON SDRAMs:
	163	* -> 0 00 010 0 010
	164	* \| \| \| \| +- Burst Length = 4
	165	* \| \| \| +----- Burst Type = Sequential
	166	* \| \| +------- CAS Latency = 2
	167	* \| +----------- Operating Mode = Standard
	168	* +-------------- Write Burst Mode = Programmed Burst Length
	169	*/
	170	memctl->memc_mar = 0x00000088;
	171
	172	/*
	173	* Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
	174	* preliminary addresses - these have to be modified after the
	175	* SDRAM size has been determined.
	176	*/
	177	memctl->memc_or2 = CFG_OR2_PRELIM;
	178	memctl->memc_br2 = CFG_BR2_PRELIM;
	179
	180	#ifndef CONFIG_CAN_DRIVER
d4ca31c4 WD	181	if ((board_type != 'L') &&
d4ca31c4 WD	182	(board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
f8cac651 WD	183	memctl->memc_or3 = CFG_OR3_PRELIM;
	184	memctl->memc_br3 = CFG_BR3_PRELIM;
	185	}
	186	#endif /* CONFIG_CAN_DRIVER */
	187
	188	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
	189
	190	udelay (200);
	191
	192	/* perform SDRAM initializsation sequence */
	193
	194	memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
	195	udelay (1);
	196	memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
	197	udelay (1);
	198
	199	#ifndef CONFIG_CAN_DRIVER
d4ca31c4 WD	200	if ((board_type != 'L') &&
d4ca31c4 WD	201	(board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
f8cac651 WD	202	memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
	203	udelay (1);
	204	memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
	205	udelay (1);
	206	}
	207	#endif /* CONFIG_CAN_DRIVER */
	208
	209	memctl->memc_mamr \|= MAMR_PTAE; /* enable refresh */
	210
	211	udelay (1000);
	212
	213	/*
	214	* Check Bank 0 Memory Size for re-configuration
	215	*
	216	* try 8 column mode
	217	*/
	218	size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE2_PRELIM,
	219	SDRAM_MAX_SIZE);
d4ca31c4	220	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
f8cac651 WD	221
	222	udelay (1000);
	223
	224	/*
	225	* try 9 column mode
	226	*/
	227	size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE2_PRELIM,
	228	SDRAM_MAX_SIZE);
d4ca31c4	229	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
f8cac651 WD	230
	231	if (size8 < size9) { /* leave configuration at 9 columns */
	232	size_b0 = size9;
f8cac651 WD	233	} else { /* back to 8 columns */
	234	size_b0 = size8;
	235	memctl->memc_mamr = CFG_MAMR_8COL;
	236	udelay (500);
f8cac651	237	}
d4ca31c4	238	debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
f8cac651 WD	239
f8cac651 WD	240	#ifndef CONFIG_CAN_DRIVER
d4ca31c4 WD	241	if ((board_type != 'L') &&
d4ca31c4 WD	242	(board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
f8cac651 WD	243	/*
	244	* Check Bank 1 Memory Size
	245	* use current column settings
	246	* [9 column SDRAM may also be used in 8 column mode,
	247	* but then only half the real size will be used.]
	248	*/
d4ca31c4 WD	249	size_b1 = dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE3_PRELIM,
	250	SDRAM_MAX_SIZE);
	251	debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
f8cac651 WD	252	} else {
	253	size_b1 = 0;
	254	}
d4ca31c4	255	#endif /* CONFIG_CAN_DRIVER */
f8cac651 WD	256
	257	udelay (1000);
	258
	259	/*
	260	* Adjust refresh rate depending on SDRAM type, both banks
	261	* For types > 128 MBit leave it at the current (fast) rate
	262	*/
	263	if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
	264	/* reduce to 15.6 us (62.4 us / quad) */
	265	memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
	266	udelay (1000);
	267	}
	268
	269	/*
	270	* Final mapping: map bigger bank first
	271	*/
	272	if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
	273
	274	memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) \| CFG_OR_TIMING_SDRAM;
	275	memctl->memc_br3 =
	276	(CFG_SDRAM_BASE & BR_BA_MSK) \| BR_MS_UPMA \| BR_V;
	277
	278	if (size_b0 > 0) {
	279	/*
	280	* Position Bank 0 immediately above Bank 1
	281	*/
	282	memctl->memc_or2 =
	283	((-size_b0) & 0xFFFF0000) \| CFG_OR_TIMING_SDRAM;
	284	memctl->memc_br2 =
	285	((CFG_SDRAM_BASE & BR_BA_MSK) \| BR_MS_UPMA \| BR_V)
	286	+ size_b1;
	287	} else {
	288	unsigned long reg;
	289
	290	/*
	291	* No bank 0
	292	*
	293	* invalidate bank
	294	*/
	295	memctl->memc_br2 = 0;
	296
	297	/* adjust refresh rate depending on SDRAM type, one bank */
	298	reg = memctl->memc_mptpr;
	299	reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
	300	memctl->memc_mptpr = reg;
	301	}
	302
	303	} else { /* SDRAM Bank 0 is bigger - map first */
	304
	305	memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) \| CFG_OR_TIMING_SDRAM;
	306	memctl->memc_br2 =
	307	(CFG_SDRAM_BASE & BR_BA_MSK) \| BR_MS_UPMA \| BR_V;
	308
	309	if (size_b1 > 0) {
	310	/*
	311	* Position Bank 1 immediately above Bank 0
	312	*/
	313	memctl->memc_or3 =
	314	((-size_b1) & 0xFFFF0000) \| CFG_OR_TIMING_SDRAM;
	315	memctl->memc_br3 =
	316	((CFG_SDRAM_BASE & BR_BA_MSK) \| BR_MS_UPMA \| BR_V)
	317	+ size_b0;
	318	} else {
	319	unsigned long reg;
320
321	#ifndef CONFIG_CAN_DRIVER
322	/*
323	* No bank 1
324	*
325	* invalidate bank
326	*/
327	memctl->memc_br3 = 0;
328	#endif /* CONFIG_CAN_DRIVER */
329
330	/* adjust refresh rate depending on SDRAM type, one bank */
331	reg = memctl->memc_mptpr;
332	reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
333	memctl->memc_mptpr = reg;
334	}
335	}
336
337	udelay (10000);
338
339	#ifdef CONFIG_CAN_DRIVER
340	/* Initialize OR3 / BR3 */
341	memctl->memc_or3 = CFG_OR3_CAN;
342	memctl->memc_br3 = CFG_BR3_CAN;
343
344	/* Initialize MBMR */
fd3103bb	345	memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
f8cac651 WD	346
	347	/* Initialize UPMB for CAN: single read */
	348	memctl->memc_mdr = 0xFFFFC004;
	349	memctl->memc_mcr = 0x0100 \| UPMB;
	350
	351	memctl->memc_mdr = 0x0FFFD004;
	352	memctl->memc_mcr = 0x0101 \| UPMB;
	353
	354	memctl->memc_mdr = 0x0FFFC000;
	355	memctl->memc_mcr = 0x0102 \| UPMB;
	356
	357	memctl->memc_mdr = 0x3FFFC004;
	358	memctl->memc_mcr = 0x0103 \| UPMB;
	359
	360	memctl->memc_mdr = 0xFFFFDC05;
	361	memctl->memc_mcr = 0x0104 \| UPMB;
	362
	363	/* Initialize UPMB for CAN: single write */
	364	memctl->memc_mdr = 0xFFFCC004;
	365	memctl->memc_mcr = 0x0118 \| UPMB;
	366
	367	memctl->memc_mdr = 0xCFFCD004;
	368	memctl->memc_mcr = 0x0119 \| UPMB;
	369
	370	memctl->memc_mdr = 0x0FFCC000;
	371	memctl->memc_mcr = 0x011A \| UPMB;
	372
	373	memctl->memc_mdr = 0x7FFCC004;
	374	memctl->memc_mcr = 0x011B \| UPMB;
	375
	376	memctl->memc_mdr = 0xFFFDCC05;
	377	memctl->memc_mcr = 0x011C \| UPMB;
	378	#endif /* CONFIG_CAN_DRIVER */
	379
bdccc4fe WD	380	#ifdef CONFIG_ISP1362_USB
	381	/* Initialize OR5 / BR5 */
	382	memctl->memc_or5 = CFG_OR5_ISP1362;
	383	memctl->memc_br5 = CFG_BR5_ISP1362;
	384	#endif /* CONFIG_ISP1362_USB */
42d1f039 WD	385
42d1f039 WD	386
f8cac651 WD	387	return (size_b0 + size_b1);
	388	}
	389
	390	/* ------------------------------------------------------------------------- */
	391
	392	/*
	393	* Check memory range for valid RAM. A simple memory test determines
	394	* the actually available RAM size between addresses `base' and
	395	* `base + maxsize'. Some (not all) hardware errors are detected:
	396	* - short between address lines
	397	* - short between data lines
	398	*/
	399
d4ca31c4	400	static long int dram_size (long int mamr_value, long int *base, long int maxsize)
f8cac651 WD	401	{
	402	volatile immap_t immap = (immap_t ) CFG_IMMR;
	403	volatile memctl8xx_t *memctl = &immap->im_memctl;
f8cac651 WD	404
	405	memctl->memc_mamr = mamr_value;
	406
c83bf6a2	407	return (get_ram_size(base, maxsize));
f8cac651 WD	408	}
	409
	410	/* ------------------------------------------------------------------------- */
1c43771b WD	411
	412	#ifdef CONFIG_PS2MULT
	413
	414	#ifdef CONFIG_BMS2003
	415	#define BASE_BAUD ( 1843200 / 16 )
	416	struct serial_state rs_table[] = {
	417	{ BASE_BAUD, 4, (void*)0xec140000 },
	418	{ BASE_BAUD, 2, (void*)0xec150000 },
	419	{ BASE_BAUD, 6, (void*)0xec160000 },
	420	{ BASE_BAUD, 10, (void*)0xec170000 },
	421	};
c837dcb1 WD	422
	423	#ifdef CONFIG_BOARD_EARLY_INIT_R
	424	int board_early_init_r (void)
	425	{
	426	ps2mult_early_init();
	427	return (0);
	428	}
	429	#endif
1c43771b WD	430	#endif /* CONFIG_BMS2003 */
	431
	432	#endif /* CONFIG_PS2MULT */
	433
	434	/* ------------------------------------------------------------------------- */
	435	#ifdef CONFIG_BMS2003
	436
	437	int misc_init_r (void)
	438	{
	439	#ifdef CONFIG_IDE_LED
	440	volatile immap_t immap = (immap_t ) CFG_IMMR;
	441
	442	/* Configure PA15 as output port */
	443	immap->im_ioport.iop_padir \|= 0x0001;
	444	immap->im_ioport.iop_paodr \|= 0x0001;
	445	immap->im_ioport.iop_papar &= ~0x0001;
	446	immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */
	447	#endif
	448	return (0);
	449	}
	450
	451	#ifdef CONFIG_IDE_LED
	452	void ide_led (uchar led, uchar status)
	453	{
	454	volatile immap_t immap = (immap_t ) CFG_IMMR;
	455
	456	/* We have one led for both pcmcia slots */
	457	if (status) { /* led on */
	458	immap->im_ioport.iop_padat \|= 0x0001;
	459	} else {
	460	immap->im_ioport.iop_padat &= ~0x0001;
	461	}
	462	}
	463	#endif
	464
	465	#endif /* CONFIG_BMS2003 */
	466	/* ------------------------------------------------------------------------- */