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Commit | Line | Data |
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f8f8acd7 SB |
1 | /* |
2 | * (C) Copyright 2010 | |
3 | * Stefano Babic, DENX Software Engineering, sbabic@denx.de. | |
4 | * | |
5 | * (C) Copyright 2009 Freescale Semiconductor, Inc. | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #include <common.h> | |
27 | #include <asm/io.h> | |
28 | #include <asm/arch/imx-regs.h> | |
f8f8acd7 | 29 | #include <asm/arch/crm_regs.h> |
a2ac1b3a | 30 | #include <asm/arch/clock.h> |
6ea4217f | 31 | #include <asm/arch/iomux-mx51.h> |
4c0443c4 | 32 | #include <asm/gpio.h> |
f8f8acd7 | 33 | #include <asm/arch/sys_proto.h> |
f8f8acd7 SB |
34 | #include <i2c.h> |
35 | #include <mmc.h> | |
c7336815 | 36 | #include <power/pmic.h> |
f8f8acd7 SB |
37 | #include <fsl_esdhc.h> |
38 | #include <fsl_pmic.h> | |
39 | #include <mc13892.h> | |
a0152c4b | 40 | #include <linux/fb.h> |
f8f8acd7 | 41 | |
02ae1a18 MV |
42 | #include <ipu_pixfmt.h> |
43 | ||
f8f8acd7 SB |
44 | DECLARE_GLOBAL_DATA_PTR; |
45 | ||
08fd6a35 | 46 | static struct fb_videomode const nec_nl6448bc26_09c = { |
a0152c4b SB |
47 | "NEC_NL6448BC26-09C", |
48 | 60, /* Refresh */ | |
49 | 640, /* xres */ | |
50 | 480, /* yres */ | |
51 | 37650, /* pixclock = 26.56Mhz */ | |
52 | 48, /* left margin */ | |
53 | 16, /* right margin */ | |
54 | 31, /* upper margin */ | |
55 | 12, /* lower margin */ | |
56 | 96, /* hsync-len */ | |
57 | 2, /* vsync-len */ | |
58 | 0, /* sync */ | |
59 | FB_VMODE_NONINTERLACED, /* vmode */ | |
60 | 0, /* flag */ | |
61 | }; | |
62 | ||
c08f68c2 FE |
63 | #ifdef CONFIG_HW_WATCHDOG |
64 | #include <watchdog.h> | |
f8f8acd7 SB |
65 | void hw_watchdog_reset(void) |
66 | { | |
67 | int val; | |
68 | ||
69 | /* toggle watchdog trigger pin */ | |
6ea4217f | 70 | val = gpio_get_value(IMX_GPIO_NR(3, 2)); |
f8f8acd7 | 71 | val = val ? 0 : 1; |
6ea4217f | 72 | gpio_set_value(IMX_GPIO_NR(3, 2), val); |
f8f8acd7 SB |
73 | } |
74 | #endif | |
75 | ||
76 | static void init_drive_strength(void) | |
77 | { | |
6ea4217f BT |
78 | static const iomux_v3_cfg_t ddr_pads[] = { |
79 | NEW_PAD_CTRL(MX51_GRP_PKEDDR, 0), | |
80 | NEW_PAD_CTRL(MX51_GRP_PKEADDR, PAD_CTL_PKE), | |
81 | NEW_PAD_CTRL(MX51_GRP_DDRAPKS, 0), | |
82 | NEW_PAD_CTRL(MX51_GRP_DDRAPUS, PAD_CTL_PUS_100K_UP), | |
83 | NEW_PAD_CTRL(MX51_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST), | |
84 | NEW_PAD_CTRL(MX51_GRP_DDR_A0, PAD_CTL_DSE_HIGH), | |
85 | NEW_PAD_CTRL(MX51_GRP_DDR_A1, PAD_CTL_DSE_HIGH), | |
86 | NEW_PAD_CTRL(MX51_PAD_DRAM_RAS__DRAM_RAS, | |
87 | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), | |
88 | NEW_PAD_CTRL(MX51_PAD_DRAM_CAS__DRAM_CAS, | |
89 | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), | |
90 | NEW_PAD_CTRL(MX51_GRP_PKEDDR, PAD_CTL_PKE), | |
91 | NEW_PAD_CTRL(MX51_GRP_DDRPKS, 0), | |
92 | NEW_PAD_CTRL(MX51_GRP_HYSDDR0, 0), | |
93 | NEW_PAD_CTRL(MX51_GRP_HYSDDR1, 0), | |
94 | NEW_PAD_CTRL(MX51_GRP_HYSDDR2, 0), | |
95 | NEW_PAD_CTRL(MX51_GRP_HYSDDR3, 0), | |
96 | NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B0, PAD_CTL_SRE_FAST), | |
97 | NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B1, PAD_CTL_SRE_FAST), | |
98 | NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B2, PAD_CTL_SRE_FAST), | |
99 | NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B4, PAD_CTL_SRE_FAST), | |
100 | NEW_PAD_CTRL(MX51_GRP_DDRPUS, PAD_CTL_PUS_100K_UP), | |
101 | NEW_PAD_CTRL(MX51_GRP_INMODE1, 0), | |
102 | NEW_PAD_CTRL(MX51_GRP_DRAM_B0, PAD_CTL_DSE_MED), | |
103 | NEW_PAD_CTRL(MX51_GRP_DRAM_B1, PAD_CTL_DSE_MED), | |
104 | NEW_PAD_CTRL(MX51_GRP_DRAM_B2, PAD_CTL_DSE_MED), | |
105 | NEW_PAD_CTRL(MX51_GRP_DRAM_B4, PAD_CTL_DSE_MED), | |
106 | ||
107 | NEW_PAD_CTRL(MX51_PAD_DRAM_SDWE__DRAM_SDWE, MX51_GPIO_PAD_CTRL), | |
108 | NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0, | |
109 | MX51_GPIO_PAD_CTRL), | |
110 | NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1, | |
111 | MX51_GPIO_PAD_CTRL), | |
112 | NEW_PAD_CTRL(MX51_PAD_DRAM_SDCLK__DRAM_SDCLK, | |
113 | MX51_GPIO_PAD_CTRL), | |
114 | NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS0__DRAM_SDQS0, | |
115 | MX51_GPIO_PAD_CTRL), | |
116 | NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS1__DRAM_SDQS1, | |
117 | MX51_GPIO_PAD_CTRL), | |
118 | NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS2__DRAM_SDQS2, | |
119 | MX51_GPIO_PAD_CTRL), | |
120 | NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS3__DRAM_SDQS3, | |
121 | MX51_GPIO_PAD_CTRL), | |
122 | NEW_PAD_CTRL(MX51_PAD_DRAM_CS0__DRAM_CS0, MX51_GPIO_PAD_CTRL), | |
123 | NEW_PAD_CTRL(MX51_PAD_DRAM_CS1__DRAM_CS1, MX51_GPIO_PAD_CTRL), | |
124 | NEW_PAD_CTRL(MX51_PAD_DRAM_DQM0__DRAM_DQM0, MX51_GPIO_PAD_CTRL), | |
125 | NEW_PAD_CTRL(MX51_PAD_DRAM_DQM1__DRAM_DQM1, MX51_GPIO_PAD_CTRL), | |
126 | NEW_PAD_CTRL(MX51_PAD_DRAM_DQM2__DRAM_DQM2, MX51_GPIO_PAD_CTRL), | |
127 | NEW_PAD_CTRL(MX51_PAD_DRAM_DQM3__DRAM_DQM3, MX51_GPIO_PAD_CTRL), | |
128 | }; | |
129 | ||
130 | imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads)); | |
f8f8acd7 SB |
131 | } |
132 | ||
f8f8acd7 SB |
133 | int dram_init(void) |
134 | { | |
f8f8acd7 SB |
135 | gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, |
136 | PHYS_SDRAM_1_SIZE); | |
f8f8acd7 SB |
137 | |
138 | return 0; | |
139 | } | |
140 | ||
141 | static void setup_weim(void) | |
142 | { | |
143 | struct weim *pweim = (struct weim *)WEIM_BASE_ADDR; | |
144 | ||
ea113823 FE |
145 | pweim->cs0gcr1 = 0x004100b9; |
146 | pweim->cs0gcr2 = 0x00000001; | |
147 | pweim->cs0rcr1 = 0x0a018000; | |
148 | pweim->cs0rcr2 = 0; | |
149 | pweim->cs0wcr1 = 0x0704a240; | |
f8f8acd7 SB |
150 | } |
151 | ||
152 | static void setup_uart(void) | |
153 | { | |
6ea4217f BT |
154 | static const iomux_v3_cfg_t uart_pads[] = { |
155 | MX51_PAD_EIM_D25__UART3_RXD, /* console RX */ | |
156 | MX51_PAD_EIM_D26__UART3_TXD, /* console TX */ | |
157 | }; | |
158 | ||
159 | imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); | |
f8f8acd7 SB |
160 | } |
161 | ||
162 | #ifdef CONFIG_MXC_SPI | |
163 | void spi_io_init(void) | |
164 | { | |
6ea4217f BT |
165 | static const iomux_v3_cfg_t spi_pads[] = { |
166 | NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS | | |
167 | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), | |
168 | NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS | | |
169 | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), | |
170 | NEW_PAD_CTRL(MX51_PAD_CSPI1_SS0__ECSPI1_SS0, PAD_CTL_HYS | | |
171 | PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), | |
172 | NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1, PAD_CTL_HYS | | |
173 | PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), | |
174 | NEW_PAD_CTRL(MX51_PAD_DI1_PIN11__ECSPI1_SS2, PAD_CTL_HYS | | |
175 | PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), | |
176 | NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS | | |
177 | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), | |
178 | }; | |
179 | ||
180 | imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads)); | |
f8f8acd7 SB |
181 | } |
182 | ||
183 | static void reset_peripherals(int reset) | |
184 | { | |
6ea4217f BT |
185 | #ifdef CONFIG_VISION2_HW_1_0 |
186 | static const iomux_v3_cfg_t fec_cfg_pads[] = { | |
187 | /* RXD1 */ | |
188 | NEW_PAD_CTRL(MX51_PAD_EIM_EB3__GPIO2_23, NO_PAD_CTRL), | |
189 | /* RXD2 */ | |
190 | NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, NO_PAD_CTRL), | |
191 | /* RXD3 */ | |
192 | NEW_PAD_CTRL(MX51_PAD_EIM_CS3__GPIO2_28, NO_PAD_CTRL), | |
193 | /* RXER */ | |
194 | NEW_PAD_CTRL(MX51_PAD_EIM_CS4__GPIO2_29, NO_PAD_CTRL), | |
195 | /* COL */ | |
196 | NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__GPIO3_10, NO_PAD_CTRL), | |
197 | /* RCLK */ | |
198 | NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__GPIO3_11, NO_PAD_CTRL), | |
199 | /* RXD0 */ | |
200 | NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, NO_PAD_CTRL), | |
201 | }; | |
202 | ||
203 | static const iomux_v3_cfg_t fec_pads[] = { | |
204 | NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2), | |
205 | NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2), | |
206 | NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2), | |
207 | MX51_PAD_NANDF_D9__FEC_RDATA0, | |
208 | NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4), | |
209 | MX51_PAD_EIM_CS4__FEC_RX_ER, | |
210 | NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4), | |
211 | }; | |
212 | #endif | |
213 | ||
f8f8acd7 SB |
214 | if (reset) { |
215 | ||
216 | /* reset_n is on NANDF_D15 */ | |
6ea4217f | 217 | gpio_direction_output(IMX_GPIO_NR(3, 25), 0); |
f8f8acd7 SB |
218 | |
219 | #ifdef CONFIG_VISION2_HW_1_0 | |
220 | /* | |
221 | * set FEC Configuration lines | |
222 | * set levels of FEC config lines | |
223 | */ | |
6ea4217f BT |
224 | gpio_direction_output(IMX_GPIO_NR(3, 11), 0); |
225 | gpio_direction_output(IMX_GPIO_NR(3, 10), 1); | |
226 | gpio_direction_output(IMX_GPIO_NR(3, 31), 1); | |
f8f8acd7 SB |
227 | |
228 | /* set direction of FEC config lines */ | |
6ea4217f BT |
229 | gpio_direction_output(IMX_GPIO_NR(2, 27), 0); |
230 | gpio_direction_output(IMX_GPIO_NR(2, 28), 0); | |
231 | gpio_direction_output(IMX_GPIO_NR(2, 29), 0); | |
232 | gpio_direction_output(IMX_GPIO_NR(2, 23), 1); | |
233 | ||
234 | imx_iomux_v3_setup_multiple_pads(fec_cfg_pads, | |
235 | ARRAY_SIZE(fec_cfg_pads)); | |
f8f8acd7 SB |
236 | #endif |
237 | ||
6ea4217f BT |
238 | /* activate reset_n pin */ |
239 | imx_iomux_v3_setup_pad( | |
240 | NEW_PAD_CTRL(MX51_PAD_NANDF_D15__GPIO3_25, | |
241 | PAD_CTL_DSE_MAX)); | |
f8f8acd7 SB |
242 | } else { |
243 | /* set FEC Control lines */ | |
6ea4217f | 244 | gpio_direction_input(IMX_GPIO_NR(3, 25)); |
f8f8acd7 SB |
245 | udelay(500); |
246 | ||
247 | #ifdef CONFIG_VISION2_HW_1_0 | |
6ea4217f BT |
248 | imx_iomux_v3_setup_multiple_pads(fec_pads, |
249 | ARRAY_SIZE(fec_pads)); | |
f8f8acd7 SB |
250 | #endif |
251 | } | |
252 | } | |
253 | ||
254 | static void power_init_mx51(void) | |
255 | { | |
256 | unsigned int val; | |
bac395ee | 257 | struct pmic *p; |
c7336815 | 258 | int ret; |
bac395ee | 259 | |
c7336815 ŁM |
260 | ret = pmic_init(I2C_PMIC); |
261 | if (ret) | |
262 | return; | |
263 | ||
264 | p = pmic_get("FSL_PMIC"); | |
265 | if (!p) | |
266 | return; | |
f8f8acd7 SB |
267 | |
268 | /* Write needed to Power Gate 2 register */ | |
bac395ee | 269 | pmic_reg_read(p, REG_POWER_MISC, &val); |
f8f8acd7 SB |
270 | |
271 | /* enable VCAM with 2.775V to enable read from PMIC */ | |
272 | val = VCAMCONFIG | VCAMEN; | |
bac395ee | 273 | pmic_reg_write(p, REG_MODE_1, val); |
f8f8acd7 SB |
274 | |
275 | /* | |
276 | * Set switchers in Auto in NORMAL mode & STANDBY mode | |
277 | * Setup the switcher mode for SW1 & SW2 | |
278 | */ | |
bac395ee | 279 | pmic_reg_read(p, REG_SW_4, &val); |
f8f8acd7 SB |
280 | val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | |
281 | (SWMODE_MASK << SWMODE2_SHIFT))); | |
282 | val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | | |
283 | (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); | |
bac395ee | 284 | pmic_reg_write(p, REG_SW_4, val); |
f8f8acd7 SB |
285 | |
286 | /* Setup the switcher mode for SW3 & SW4 */ | |
bac395ee | 287 | pmic_reg_read(p, REG_SW_5, &val); |
f8f8acd7 SB |
288 | val &= ~((SWMODE_MASK << SWMODE4_SHIFT) | |
289 | (SWMODE_MASK << SWMODE3_SHIFT)); | |
290 | val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) | | |
291 | (SWMODE_AUTO_AUTO << SWMODE3_SHIFT); | |
bac395ee | 292 | pmic_reg_write(p, REG_SW_5, val); |
f8f8acd7 SB |
293 | |
294 | ||
295 | /* Set VGEN3 to 1.8V, VCAM to 3.0V */ | |
bac395ee | 296 | pmic_reg_read(p, REG_SETTING_0, &val); |
f8f8acd7 SB |
297 | val &= ~(VCAM_MASK | VGEN3_MASK); |
298 | val |= VCAM_3_0; | |
bac395ee | 299 | pmic_reg_write(p, REG_SETTING_0, val); |
f8f8acd7 SB |
300 | |
301 | /* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */ | |
bac395ee | 302 | pmic_reg_read(p, REG_SETTING_1, &val); |
f8f8acd7 SB |
303 | val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); |
304 | val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8; | |
bac395ee | 305 | pmic_reg_write(p, REG_SETTING_1, val); |
f8f8acd7 SB |
306 | |
307 | /* Configure VGEN3 and VCAM regulators to use external PNP */ | |
308 | val = VGEN3CONFIG | VCAMCONFIG; | |
bac395ee | 309 | pmic_reg_write(p, REG_MODE_1, val); |
f8f8acd7 SB |
310 | udelay(200); |
311 | ||
312 | /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ | |
313 | val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | | |
314 | VVIDEOEN | VAUDIOEN | VSDEN; | |
bac395ee | 315 | pmic_reg_write(p, REG_MODE_1, val); |
f8f8acd7 | 316 | |
bac395ee | 317 | pmic_reg_read(p, REG_POWER_CTL2, &val); |
f8f8acd7 | 318 | val |= WDIRESET; |
bac395ee | 319 | pmic_reg_write(p, REG_POWER_CTL2, val); |
f8f8acd7 SB |
320 | |
321 | udelay(2500); | |
322 | ||
323 | } | |
324 | #endif | |
325 | ||
326 | static void setup_gpios(void) | |
327 | { | |
6ea4217f BT |
328 | static const iomux_v3_cfg_t gpio_pads_1[] = { |
329 | NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, PAD_CTL_PKE | | |
330 | PAD_CTL_DSE_MED), /* CAM_SUP_DISn */ | |
331 | NEW_PAD_CTRL(MX51_PAD_DI1_PIN12__GPIO3_1, PAD_CTL_PKE | | |
332 | PAD_CTL_DSE_MED), /* DAB Display EN */ | |
333 | NEW_PAD_CTRL(MX51_PAD_DI1_PIN13__GPIO3_2, PAD_CTL_PKE | | |
334 | PAD_CTL_DSE_MED), /* WDOG_TRIGGER */ | |
335 | }; | |
336 | ||
337 | static const iomux_v3_cfg_t gpio_pads_2[] = { | |
338 | NEW_PAD_CTRL(MX51_PAD_DI1_D0_CS__GPIO3_3, PAD_CTL_PKE | | |
339 | PAD_CTL_DSE_MED), /* Display2 TxEN */ | |
340 | NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4, PAD_CTL_PKE | | |
341 | PAD_CTL_DSE_MED), /* DAB Light EN */ | |
342 | NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIN__GPIO3_5, PAD_CTL_PKE | | |
343 | PAD_CTL_DSE_MED), /* AUDIO_MUTE */ | |
344 | NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIO__GPIO3_6, PAD_CTL_PKE | | |
345 | PAD_CTL_DSE_MED), /* SPARE_OUT */ | |
346 | NEW_PAD_CTRL(MX51_PAD_NANDF_D14__GPIO3_26, PAD_CTL_PKE | | |
347 | PAD_CTL_DSE_MED), /* BEEPER_EN */ | |
348 | NEW_PAD_CTRL(MX51_PAD_NANDF_D13__GPIO3_27, PAD_CTL_PKE | | |
349 | PAD_CTL_DSE_MED), /* POWER_OFF */ | |
350 | NEW_PAD_CTRL(MX51_PAD_NANDF_D10__GPIO3_30, PAD_CTL_PKE | | |
351 | PAD_CTL_DSE_MED), /* FRAM_WE */ | |
352 | NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__GPIO4_26, PAD_CTL_PKE | | |
353 | PAD_CTL_DSE_MED), /* EXPANSION_EN */ | |
354 | MX51_PAD_GPIO1_2__PWM1_PWMO, | |
355 | }; | |
f8f8acd7 | 356 | |
6ea4217f | 357 | unsigned int i; |
f8f8acd7 | 358 | |
6ea4217f | 359 | imx_iomux_v3_setup_multiple_pads(gpio_pads_1, ARRAY_SIZE(gpio_pads_1)); |
f8f8acd7 SB |
360 | |
361 | /* Now we need to trigger the watchdog */ | |
362 | WATCHDOG_RESET(); | |
363 | ||
6ea4217f | 364 | imx_iomux_v3_setup_multiple_pads(gpio_pads_2, ARRAY_SIZE(gpio_pads_2)); |
a0152c4b | 365 | |
f8f8acd7 SB |
366 | /* |
367 | * Set GPIO1_4 to high and output; it is used to reset | |
368 | * the system on reboot | |
369 | */ | |
6ea4217f | 370 | gpio_direction_output(IMX_GPIO_NR(1, 4), 1); |
f8f8acd7 | 371 | |
6ea4217f BT |
372 | gpio_direction_output(IMX_GPIO_NR(1, 7), 0); |
373 | for (i = IMX_GPIO_NR(3, 1); i < IMX_GPIO_NR(3, 7); i++) | |
4c0443c4 | 374 | gpio_direction_output(i, 0); |
f8f8acd7 | 375 | |
6ea4217f | 376 | gpio_direction_output(IMX_GPIO_NR(3, 30), 0); |
f8f8acd7 SB |
377 | |
378 | /* Set POWER_OFF high */ | |
6ea4217f | 379 | gpio_direction_output(IMX_GPIO_NR(3, 27), 1); |
f8f8acd7 | 380 | |
6ea4217f | 381 | gpio_direction_output(IMX_GPIO_NR(3, 26), 0); |
f8f8acd7 | 382 | |
6ea4217f | 383 | gpio_direction_output(IMX_GPIO_NR(4, 26), 0); |
f8f8acd7 | 384 | |
6ea4217f | 385 | gpio_direction_output(IMX_GPIO_NR(4, 25), 1); |
f8f8acd7 SB |
386 | |
387 | WATCHDOG_RESET(); | |
388 | } | |
389 | ||
390 | static void setup_fec(void) | |
391 | { | |
6ea4217f BT |
392 | static const iomux_v3_cfg_t fec_pads[] = { |
393 | NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS | | |
394 | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | | |
395 | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), | |
396 | MX51_PAD_NANDF_CS3__FEC_MDC, | |
397 | NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2), | |
398 | NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2), | |
399 | NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2), | |
400 | MX51_PAD_NANDF_D9__FEC_RDATA0, | |
401 | MX51_PAD_NANDF_CS6__FEC_TDATA3, | |
402 | MX51_PAD_NANDF_CS5__FEC_TDATA2, | |
403 | MX51_PAD_NANDF_CS4__FEC_TDATA1, | |
404 | MX51_PAD_NANDF_D8__FEC_TDATA0, | |
405 | MX51_PAD_NANDF_CS7__FEC_TX_EN, | |
406 | MX51_PAD_NANDF_CS2__FEC_TX_ER, | |
407 | MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, | |
408 | NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4), | |
409 | NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4), | |
410 | MX51_PAD_EIM_CS5__FEC_CRS, | |
411 | MX51_PAD_EIM_CS4__FEC_RX_ER, | |
412 | NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4), | |
413 | }; | |
414 | ||
415 | imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); | |
f8f8acd7 SB |
416 | } |
417 | ||
418 | struct fsl_esdhc_cfg esdhc_cfg[1] = { | |
16e43f35 | 419 | {MMC_SDHC1_BASE_ADDR}, |
f8f8acd7 SB |
420 | }; |
421 | ||
422 | int get_mmc_getcd(u8 *cd, struct mmc *mmc) | |
423 | { | |
424 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; | |
425 | ||
426 | if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) | |
6ea4217f | 427 | *cd = gpio_get_value(IMX_GPIO_NR(1, 0)); |
f8f8acd7 SB |
428 | else |
429 | *cd = 0; | |
430 | ||
431 | return 0; | |
432 | } | |
433 | ||
434 | #ifdef CONFIG_FSL_ESDHC | |
435 | int board_mmc_init(bd_t *bis) | |
436 | { | |
6ea4217f BT |
437 | static const iomux_v3_cfg_t sd1_pads[] = { |
438 | NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX | | |
439 | PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), | |
440 | NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX | | |
441 | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), | |
442 | NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX | | |
443 | PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), | |
444 | NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX | | |
445 | PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), | |
446 | NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX | | |
447 | PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), | |
448 | NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX | | |
449 | PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST), | |
450 | NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS), | |
451 | NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS), | |
452 | }; | |
453 | ||
454 | imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads)); | |
f8f8acd7 | 455 | |
a2ac1b3a | 456 | esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
f8f8acd7 SB |
457 | return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); |
458 | } | |
459 | #endif | |
460 | ||
e9934f0b SB |
461 | void lcd_enable(void) |
462 | { | |
6ea4217f BT |
463 | static const iomux_v3_cfg_t lcd_pads[] = { |
464 | MX51_PAD_DI1_PIN2__DI1_PIN2, | |
465 | MX51_PAD_DI1_PIN3__DI1_PIN3, | |
466 | }; | |
467 | ||
e9934f0b SB |
468 | int ret; |
469 | ||
6ea4217f | 470 | imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); |
e9934f0b | 471 | |
6ea4217f BT |
472 | gpio_set_value(IMX_GPIO_NR(1, 2), 1); |
473 | imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_2__GPIO1_2, | |
474 | NO_PAD_CTRL)); | |
e9934f0b | 475 | |
a1b0e190 | 476 | ret = ipuv3_fb_init(&nec_nl6448bc26_09c, 0, IPU_PIX_FMT_RGB666); |
e9934f0b SB |
477 | if (ret) |
478 | puts("LCD cannot be configured\n"); | |
479 | } | |
480 | ||
f8f8acd7 SB |
481 | int board_early_init_f(void) |
482 | { | |
483 | ||
484 | ||
485 | init_drive_strength(); | |
486 | ||
487 | /* Setup debug led */ | |
6ea4217f BT |
488 | gpio_direction_output(IMX_GPIO_NR(1, 6), 0); |
489 | imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, | |
490 | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST)); | |
f8f8acd7 SB |
491 | |
492 | /* wait a little while to give the pll time to settle */ | |
493 | sdelay(100000); | |
494 | ||
495 | setup_weim(); | |
496 | setup_uart(); | |
497 | setup_fec(); | |
498 | setup_gpios(); | |
499 | ||
500 | spi_io_init(); | |
501 | ||
502 | return 0; | |
503 | } | |
504 | ||
a0152c4b SB |
505 | static void backlight(int on) |
506 | { | |
507 | if (on) { | |
6ea4217f | 508 | gpio_set_value(IMX_GPIO_NR(3, 1), 1); |
a0152c4b | 509 | udelay(10000); |
6ea4217f | 510 | gpio_set_value(IMX_GPIO_NR(3, 4), 1); |
a0152c4b | 511 | } else { |
6ea4217f BT |
512 | gpio_set_value(IMX_GPIO_NR(3, 1), 0); |
513 | gpio_set_value(IMX_GPIO_NR(3, 4), 0); | |
a0152c4b SB |
514 | } |
515 | } | |
516 | ||
f8f8acd7 SB |
517 | int board_init(void) |
518 | { | |
f8f8acd7 SB |
519 | /* address of boot parameters */ |
520 | gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; | |
521 | ||
e9934f0b SB |
522 | lcd_enable(); |
523 | ||
524 | backlight(1); | |
525 | ||
f8f8acd7 SB |
526 | return 0; |
527 | } | |
528 | ||
529 | int board_late_init(void) | |
530 | { | |
531 | power_init_mx51(); | |
532 | ||
533 | reset_peripherals(1); | |
534 | udelay(2000); | |
535 | reset_peripherals(0); | |
536 | udelay(2000); | |
537 | ||
538 | /* Early revisions require a second reset */ | |
539 | #ifdef CONFIG_VISION2_HW_1_0 | |
540 | reset_peripherals(1); | |
541 | udelay(2000); | |
542 | reset_peripherals(0); | |
543 | udelay(2000); | |
544 | #endif | |
545 | ||
546 | return 0; | |
547 | } | |
548 | ||
fca37fcd FE |
549 | /* |
550 | * Do not overwrite the console | |
551 | * Use always serial for U-Boot console | |
552 | */ | |
553 | int overwrite_console(void) | |
554 | { | |
555 | return 1; | |
556 | } | |
557 | ||
f8f8acd7 SB |
558 | int checkboard(void) |
559 | { | |
51958904 | 560 | puts("Board: TTControl Vision II CPU V\n"); |
f8f8acd7 SB |
561 | |
562 | return 0; | |
563 | } | |
564 | ||
a0152c4b SB |
565 | int do_vision_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
566 | { | |
567 | int on; | |
568 | ||
569 | if (argc < 2) | |
570 | return cmd_usage(cmdtp); | |
571 | ||
572 | on = (strcmp(argv[1], "on") == 0); | |
573 | backlight(on); | |
574 | ||
575 | return 0; | |
576 | } | |
577 | ||
578 | U_BOOT_CMD( | |
579 | lcdbl, CONFIG_SYS_MAXARGS, 1, do_vision_lcd, | |
580 | "Vision2 Backlight", | |
581 | "lcdbl [on|off]\n" | |
582 | ); |