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6ce89324 YY |
1 | /* |
2 | * mux.c | |
3 | * | |
a94a4071 | 4 | * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ |
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5 | * |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation version 2. | |
9 | * | |
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
11 | * kind, whether express or implied; without even the implied warranty | |
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
d678a59d | 16 | #include <common.h> |
6ce89324 YY |
17 | #include <asm/arch/sys_proto.h> |
18 | #include <asm/arch/hardware.h> | |
19 | #include <asm/arch/mux.h> | |
20 | #include <asm/io.h> | |
21 | #include <i2c.h> | |
22 | #include "board.h" | |
23 | ||
24 | static struct module_pin_mux uart0_pin_mux[] = { | |
25 | {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ | |
26 | {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ | |
27 | {-1}, | |
28 | }; | |
29 | ||
6ce89324 YY |
30 | static struct module_pin_mux mmc0_pin_mux[] = { |
31 | {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ | |
32 | {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ | |
33 | {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ | |
34 | {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ | |
35 | {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ | |
36 | {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ | |
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37 | {-1}, |
38 | }; | |
39 | ||
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40 | static struct module_pin_mux i2c1_pin_mux[] = { |
41 | {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | | |
42 | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ | |
43 | {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | | |
44 | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ | |
45 | {-1}, | |
46 | }; | |
47 | ||
6ce89324 YY |
48 | static struct module_pin_mux rmii1_pin_mux[] = { |
49 | {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ | |
50 | {OFFSET(mii1_txen), MODE(1)}, /* RGMII1_TCTL */ | |
51 | {OFFSET(mii1_txd1), MODE(1)}, /* RGMII1_TCTL */ | |
52 | {OFFSET(mii1_txd0), MODE(1)}, /* RGMII1_TCTL */ | |
53 | {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ | |
54 | {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ | |
55 | {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RGMII1_TCTL */ | |
56 | {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ | |
57 | {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ | |
58 | {-1}, | |
59 | }; | |
60 | ||
61 | static struct module_pin_mux rgmii2_pin_mux[] = { | |
62 | {OFFSET(gpmc_a0), MODE(2)}, /* RGMII1_TCTL */ | |
63 | {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ | |
64 | {OFFSET(gpmc_a2), MODE(2)}, /* RGMII1_TD3 */ | |
65 | {OFFSET(gpmc_a3), MODE(2)}, /* RGMII1_TD2 */ | |
66 | {OFFSET(gpmc_a4), MODE(2)}, /* RGMII1_TD1 */ | |
67 | {OFFSET(gpmc_a5), MODE(2)}, /* RGMII1_TD0 */ | |
68 | {OFFSET(gpmc_a6), MODE(2)}, /* RGMII1_TCLK */ | |
69 | {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ | |
70 | {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ | |
71 | {OFFSET(gpmc_a9), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ | |
72 | {OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ | |
73 | {OFFSET(gpmc_a11), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ | |
74 | {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ | |
75 | {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ | |
76 | {-1}, | |
77 | }; | |
78 | ||
79 | static struct module_pin_mux nand_pin_mux[] = { | |
80 | {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ | |
81 | {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ | |
82 | {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ | |
83 | {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ | |
84 | {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ | |
85 | {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ | |
86 | {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ | |
87 | {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ | |
88 | {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ | |
89 | {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ | |
90 | {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ | |
91 | {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ | |
92 | {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ | |
93 | {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ | |
94 | {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ | |
95 | {-1}, | |
96 | }; | |
97 | ||
98 | void enable_uart0_pin_mux(void) | |
99 | { | |
100 | configure_module_pin_mux(uart0_pin_mux); | |
101 | } | |
102 | ||
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103 | void enable_i2c1_pin_mux(void) |
104 | { | |
105 | configure_module_pin_mux(i2c1_pin_mux); | |
106 | } | |
107 | ||
108 | void enable_board_pin_mux() | |
109 | { | |
6ce89324 | 110 | configure_module_pin_mux(i2c1_pin_mux); |
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111 | configure_module_pin_mux(rgmii2_pin_mux); |
112 | configure_module_pin_mux(rmii1_pin_mux); | |
113 | configure_module_pin_mux(mmc0_pin_mux); | |
114 | ||
88718be3 | 115 | #if defined(CONFIG_MTD_RAW_NAND) |
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116 | configure_module_pin_mux(nand_pin_mux); |
117 | #endif | |
118 | } |