[people/ms/u-boot.git] / board / xaeniax / lowlevel_init.S

 /*
 * Most of this taken from Redboot hal_platform_setup.h with cleanup
 *
 * NOTE: I haven't clean this up considerably, just enough to get it
 * running. See hal_platform_setup.h for the source. See
 * board/cradle/lowlevel_init.S for another PXA250 setup that is
 * much cleaner.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <version.h>
#include <asm/arch/pxa-regs.h>

DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE

/* wait for coprocessor write complete */
	.macro CPWAIT reg
	mrc  p15,0,\reg,c2,c0,0
	mov  \reg,\reg
	sub  pc,pc,#4
	.endm


.globl lowlevel_init
lowlevel_init:

	mov	 r10, lr

	/* Set up GPIO pins first ----------------------------------------- */

	ldr	r0,=GPSR0
	ldr	r1,=CONFIG_SYS_GPSR0_VAL
	str	r1,[r0]

	ldr	r0,=GPSR1
	ldr	r1,=CONFIG_SYS_GPSR1_VAL
	str	r1,[r0]

	ldr	r0,=GPSR2
	ldr	r1,=CONFIG_SYS_GPSR2_VAL
	str	r1,[r0]

	ldr	r0,=GPCR0
	ldr	r1,=CONFIG_SYS_GPCR0_VAL
	str	r1,[r0]

	ldr	r0,=GPCR1
	ldr	r1,=CONFIG_SYS_GPCR1_VAL
	str	r1,[r0]

	ldr	r0,=GPCR2
	ldr	r1,=CONFIG_SYS_GPCR2_VAL
	str	r1,[r0]

	ldr	r0,=GPDR0
	ldr	r1,=CONFIG_SYS_GPDR0_VAL
	str	r1,[r0]

	ldr	r0,=GPDR1
	ldr	r1,=CONFIG_SYS_GPDR1_VAL
	str	r1,[r0]

	ldr	r0,=GPDR2
	ldr	r1,=CONFIG_SYS_GPDR2_VAL
	str	r1,[r0]

	ldr	r0,=GAFR0_L
	ldr	r1,=CONFIG_SYS_GAFR0_L_VAL
	str	r1,[r0]

	ldr	r0,=GAFR0_U
	ldr	r1,=CONFIG_SYS_GAFR0_U_VAL
	str	r1,[r0]

	ldr	r0,=GAFR1_L
	ldr	r1,=CONFIG_SYS_GAFR1_L_VAL
	str	r1,[r0]

	ldr	r0,=GAFR1_U
	ldr	r1,=CONFIG_SYS_GAFR1_U_VAL
	str	r1,[r0]

	ldr	r0,=GAFR2_L
	ldr	r1,=CONFIG_SYS_GAFR2_L_VAL
	str	r1,[r0]

	ldr	r0,=GAFR2_U
	ldr	r1,=CONFIG_SYS_GAFR2_U_VAL
	str	r1,[r0]

	ldr	r0,=PSSR		/* enable GPIO pins */
	ldr	r1,=CONFIG_SYS_PSSR_VAL
	str	r1,[r0]

	/* ---------------------------------------------------------------- */
	/* Enable memory interface                                          */
	/*                                                                  */
	/* The sequence below is based on the recommended init steps        */
	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
	/* Chapter 10.                                                      */
	/* ---------------------------------------------------------------- */

	/* ---------------------------------------------------------------- */
	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
	/*         clocks to settle. Only necessary after hard reset...     */
	/*         FIXME: can be optimized later                            */
	/* ---------------------------------------------------------------- */

	ldr	r3, =OSCR		/* reset the OS Timer Count to zero */
	mov	r2, #0
	str	r2, [r3]
	ldr	r4, =0x300		/* really 0x2E1 is about 200usec,   */
					/* so 0x300 should be plenty        */
1:
	ldr	r2, [r3]
	cmp	r4, r2
	bgt	1b

mem_init:

	ldr	r1,=MEMC_BASE		/* get memory controller base addr. */

	/* ---------------------------------------------------------------- */
	/* Step 2a: Initialize Asynchronous static memory controller        */
	/* ---------------------------------------------------------------- */

	/* MSC registers: timing, bus width, mem type                       */

	/* MSC0: nCS(0,1)                                                   */
	ldr     r2,=CONFIG_SYS_MSC0_VAL
	str     r2,[r1, #MSC0_OFFSET]
	ldr     r2,[r1, #MSC0_OFFSET]	/* read back to ensure data latches */

	/* MSC1: nCS(2,3)                                                   */
	ldr     r2,=CONFIG_SYS_MSC1_VAL
	str     r2,[r1, #MSC1_OFFSET]
	ldr     r2,[r1, #MSC1_OFFSET]

	/* MSC2: nCS(4,5)                                                   */
	ldr     r2,=CONFIG_SYS_MSC2_VAL
	str     r2,[r1, #MSC2_OFFSET]
	ldr     r2,[r1, #MSC2_OFFSET]

	/* ---------------------------------------------------------------- */
	/* Step 2b: Initialize Card Interface                               */
	/* ---------------------------------------------------------------- */

	/* MECR: Memory Expansion Card Register                             */
	ldr     r2,=CONFIG_SYS_MECR_VAL
	str     r2,[r1, #MECR_OFFSET]
	ldr	r2,[r1, #MECR_OFFSET]

	/* MCMEM0: Card Interface slot 0 timing                             */
	ldr     r2,=CONFIG_SYS_MCMEM0_VAL
	str     r2,[r1, #MCMEM0_OFFSET]
	ldr	r2,[r1, #MCMEM0_OFFSET]

	/* MCMEM1: Card Interface slot 1 timing                             */
	ldr     r2,=CONFIG_SYS_MCMEM1_VAL
	str     r2,[r1, #MCMEM1_OFFSET]
	ldr	r2,[r1, #MCMEM1_OFFSET]

	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
	ldr     r2,=CONFIG_SYS_MCATT0_VAL
	str     r2,[r1, #MCATT0_OFFSET]
	ldr	r2,[r1, #MCATT0_OFFSET]

	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
	ldr     r2,=CONFIG_SYS_MCATT1_VAL
	str     r2,[r1, #MCATT1_OFFSET]
	ldr	r2,[r1, #MCATT1_OFFSET]

	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
	ldr     r2,=CONFIG_SYS_MCIO0_VAL
	str     r2,[r1, #MCIO0_OFFSET]
	ldr	r2,[r1, #MCIO0_OFFSET]

	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
	ldr     r2,=CONFIG_SYS_MCIO1_VAL
	str     r2,[r1, #MCIO1_OFFSET]
	ldr	r2,[r1, #MCIO1_OFFSET]

	/* ---------------------------------------------------------------- */
	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
	/* ---------------------------------------------------------------- */

	/* ---------------------------------------------------------------- */
	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
	/* ---------------------------------------------------------------- */

	@ get the mdrefr settings
	ldr     r4,=CONFIG_SYS_MDREFR_VAL

	@ write back mdrefr
	str     r4,[r1, #MDREFR_OFFSET]
	ldr     r4,[r1, #MDREFR_OFFSET]

	/* ---------------------------------------------------------------- */
	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
	/* ---------------------------------------------------------------- */

	/* Initialize SXCNFG register. Assert the enable bits               */

	/* Write SXMRS to cause an MRS command to all enabled banks of      */
	/* synchronous static memory. Note that SXLCR need not be written   */
	/* at this time.                                                    */

	/* FIXME: we use async mode for now                                 */

	/* ---------------------------------------------------------------- */
	/* Step 4: Initialize SDRAM                                         */
	/* ---------------------------------------------------------------- */

	@ set K1RUN for bank 0
	@
	orr   r4,  r4,  #MDREFR_K1RUN

	@ write back mdrefr
	@
	str     r4,  [r1, #MDREFR_OFFSET]
	ldr     r4,  [r1, #MDREFR_OFFSET]

	@ deassert SLFRSH
	@
	bic     r4,  r4,  #MDREFR_SLFRSH

	@ write back mdrefr
	@
	str     r4,  [r1, #MDREFR_OFFSET]
	ldr     r4,  [r1, #MDREFR_OFFSET]

	@ assert E1PIN
	@ if E0PIN is also used:	 #(MDREFR_E1PIN|MDREFR_E0PIN)
	orr     r4,  r4, #(MDREFR_E1PIN)

	@ write back mdrefr
	@
	str     r4,  [r1, #MDREFR_OFFSET]
	ldr     r4,  [r1, #MDREFR_OFFSET]
	nop
	nop

	/* Step 4d:							*/
	/* fetch platform value of mdcnfg				*/
	@
	ldr     r2,  =CONFIG_SYS_MDCNFG_VAL

	@ disable all sdram banks
	@
	bic     r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
	bic     r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)

	@ program banks 0/1 for bus width
	@
	bic   r2,  r2,  #MDCNFG_DWID0      @0=32-bit

	@ write initial value of mdcnfg, w/o enabling sdram banks
	@
	str     r2,  [r1, #MDCNFG_OFFSET]

	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
Commit	Line	Data
4ec3a7f0 WD	1	/*
	2	* Most of this taken from Redboot hal_platform_setup.h with cleanup
	3	*
	4	* NOTE: I haven't clean this up considerably, just enough to get it
	5	* running. See hal_platform_setup.h for the source. See
400558b5	6	* board/cradle/lowlevel_init.S for another PXA250 setup that is
4ec3a7f0 WD	7	* much cleaner.
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#include <config.h>
	29	#include <version.h>
	30	#include <asm/arch/pxa-regs.h>
	31
6d0f6bcf	32	DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
4ec3a7f0 WD	33
	34	/* wait for coprocessor write complete */
	35	.macro CPWAIT reg
	36	mrc p15,0,\reg,c2,c0,0
	37	mov \reg,\reg
	38	sub pc,pc,#4
	39	.endm
	40
	41
400558b5 WD	42	.globl lowlevel_init
400558b5 WD	43	lowlevel_init:
4ec3a7f0 WD	44
	45	mov r10, lr
	46
	47	/* Set up GPIO pins first ----------------------------------------- */
	48
	49	ldr r0,=GPSR0
6d0f6bcf	50	ldr r1,=CONFIG_SYS_GPSR0_VAL
4ec3a7f0 WD	51	str r1,[r0]
	52
	53	ldr r0,=GPSR1
6d0f6bcf	54	ldr r1,=CONFIG_SYS_GPSR1_VAL
4ec3a7f0 WD	55	str r1,[r0]
	56
	57	ldr r0,=GPSR2
6d0f6bcf	58	ldr r1,=CONFIG_SYS_GPSR2_VAL
4ec3a7f0 WD	59	str r1,[r0]
	60
	61	ldr r0,=GPCR0
6d0f6bcf	62	ldr r1,=CONFIG_SYS_GPCR0_VAL
4ec3a7f0 WD	63	str r1,[r0]
	64
	65	ldr r0,=GPCR1
6d0f6bcf	66	ldr r1,=CONFIG_SYS_GPCR1_VAL
4ec3a7f0 WD	67	str r1,[r0]
	68
	69	ldr r0,=GPCR2
6d0f6bcf	70	ldr r1,=CONFIG_SYS_GPCR2_VAL
4ec3a7f0 WD	71	str r1,[r0]
	72
	73	ldr r0,=GPDR0
6d0f6bcf	74	ldr r1,=CONFIG_SYS_GPDR0_VAL
4ec3a7f0 WD	75	str r1,[r0]
	76
	77	ldr r0,=GPDR1
6d0f6bcf	78	ldr r1,=CONFIG_SYS_GPDR1_VAL
4ec3a7f0 WD	79	str r1,[r0]
	80
	81	ldr r0,=GPDR2
6d0f6bcf	82	ldr r1,=CONFIG_SYS_GPDR2_VAL
4ec3a7f0 WD	83	str r1,[r0]
	84
	85	ldr r0,=GAFR0_L
6d0f6bcf	86	ldr r1,=CONFIG_SYS_GAFR0_L_VAL
4ec3a7f0 WD	87	str r1,[r0]
	88
	89	ldr r0,=GAFR0_U
6d0f6bcf	90	ldr r1,=CONFIG_SYS_GAFR0_U_VAL
4ec3a7f0 WD	91	str r1,[r0]
	92
	93	ldr r0,=GAFR1_L
6d0f6bcf	94	ldr r1,=CONFIG_SYS_GAFR1_L_VAL
4ec3a7f0 WD	95	str r1,[r0]
	96
	97	ldr r0,=GAFR1_U
6d0f6bcf	98	ldr r1,=CONFIG_SYS_GAFR1_U_VAL
4ec3a7f0 WD	99	str r1,[r0]
	100
	101	ldr r0,=GAFR2_L
6d0f6bcf	102	ldr r1,=CONFIG_SYS_GAFR2_L_VAL
4ec3a7f0 WD	103	str r1,[r0]
	104
	105	ldr r0,=GAFR2_U
6d0f6bcf	106	ldr r1,=CONFIG_SYS_GAFR2_U_VAL
4ec3a7f0 WD	107	str r1,[r0]
	108
	109	ldr r0,=PSSR /* enable GPIO pins */
6d0f6bcf	110	ldr r1,=CONFIG_SYS_PSSR_VAL
4ec3a7f0 WD	111	str r1,[r0]
	112
	113	/* ---------------------------------------------------------------- */
	114	/* Enable memory interface */
	115	/* */
	116	/* The sequence below is based on the recommended init steps */
	117	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
	118	/* Chapter 10. */
	119	/* ---------------------------------------------------------------- */
	120
	121	/* ---------------------------------------------------------------- */
	122	/* Step 1: Wait for at least 200 microsedonds to allow internal */
	123	/* clocks to settle. Only necessary after hard reset... */
	124	/* FIXME: can be optimized later */
	125	/* ---------------------------------------------------------------- */
	126
	127	ldr r3, =OSCR /* reset the OS Timer Count to zero */
	128	mov r2, #0
	129	str r2, [r3]
	130	ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
	131	/* so 0x300 should be plenty */
	132	1:
	133	ldr r2, [r3]
	134	cmp r4, r2
	135	bgt 1b
	136
	137	mem_init:
	138
	139	ldr r1,=MEMC_BASE /* get memory controller base addr. */
	140
	141	/* ---------------------------------------------------------------- */
	142	/* Step 2a: Initialize Asynchronous static memory controller */
	143	/* ---------------------------------------------------------------- */
	144
	145	/* MSC registers: timing, bus width, mem type */
	146
	147	/* MSC0: nCS(0,1) */
6d0f6bcf	148	ldr r2,=CONFIG_SYS_MSC0_VAL
4ec3a7f0 WD	149	str r2,[r1, #MSC0_OFFSET]
	150	ldr r2,[r1, #MSC0_OFFSET] /* read back to ensure data latches */
	151
	152	/* MSC1: nCS(2,3) */
6d0f6bcf	153	ldr r2,=CONFIG_SYS_MSC1_VAL
4ec3a7f0 WD	154	str r2,[r1, #MSC1_OFFSET]
	155	ldr r2,[r1, #MSC1_OFFSET]
	156
	157	/* MSC2: nCS(4,5) */
6d0f6bcf	158	ldr r2,=CONFIG_SYS_MSC2_VAL
4ec3a7f0 WD	159	str r2,[r1, #MSC2_OFFSET]
	160	ldr r2,[r1, #MSC2_OFFSET]
	161
	162	/* ---------------------------------------------------------------- */
	163	/* Step 2b: Initialize Card Interface */
	164	/* ---------------------------------------------------------------- */
	165
	166	/* MECR: Memory Expansion Card Register */
6d0f6bcf	167	ldr r2,=CONFIG_SYS_MECR_VAL
4ec3a7f0 WD	168	str r2,[r1, #MECR_OFFSET]
	169	ldr r2,[r1, #MECR_OFFSET]
	170
	171	/* MCMEM0: Card Interface slot 0 timing */
6d0f6bcf	172	ldr r2,=CONFIG_SYS_MCMEM0_VAL
4ec3a7f0 WD	173	str r2,[r1, #MCMEM0_OFFSET]
	174	ldr r2,[r1, #MCMEM0_OFFSET]
	175
	176	/* MCMEM1: Card Interface slot 1 timing */
6d0f6bcf	177	ldr r2,=CONFIG_SYS_MCMEM1_VAL
4ec3a7f0 WD	178	str r2,[r1, #MCMEM1_OFFSET]
	179	ldr r2,[r1, #MCMEM1_OFFSET]
	180
	181	/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
6d0f6bcf	182	ldr r2,=CONFIG_SYS_MCATT0_VAL
4ec3a7f0 WD	183	str r2,[r1, #MCATT0_OFFSET]
	184	ldr r2,[r1, #MCATT0_OFFSET]
	185
	186	/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
6d0f6bcf	187	ldr r2,=CONFIG_SYS_MCATT1_VAL
4ec3a7f0 WD	188	str r2,[r1, #MCATT1_OFFSET]
	189	ldr r2,[r1, #MCATT1_OFFSET]
	190
	191	/* MCIO0: Card Interface I/O Space Timing, slot 0 */
6d0f6bcf	192	ldr r2,=CONFIG_SYS_MCIO0_VAL
4ec3a7f0 WD	193	str r2,[r1, #MCIO0_OFFSET]
	194	ldr r2,[r1, #MCIO0_OFFSET]
	195
	196	/* MCIO1: Card Interface I/O Space Timing, slot 1 */
6d0f6bcf	197	ldr r2,=CONFIG_SYS_MCIO1_VAL
4ec3a7f0 WD	198	str r2,[r1, #MCIO1_OFFSET]
	199	ldr r2,[r1, #MCIO1_OFFSET]
	200
	201	/* ---------------------------------------------------------------- */
	202	/* Step 2c: Write FLYCNFG FIXME: what's that??? */
	203	/* ---------------------------------------------------------------- */
	204
	205	/* ---------------------------------------------------------------- */
	206	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
	207	/* ---------------------------------------------------------------- */
	208
	209	@ get the mdrefr settings
6d0f6bcf	210	ldr r4,=CONFIG_SYS_MDREFR_VAL
4ec3a7f0 WD	211
	212	@ write back mdrefr
	213	str r4,[r1, #MDREFR_OFFSET]
	214	ldr r4,[r1, #MDREFR_OFFSET]
	215
	216	/* ---------------------------------------------------------------- */
	217	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
	218	/* ---------------------------------------------------------------- */
	219
	220	/* Initialize SXCNFG register. Assert the enable bits */
	221
	222	/* Write SXMRS to cause an MRS command to all enabled banks of */
	223	/* synchronous static memory. Note that SXLCR need not be written */
	224	/* at this time. */
	225
	226	/* FIXME: we use async mode for now */
	227
	228	/* ---------------------------------------------------------------- */
	229	/* Step 4: Initialize SDRAM */
	230	/* ---------------------------------------------------------------- */
	231
	232	@ set K1RUN for bank 0
	233	@
	234	orr r4, r4, #MDREFR_K1RUN
	235
	236	@ write back mdrefr
	237	@
	238	str r4, [r1, #MDREFR_OFFSET]
	239	ldr r4, [r1, #MDREFR_OFFSET]
	240
	241	@ deassert SLFRSH
	242	@
	243	bic r4, r4, #MDREFR_SLFRSH
	244
	245	@ write back mdrefr
	246	@
	247	str r4, [r1, #MDREFR_OFFSET]
	248	ldr r4, [r1, #MDREFR_OFFSET]
	249
	250	@ assert E1PIN
	251	@ if E0PIN is also used: #(MDREFR_E1PIN\|MDREFR_E0PIN)
	252	orr r4, r4, #(MDREFR_E1PIN)
	253
	254	@ write back mdrefr
	255	@
	256	str r4, [r1, #MDREFR_OFFSET]
	257	ldr r4, [r1, #MDREFR_OFFSET]
	258	nop
	259	nop
	260
	261	/* Step 4d: */
	262	/* fetch platform value of mdcnfg */
	263	@
6d0f6bcf	264	ldr r2, =CONFIG_SYS_MDCNFG_VAL
4ec3a7f0 WD	265
	266	@ disable all sdram banks
	267	@
	268	bic r2, r2, #(MDCNFG_DE0 \| MDCNFG_DE1)
	269	bic r2, r2, #(MDCNFG_DE2 \| MDCNFG_DE3)
	270
	271	@ program banks 0/1 for bus width
	272	@
	273	bic r2, r2, #MDCNFG_DWID0 @0=32-bit
	274
	275	@ write initial value of mdcnfg, w/o enabling sdram banks
	276	@
	277	str r2, [r1, #MDCNFG_OFFSET]
	278
	279	/* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
	280