[people/ms/u-boot.git] / board / xes / xpedite520x / ddr.c

/*
 * Copyright 2008 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * Version 2 as published by the Free Software Foundation.
 */

#include <common.h>
#include <i2c.h>

#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>

static void
get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
{
	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));

	/* We use soldered memory, but use an SPD EEPROM to describe it.
	 * The SPD has an unspecified dimm type, but the DDR2 initialization
	 * code requires a specific type to be specified. This sets the type
	 * as a standard unregistered SO-DIMM. */
	if (spd->dimm_type == 0) {
		spd->dimm_type = 0x4;
		((uchar *)spd)[63] += 0x4;
	}
}

unsigned int fsl_ddr_get_mem_data_rate(void)
{
	return get_ddr_freq(0);
}

void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
			unsigned int ctrl_num)
{
	unsigned int i;

	if (ctrl_num) {
		printf("%s: invalid ctrl_num = %d\n", __func__, ctrl_num);
		return;
	}

	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++)
		get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
}

void fsl_ddr_board_options(memctl_options_t *popts,
				dimm_params_t *pdimm,
				unsigned int ctrl_num)
{
	/*
	 * Factors to consider for clock adjust:
	 *	- number of chips on bus
	 *	- position of slot
	 *	- DDR1 vs. DDR2?
	 *	- ???
	 *
	 * This needs to be determined on a board-by-board basis.
	 *	0110	3/4 cycle late
	 *	0111	7/8 cycle late
	 */
	popts->clk_adjust = 7;

	/*
	 * Factors to consider for CPO:
	 *	- frequency
	 *	- ddr1 vs. ddr2
	 */
	popts->cpo_override = 9;

	/*
	 * Factors to consider for write data delay:
	 *	- number of DIMMs
	 *
	 * 1 = 1/4 clock delay
	 * 2 = 1/2 clock delay
	 * 3 = 3/4 clock delay
	 * 4 = 1   clock delay
	 * 5 = 5/4 clock delay
	 * 6 = 3/2 clock delay
	 */
	popts->write_data_delay = 3;

	/*
	 * Factors to consider for half-strength driver enable:
	 *	- number of DIMMs installed
	 */
	popts->half_strength_driver_enable = 0;
}
Commit	Line	Data
1f03cbfa PT	1	/*
	2	* Copyright 2008 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* Version 2 as published by the Free Software Foundation.
	7	*/
	8
	9	#include <common.h>
	10	#include <i2c.h>
	11
	12	#include <asm/fsl_ddr_sdram.h>
	13	#include <asm/fsl_ddr_dimm_params.h>
	14
	15	static void
	16	get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
	17	{
	18	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
	19
	20	/* We use soldered memory, but use an SPD EEPROM to describe it.
	21	* The SPD has an unspecified dimm type, but the DDR2 initialization
	22	* code requires a specific type to be specified. This sets the type
	23	* as a standard unregistered SO-DIMM. */
	24	if (spd->dimm_type == 0) {
	25	spd->dimm_type = 0x4;
	26	((uchar *)spd)[63] += 0x4;
	27	}
	28	}
	29
	30	unsigned int fsl_ddr_get_mem_data_rate(void)
	31	{
	32	return get_ddr_freq(0);
	33	}
	34
	35	void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
	36	unsigned int ctrl_num)
	37	{
	38	unsigned int i;
	39
	40	if (ctrl_num) {
	41	printf("%s: invalid ctrl_num = %d\n", __func__, ctrl_num);
	42	return;
	43	}
	44
	45	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++)
	46	get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
	47	}
	48
	49	void fsl_ddr_board_options(memctl_options_t *popts,
	50	dimm_params_t *pdimm,
	51	unsigned int ctrl_num)
	52	{
	53	/*
	54	* Factors to consider for clock adjust:
	55	* - number of chips on bus
	56	* - position of slot
	57	* - DDR1 vs. DDR2?
	58	* - ???
	59	*
	60	* This needs to be determined on a board-by-board basis.
	61	* 0110 3/4 cycle late
	62	* 0111 7/8 cycle late
	63	*/
	64	popts->clk_adjust = 7;
65
66	/*
67	* Factors to consider for CPO:
68	* - frequency
69	* - ddr1 vs. ddr2
70	*/
71	popts->cpo_override = 9;
72
73	/*
74	* Factors to consider for write data delay:
75	* - number of DIMMs
76	*
77	* 1 = 1/4 clock delay
78	* 2 = 1/2 clock delay
79	* 3 = 3/4 clock delay
80	* 4 = 1 clock delay
81	* 5 = 5/4 clock delay
82	* 6 = 3/2 clock delay
83	*/
84	popts->write_data_delay = 3;
85
86	/*
87	* Factors to consider for half-strength driver enable:
88	* - number of DIMMs installed
89	*/
90	popts->half_strength_driver_enable = 0;
91	}